1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
9 (S), and (I) IRC handle.
13 W: http://www.cs.uiuc.edu/~vadve/
14 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
18 D: LCSSA pass and related LoopUnswitch work
19 D: GVNPRE pass, DataLayout refactoring, random improvements
22 D: MingW Win32 API portability layer
25 E: aaron@aaronballman.com
26 D: Clang frontend, frontend attributes, Windows support, general bug fixing
30 E: natebegeman@mac.com
31 D: PowerPC backend developer
32 D: Target-independent code generator and analysis improvements
35 E: dberlin@dberlin.org
36 D: ET-Forest implementation.
40 E: gberry@codeaurora.org
42 D: AArch64 backend improvements
43 D: Added EarlyCSE MemorySSA support
44 D: CodeGen improvements
48 D: General bug fixing/fit & finish, mostly in Clang
51 E: neil@daikokuya.co.uk
52 D: APFloat implementation.
59 E: brukman+llvm@uiuc.edu
60 W: http://misha.brukman.net
61 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
62 D: Incremental bitcode loader
66 D: The `mem2reg' pass - promotes values stored in memory to registers
69 E: bcahoon@codeaurora.org
70 D: Loop unrolling with run-time trip counts.
73 E: chandlerc@gmail.com
74 E: chandlerc@google.com
75 D: Hashing algorithms and interfaces
76 D: Inline cost analysis
77 D: Machine block placement pass
82 D: Fixes to the Reassociation pass, various improvement patches
85 E: evan.cheng@apple.com
86 D: ARM and X86 backends
87 D: Instruction scheduler improvements
88 D: Register allocator improvements
89 D: Loop optimizer improvements
90 D: Target-independent code generator improvements
92 N: Dan Villiom Podlaski Christiansen
96 D: LLVM Makefile improvements
97 D: Clang diagnostic & driver tweaks
101 E: jeffc@jolt-lang.org
102 W: http://jolt-lang.org
103 D: Native Win32 API portability layer
107 D: Original Autoconf support, documentation improvements, bug fixes
110 E: adasgupt@codeaurora.org
111 D: Deterministic finite automaton based infrastructure for VLIW packetization
114 E: stefanus.du.toit@intel.com
115 D: Bug fixes and minor improvements
117 N: Rafael Avila de Espindola
122 E: cestes@codeaurora.org
123 D: AArch64 machine description for Cortex-A53
126 E: alkis@evlogimenos.com
127 D: Linear scan register allocator, many codegen improvements, Java frontend
131 D: Basic-block autovectorization, PowerPC backend improvements
135 D: LIT patches and documentation
138 E: pizza@parseerror.com
139 D: Miscellaneous bug fixes
143 W: http://www.students.uiuc.edu/~gaeke/
144 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
145 D: Dynamic trace optimizer
146 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
149 E: nicolas.geoffray@lip6.fr
150 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
151 D: PPC backend fixes for Linux
155 D: Portions of the PowerPC backend
158 E: saemghani@gmail.com
159 D: Callgraph class cleanups
161 N: Mikhail Glushenkov
162 E: foldr@codedgers.com
166 E: sunfish@mozilla.com
167 D: Miscellaneous bug fixes
168 D: WebAssembly Backend
171 E: rengolin@systemcall.eu
172 E: rengolin@gmail.com
173 D: ARM/AArch64 back-end improvements
174 D: Loop Vectorizer improvements
175 D: Regression and Test Suite improvements
176 D: Linux compatibility (GNU, musl, etc)
177 D: Initial Linux kernel / Android support effort
180 E: david@goodwinz.net
181 D: Thumb-2 code generator
184 E: greened@obbligato.org
185 D: Miscellaneous bug fixes
186 D: Register allocation refactoring
190 D: Improvements for space efficiency
193 E: grosbach@apple.com
195 D: SjLj exception handling support
196 D: General fixes and improvements for the ARM back-end
198 D: ARM integrated assembler and assembly parser
199 D: Led effort for the backend formerly known as ARM64
203 D: PBQP-based register allocator
206 E: gordonhenriksen@mac.com
207 D: Pluggable GC support
211 N: Raul Fernandes Herbster
212 E: raul@dsc.ufcg.edu.br
213 D: JIT support for ARM
216 E: arathorn@fastwebnet.it
217 D: Visual C++ compatibility fixes
220 E: patjenk@wam.umd.edu
223 N: Tony(Yanjun) Jiang
225 D: PowerPC Backend Developer
226 D: Improvements to the PPC backend and miscellaneous bug fixes
230 D: ARM constant islands improvements
231 D: Tail merging improvements
232 D: Rewrite X87 back end
233 D: Use APFloat for floating point constants widely throughout compiler
234 D: Implement X87 long double
237 E: kungfoomaster@nondot.org
238 D: Support for packed types
242 D: Author of LLVM Ada bindings
245 E: erich.keane@intel.com
246 D: A variety of Clang contributions including function multiversioning, regcall/vectorcall.
250 W: http://randomhacks.net/
251 D: llvm-config script
253 N: Anton Korobeynikov
254 E: anton at korobeynikov dot info
255 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
256 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
257 D: Switch lowering refactoring
261 D: Author of the original C backend
264 E: benny.kra@gmail.com
265 D: Miscellaneous bug fixes
268 E: sundeepk@codeaurora.org
269 D: Implemented DFA-based target independent VLIW packetizer
272 E: christopher.lamb@gmail.com
273 D: aligned load/store support, parts of noalias and restrict support
274 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
279 D: Improvements to the PPC backend, instruction scheduling
280 D: Debug and Dwarf implementation
281 D: Auto upgrade mangler
282 D: llvm-gcc4 svn wrangler
286 W: http://nondot.org/~sabre/
287 D: Primary architect of LLVM
289 N: Tanya Lattner (Tanya Brethour)
291 W: http://nondot.org/~tonic/
292 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
293 D: Modulo scheduling in the SparcV9 backend
294 D: Release manager (1.7+)
297 E: sylvestre@debian.org
298 W: http://sylvestre.ledru.info/
299 W: https://apt.llvm.org/
300 D: Debian and Ubuntu packaging
301 D: Continuous integration with jenkins
304 E: alenhar2@cs.uiuc.edu
305 W: http://www.lenharth.org/~andrewl/
307 D: Sampling based profiling
311 D: PredicateSimplifier pass
313 N: Tony Linthicum, et. al.
314 E: tlinth@codeaurora.org
315 D: Backend for Qualcomm's Hexagon VLIW processor.
317 N: Bruno Cardoso Lopes
318 E: bruno.cardoso@gmail.com
320 W: http://brunocardoso.cc
322 D: Random ARM integrated assembler and assembly parser improvements
323 D: General X86 AVX1 support
326 E: duraid@octopus.com.au
327 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
328 D: IA64 backend, BigBlock register allocator
331 E: rjmccall@apple.com
332 D: Clang semantic analysis and IR generation
335 E: michael.mccracken@gmail.com
336 D: Line number support for llvmgcc
338 N: Vladimir Merzliakov
340 D: Test suite fixes for FreeBSD
344 D: Added STI Cell SPU backend.
348 D: Support for implicit TLS model used with MS VC runtime
349 D: Dumping of Win64 EH structures
353 E: geek4civic@gmail.com
354 E: chapuni@hf.rim.or.jp
355 D: Maintaining the Git monorepo
356 W: https://github.com/llvm-project/
359 N: Edward O'Callaghan
360 E: eocallaghan@auroraux.org
361 W: http://www.auroraux.org
362 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
363 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
364 D: and error clean ups.
368 D: Visual C++ compatibility fixes
370 N: Jakob Stoklund Olesen
372 D: Machine code verifier
374 D: Fast register allocator
375 D: Greedy register allocator
382 E: piotr.padlewski@gmail.com
383 D: !invariant.group metadata and other intrinsics for devirtualization in clang
387 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
388 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
389 D: Optimizer improvements, Loop Index Split
392 E: apazos@codeaurora.org
393 D: Fixes and improvements to the AArch64 backend
396 E: peckw@wesleypeck.com
397 W: http://wesleypeck.com/
398 D: MicroBlaze backend
401 E: pichet2000@gmail.com
409 W: http://vladimir_prus.blogspot.com
411 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
414 E: kalle.rasikila@nokia.com
415 D: Some bugfixes to CellSPU
419 D: Cmake dependency chain and various bug fixes
422 E: alexr@leftfield.org
424 D: ARM calling conventions rewrite, hard float support
427 E: mcrosier@codeaurora.org
429 D: AArch64 fast instruction selection pass
430 D: Fixes and improvements to the ARM fast-isel pass
431 D: Fixes and improvements to the AArch64 backend
434 E: nadav.rotem@me.com
435 D: X86 code generation improvements, Loop Vectorizer, SLP Vectorizer
438 E: roman@codedgers.com
444 D: Ada support in llvm-gcc
446 D: Exception handling improvements
447 D: Type legalizer rewrite
451 D: Graph coloring register allocator for the Sparc64 backend
453 N: Arnold Schwaighofer
454 E: arnold.schwaighofer@gmail.com
455 D: Tail call optimization for the x86 backend
459 D: Miscellaneous bug fixes
462 E: ashukla@cs.uiuc.edu
465 N: Michael J. Spencer
466 E: bigcheesegs@gmail.com
467 D: Shepherding Windows COFF support into MC.
468 D: Lots of Windows stuff.
471 E: rspencer@reidspencer.com
472 W: http://reidspencer.com/
473 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
477 W: http://atoker.com/
478 D: C++ frontend next generation standards implementation
481 E: craig.topper@gmail.com
482 D: X86 codegen and disassembler improvements. AVX2 support.
485 E: edwintorok@gmail.com
486 D: Miscellaneous bug fixes
490 D: C++ bugs filed, and C++ front-end bug fixes.
494 D: Instruction Scheduling, ...
496 N: Lauro Ramos Venancio
497 E: lauro.venancio@indt.org.br
498 D: ARM backend improvements
499 D: Thread Local Storage implementation
503 E: isanbard@gmail.com
504 D: Release manager, IR Linker, LTO.
508 E: bob.wilson@acm.org
509 D: Advanced SIMD (NEON) support in the ARM backend.
513 D: PowerPC Backend Developer
516 E: hljhehlj@cn.ibm.com
517 D: PowerPC Backend Developer
521 D: PowerPC Backend Developer
524 E: shkzhang@cn.ibm.com
525 D: PowerPC Backend Developer