1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), and snail-mail address
14 W: http://www.cs.uiuc.edu/~vadve/
15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
19 D: LCSSA pass and related LoopUnswitch work
20 D: GVNPRE pass, TargetData refactoring, random improvements
23 D: MingW Win32 API portability layer
26 E: natebegeman@mac.com
27 D: PowerPC backend developer
28 D: Target-independent code generator and analysis improvements
31 E: dberlin@dberlin.org
32 D: ET-Forest implementation.
37 D: General bug fixing/fit & finish, mostly in Clang
40 E: neil@daikokuya.co.uk
41 D: APFloat implementation.
44 E: brukman+llvm@uiuc.edu
45 W: http://misha.brukman.net
46 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
47 D: Incremental bitcode loader
51 D: The `mem2reg' pass - promotes values stored in memory to registers
54 E: bcahoon@codeaurora.org
55 D: Loop unrolling with run-time trip counts.
58 E: chandlerc@gmail.com
59 D: LinkTimeOptimizer for Linux, via binutils integration, and C API
63 D: Fixes to the Reassociation pass, various improvement patches
66 E: evan.cheng@apple.com
67 D: ARM and X86 backends
68 D: Instruction scheduler improvements
69 D: Register allocator improvements
70 D: Loop optimizer improvements
71 D: Target-independent code generator improvements
73 N: Dan Villiom Podlaski Christiansen
77 D: LLVM Makefile improvements
78 D: Clang diagnostic & driver tweaks
82 E: jeffc@jolt-lang.org
83 W: http://jolt-lang.org
84 D: Native Win32 API portability layer
88 D: Original Autoconf support, documentation improvements, bug fixes
91 E: adasgupt@codeaurora.org
92 D: Deterministic finite automaton based infrastructure for VLIW packetization
95 E: stefanus.dutoit@rapidmind.com
96 D: Bug fixes and minor improvements
98 N: Rafael Avila de Espindola
99 E: rafael.espindola@gmail.com
103 E: alkis@evlogimenos.com
104 D: Linear scan register allocator, many codegen improvements, Java frontend
108 D: Basic-block autovectorization, PowerPC backend improvements
111 E: pizza@parseerror.com
112 D: Miscellaneous bug fixes
116 W: http://www.students.uiuc.edu/~gaeke/
117 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
118 D: Dynamic trace optimizer
119 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
122 E: nicolas.geoffray@lip6.fr
123 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
124 D: PPC backend fixes for Linux
127 D: Portions of the PowerPC backend
130 E: saemghani@gmail.com
131 D: Callgraph class cleanups
133 N: Mikhail Glushenkov
134 E: foldr@codedgers.com
139 D: Miscellaneous bug fixes
142 E: david@goodwinz.net
143 D: Thumb-2 code generator
146 E: greened@obbligato.org
147 D: Miscellaneous bug fixes
148 D: Register allocation refactoring
152 D: Improvements for space efficiency
155 E: grosbach@apple.com
156 D: SjLj exception handling support
157 D: General fixes and improvements for the ARM back-end
159 D: ARM integrated assembler and assembly parser
163 D: PBQP-based register allocator
166 E: gordonhenriksen@mac.com
167 D: Pluggable GC support
171 N: Raul Fernandes Herbster
172 E: raul@dsc.ufcg.edu.br
173 D: JIT support for ARM
176 E: arathorn@fastwebnet.it
177 D: Visual C++ compatibility fixes
180 E: patjenk@wam.umd.edu
185 D: ARM constant islands improvements
186 D: Tail merging improvements
187 D: Rewrite X87 back end
188 D: Use APFloat for floating point constants widely throughout compiler
189 D: Implement X87 long double
192 E: kungfoomaster@nondot.org
193 D: Support for packed types
197 D: Author of LLVM Ada bindings
200 W: http://randomhacks.net/
201 D: llvm-config script
203 N: Anton Korobeynikov
205 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
206 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
207 D: Switch lowering refactoring
211 D: Author of the original C backend
214 E: benny.kra@gmail.com
215 D: Miscellaneous bug fixes
218 E: christopher.lamb@gmail.com
219 D: aligned load/store support, parts of noalias and restrict support
220 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
225 D: Improvements to the PPC backend, instruction scheduling
226 D: Debug and Dwarf implementation
227 D: Auto upgrade mangler
228 D: llvm-gcc4 svn wrangler
232 W: http://nondot.org/~sabre/
233 D: Primary architect of LLVM
235 N: Tanya Lattner (Tanya Brethour)
237 W: http://nondot.org/~tonic/
238 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
239 D: Modulo scheduling in the SparcV9 backend
240 D: Release manager (1.7+)
243 E: alenhar2@cs.uiuc.edu
244 W: http://www.lenharth.org/~andrewl/
246 D: Sampling based profiling
250 D: PredicateSimplifier pass
252 N: Tony Linthicum, et. al.
253 E: tlinth@codeaurora.org
254 D: Backend for Qualcomm's Hexagon VLIW processor.
256 N: Bruno Cardoso Lopes
257 E: bruno.cardoso@gmail.com
258 W: http://www.brunocardoso.org
262 E: duraid@octopus.com.au
263 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
264 D: IA64 backend, BigBlock register allocator
267 E: rjmccall@apple.com
268 D: Clang semantic analysis and IR generation
271 E: michael.mccracken@gmail.com
272 D: Line number support for llvmgcc
274 N: Vladimir Merzliakov
276 D: Test suite fixes for FreeBSD
280 D: Added STI Cell SPU backend.
283 E: geek4civic@gmail.com
284 E: chapuni@hf.rim.or.jp
285 D: Cygwin and MinGW support.
289 N: Edward O'Callaghan
290 E: eocallaghan@auroraux.org
291 W: http://www.auroraux.org
292 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
293 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
294 D: and error clean ups.
298 D: Visual C++ compatibility fixes
300 N: Jakob Stoklund Olesen
302 D: Machine code verifier
304 D: Fast register allocator
305 D: Greedy register allocator
313 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
314 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
315 D: Optimizer improvements, Loop Index Split
318 E: deeppatel1987@gmail.com
319 D: ARM calling conventions rewrite, hard float support
322 E: peckw@wesleypeck.com
323 W: http://wesleypeck.com/
324 D: MicroBlaze backend
327 E: pichet2000@gmail.com
331 W: http://vladimir_prus.blogspot.com
333 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
337 D: Cmake dependency chain and various bug fixes
340 E: mcrosier@apple.com
341 D: ARM fast-isel improvements
342 D: Performance monitoring
345 E: nadav.rotem@intel.com
346 D: Vector code generation improvements.
349 E: roman@codedgers.com
354 D: Ada support in llvm-gcc
356 D: Exception handling improvements
357 D: Type legalizer rewrite
361 D: Graph coloring register allocator for the Sparc64 backend
363 N: Arnold Schwaighofer
364 E: arnold.schwaighofer@gmail.com
365 D: Tail call optimization for the x86 backend
369 D: Miscellaneous bug fixes
372 E: ashukla@cs.uiuc.edu
375 N: Michael J. Spencer
376 E: bigcheesegs@gmail.com
377 D: Shepherding Windows COFF support into MC.
378 D: Lots of Windows stuff.
381 E: rspencer@reidspencer.com
382 W: http://reidspencer.com/
383 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
386 E: edwintorok@gmail.com
387 D: Miscellaneous bug fixes
391 D: C++ bugs filed, and C++ front-end bug fixes.
393 N: Lauro Ramos Venancio
394 E: lauro.venancio@indt.org.br
395 D: ARM backend improvements
396 D: Thread Local Storage implementation
399 E: wendling@apple.com
400 D: Exception handling
404 E: bob.wilson@acm.org
405 D: Advanced SIMD (NEON) support in the ARM backend