1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/mediatek/mediatek,rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Read Direct Memory Access
10 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
11 - Philipp Zabel <p.zabel@pengutronix.de>
14 Mediatek Read Direct Memory Access(RDMA) component used to read the
15 data into DMA. It provides real time data to the back-end panel
16 driver, such as DSI, DPI and DP_INTF.
17 It contains one line buffer to store the sufficient pixel data.
18 RDMA device node must be siblings to the central MMSYS_CONFIG node.
19 For a description of the MMSYS_CONFIG binding, see
20 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
27 - const: mediatek,mt2701-disp-rdma
29 - const: mediatek,mt8173-disp-rdma
31 - const: mediatek,mt8183-disp-rdma
33 - const: mediatek,mt8195-disp-rdma
36 - mediatek,mt7623-disp-rdma
37 - mediatek,mt2712-disp-rdma
39 - mediatek,mt2701-disp-rdma
42 - mediatek,mt8192-disp-rdma
44 - mediatek,mt8183-disp-rdma
53 description: A phandle and PM domain specifier as defined by bindings of
54 the power controller specified by phandle. See
55 Documentation/devicetree/bindings/power/power-domain.yaml for details.
59 - description: RDMA Clock
63 This property should point to the respective IOMMU block with master port as argument,
64 see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
66 mediatek,rdma-fifo-size:
68 rdma fifo size may be different even in same SOC, add this property to the
70 The value below is the Max value which defined in hardware data sheet
71 mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
72 mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
73 mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
74 $ref: /schemas/types.yaml#/definitions/uint32
75 enum: [8192, 5120, 2048]
77 mediatek,gce-client-reg:
78 description: The register of client driver can be configured by gce with
79 4 arguments defined in this property, such as phandle of gce, subsys id,
80 register offset and size. Each GCE subsys id is mapping to a client
81 defined in the header include/dt-bindings/gce/<chip>-gce.h.
82 $ref: /schemas/types.yaml#/definitions/phandle-array
93 additionalProperties: false
98 rdma0: rdma@1400e000 {
99 compatible = "mediatek,mt8173-disp-rdma";
100 reg = <0 0x1400e000 0 0x1000>;
101 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
102 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
103 clocks = <&mmsys CLK_MM_DISP_RDMA0>;
104 iommus = <&iommu M4U_PORT_DISP_RDMA0>;
105 mediatek,rdma-fifosize = <8192>;
106 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;