1 \ name : msp430FR5xxx_I2C_MMultiMaster.f
3 \ Copyright (C) <2016> <J.M. THOORENS>
5 \ This program is free software: you can redistribute it and/or modify
6 \ it under the terms of the GNU General Public License as published by
7 \ the Free Software Foundation, either version 3 of the License, or
8 \ (at your option) any later version.
10 \ This program is distributed in the hope that it will be useful,
11 \ but WITHOUT ANY WARRANTY; without even the implied warranty of
12 \ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 \ GNU General Public License for more details.
15 \ You should have received a copy of the GNU General Public License
16 \ along with this program. If not, see <http://www.gnu.org/licenses/>.
19 \ I2C MASTER Standard Mode software driver without interrupt
20 \ Target: MSP-EXP430FR5969 @ 8,16MHz
21 \ version 1.1 2016-03-18
23 \ ---------------------------------------------------------------------------------------------------------------------;
24 \ SCL clock generation, timing, and test of data(s) number are made by I2C_MMaster.
25 \ slave can strech SCL low after Start Condition and after any bit.
27 \ address Ack/Nack is generated by the slave on SDA line (released by the master)
28 \ Two groups of eight addresses (000$xxy and 1111xxxy) are not allowed (reserved)
29 \ after address or data is sent, the transmitter (Master or Slave) must release SDA line to allow (N)Ack by the receiver
30 \ data Ack/Nack are generated by the receiver (master or slave) on SDA line
31 \ a master receiver must signal the end of data to the slave transmitter by sending a Nack bit
32 \ Stop or restart conditions must be generated by master after a Nack bit.
33 \ after Ack bit is sent, Slave must release SDA line to allow master to do stop or restart conditions
35 \ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK _
36 \ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X___/
37 \ _____ _ _ _ _ _ _ _ _ _ _ ___
38 \ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/
40 \ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
42 \ |Start Condition |stoP Condition
44 \ __ _____ _____ _..._ _____ _____ _NACK _____ _____ _..._ _____ _____ _NACK ___
45 \ SDA \____/_MSB_X_____X_..._X_LSB_X_R/W_x_ACK_x_MSB_X_____X_..._X_____X_LSB_X_ACK_X \____...
46 \ _____ _ _ _ _ _ _ _ _ _ _ ____
47 \ SCL \___/1\___/2\___...___/7\___/8\___/9\___/1\___/2\___...___/7\___/8\___/9\___/ \_...
49 \ | |Slave Stretch Low |SSL |SSL |SSL |SSL |
51 \ |Start Condition |reStart Condition
53 \ tHIGH : SCL high time
55 \ tBUF : SDA high time between Stop and Start conditions
56 \ tHD:STA : Start_Condition SCL high time after SDA is low
57 \ tSU:STO : Stop_Condition SCL high time before SDA rise
58 \ tSU:STA : Start_Condition SCL high time before SDA fall
59 \ tHD:DAT : SDA data change time after SCL is low
60 \ the SDA line must be strobe just after SCL is high
61 \ the SDA data must be change just after SCL is low
62 \ standard mode (up to 100 kHz) : tHIGH = tHD:STA = tSU:STO = 4µs
63 \ tLOW = tSU:STA = tBUF = 4,7µs
66 \ fast mode (up to 400 kHz) : tHIGH = tHD:STA = tSU:STO = 0,6µs
67 \ tLOW = tSU:STA = tBUF = 1,3µs
69 \ -------------------------------------------------------------------------------------------------------------------;
71 \ =========================================================================
72 \ =========================================================================
74 \ ### ##### ##### # ## #
75 \ # # # # # ## ## ## ## ## #### ##### ###### #####
76 \ # # # # # # # # # # # # # # # # # #
77 \ # ##### # # # # # # # # # #### # ##### # #
78 \ # # # # # # # ###### # # # #####
79 \ # # # # # # # # # # # # # # # #
80 \ ### ####### ##### # # # # # # #### # ###### # #
82 \ =========================================================================
83 \ =========================================================================
85 \ tested with P1.6 SDA, P1.7 SCL :
86 \ Start + Adr + Write 3 bytes + Stop + Start + adr + read 2 bytes + stop = 206us ==> 305 kHz (STOP=14us)
87 \ See MSP430FR5xxx_I2C_MultiMaster.png
90 CREATE I2CMS_ADR \ low(I2CMS_ADR) = slave I2C address with RW flag, high(I2CMS_ADR) = RX buffer,data0
92 CREATE I2CMM_BUF \ low(I2CMM_BUF) = RX or TX lentgh, high(I2CMM_BUF) = TX buffer,data0
98 \ ----------------------------------\
100 \ ----------------------------------\
101 \ \ in I2CMS_ADR/I2CMM_BUF as RX/TX buffer requested by I2CMS_ADR(0(0))
102 \ \ I2CMS_ADR(0) = I2C_Slave_addr&R/w
103 \ \ I2CMM_BUF(0) = TX/RX count of datas
104 \ \ I2CMM_BUF(0) = 0 ==> send only I2C address
107 \ \ out S = BUF PTR pointing on first data not exCHNGd
108 \ \ T = count of TX/RX datas exCHNGd
109 \ \ T = -1 ==> NACK on address
110 \ \ I2CMS_ADR(0) = -1 ==> arbitration lost, else unchanged
111 \ \ I2CMM_BUF(0) = unchanged
112 \ ------------------------------ \
113 \ Swap Slave to Master mode \
114 \ ------------------------------ \
115 BIS #1,&UCB0CTLW0 \ SWRST
116 MOV #$2FD3,&UCB0CTLW0 \ master mode + UCMM + UCTR + START + SWRST, IFG=IE=0
117 MOV #$00C8,&UCB0CTLW1 \ set automatic stop (count byte reached)
118 MOV #$14,&UCB0BRW \ baudrate = SMCLK/20 = 400 kHz @8MHz ; 340 kHz measured
119 MOV &MY_OWN_ADR,&UCB0I2COA0 \ (required by multimaster mode)
120 BIS #$0400,&UCB0I2COA0 \ UCOAEN=1 enable UCB0I2COA0 with address slave
121 \ ------------------------------ \
122 MOV #I2CMM_BUF,S \ count & TX buf
123 MOV.B @S+,&UCB0TBCNT \
124 CMP.B #0,&UCB0TBCNT \
126 BIS #4,&UCB0CTLW0 \ add Stop to Start cmd ==> Master send only I2C address
128 MOV #I2CMS_ADR,T \ I2Cadr & RX buf
129 MOV.B @T+,&UCB0I2CSA \ UCB0I2CSA = slave_address & R/w bit
130 RRA &UCB0I2CSA \ UCB0I2CSA = slave_address, C flag = R/w flag
132 MOV T,S \ Master read : S = RX buffer
133 BIC #$10,&UCB0CTLW0 \ UCB0CTLW0 <-- UCTR=0
135 \ ------------------------------ \
137 \ ------------------------------ \
139 BIC #1,&UCB0CTLW0 \ UCB0CTLW0 : clear SWRST, start I2C MASTER
140 BIT.B #1,&I2CMS_ADR \ R/W test
142 \ ---------------------------- \
144 \ ---------------------------- \
146 MOV.B &UCBCNT0,T \ store count of byte
147 BIT #$10,&UCB0IFG \ test UCALIFG : arbitration lost interrupt
148 0<> ?GOTO FW1 \ eUSCI is already in Slave mode
149 BIT #8,&UCB0IFG \ test UCSTPIFG
151 BIT #$20,&UCB0IFG \ test UCNACKIFG
153 BIS #4,&UCB0CTLW0 \ generate stop bit
155 BIT #2,&UCB0IFG \ test UCTXIFG0
157 MOV.B @S+,&UCB0TXBUF \ load data into UCB0TXBUF
161 \ ------------------------------ \
163 \ ------------------------------ \
165 MOV.B &UCBCNT0,T \ store count of byte
166 BIT #8,&UCB0IFG \ test UCSTPIFG
168 MOV @RSP+,PC \ end of I2C_MM RX driver
170 BIT #1,&UCB0IFG \ test UCRXIFG0
172 MOV.B &UCB0RXBUF,0(S) \ load data from UCB0RXBUF
176 \ ------------------------------ \
177 \ Swap Master to Slave mode \
178 \ ------------------------------ \
179 FW2 MOV #1,&UCB0CTLW0 \ set eUSCI_B in reset state, clear UCB0IE & UCB0IFG all flags
180 BIS #$07A0,&UCB0CTLW0 \
181 \ BIS #$10,&UCB0CTLW1 \ set software ack address (UCSWACK=1)
182 \ MOV #0,&UCB0ADDMSK \ enable address mask for all addresses i.e. software address
183 BIC #1,&UCB0CTLW0 \ activate eUSCI_B
184 MOV #4,&UCB0IE \ enable StartCond interrupt
186 \ ------------------------------ \
187 ENDASM \ 62 words + 9 init words
190 \ ------------------------------\
192 \ ------------------------------\
194 \ ------------------------------\
195 \ %0000 1111 1101 0011 $640 = $0FD3
196 \ - UCMM = 1 : multi master mode
197 \ - UCMST = 1 : I2C_MMaster
198 \ -- UCMODE = %11 = I2C
199 \ _ USYNC=1 (always 1)
200 \ -- UCSSEL=SMCLK=8MHz
201 \ - UCTXACK=0 not auto ACK slave address
202 \ - UCTR=1/0 : TX/RX modes
204 \ - UCTXSTT send start
206 \ ------------------------------\
207 \ %0000 0000 1100 1000 $642 = $00C8
208 \ - UCETXINT=0 : UCTXIFG0 set address match UCxI2COAx and TX mode
209 \ -- UCCLTO=%11 : SCL low time out = 34 ms
210 \ - UCSWACK=1 : UCTXACK must be written to continue
211 \ -- UCASTP0=%10 : automatic Stop when UCBxTBCNT is reached
212 \ ------------------------------\
213 \ PORTX (PORTx:y) default values\ DIR0,REN1,OUT1 (input with pullup resistors)
214 \ ------------------------------\
215 \ notice : UCB0 I2C driver seems to control only DIR register !!!
216 BIC.B #MM_BUS,&I2CMM_REN \ REN0 : no_resistor
217 BIC.B #MM_BUS,&I2CMM_OUT \ OUT0 : preset output low
218 BIS.B #MM_BUS,&I2CMM_SEL1 \ SEL11 : enable I2C I/O
220 ." ; type stop to stop :-)"
221 LIT recurse is WARM \ insert this starting routine between COLD and WARM...
222 (WARM) \ ...and continue with (WARM)
226 : STOP \ stops multitasking, must to be used before downloading app
227 ['] (WARM) IS WARM \ remove START app from FORTH init process
228 ECHO COLD \ reset CPU, interrupt vectors, and start FORTH