1 ; MSP430fr57xx.inc : MSP430FR57xx declarations
4 .IF DEVICE = "MSP430FR5734"
6 ; ----------------------------------------------------------------------
7 ; MSP430FR5734 Peripheral File Map
8 ; ----------------------------------------------------------------------
9 SFR_SFR .equ 0100h ; Special function
10 PMM_SFR .equ 0120h ; PMM
11 FRAM_SFR .equ 0140h ; FRAM control
13 WDT_A_SFR .equ 015Ch ; Watchdog
15 SYS_SFR .equ 0180h ; SYS
16 REF_SFR .equ 01B0h ; REF
17 PA_SFR .equ 0200h ; PORT1/2
18 PJ_SFR .equ 0320h ; PORTJ
26 DMA_CTRL_SFR .equ 0500h
27 DMA_CHN0_SFR .equ 0510h
28 DMA_CHN1_SFR .equ 0520h
29 DMA_CHN2_SFR .equ 0530h
30 MPU_SFR .equ 05A0h ; memory protect unit
31 eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
32 eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
33 ADC10_B_SFR .equ 0700h
37 ; ----------------------------------------------
38 ; MSP430FR5734 MEMORY MAP
39 ; ----------------------------------------------
40 ; 0000-0FFF = peripherals (4 KB)
41 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
42 ; 1800-187F = info B (FRAM 128 B)
43 ; 1880-18FF = info A (FRAM 128 B)
44 ; 1900-19FF = N/A (mirrored into info A/B)
45 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
46 ; 1A80-1BFF = unused (385 B)
47 ; 1C00-1FFF = RAM (1 KB)
48 ; 2000-C1FF = unused (41472 B)
49 ; E000-FF7F = code memory (FRAM 15743 B)
50 ; FF80-FFFF = interrupt vectors (FRAM 127 B)
51 ; ----------------------------------------------
52 PAGESIZE .equ 512 ; MPU unit
53 ; ----------------------------------------------
54 ; FRAM ; INFO B, A, TLV
55 ; ----------------------------------------------
57 INFOBSTART .equ 01800h
59 INFOASTART .equ 01880h
61 TLVSTAT .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
63 ; ----------------------------------------------
65 ; ----------------------------------------------
68 ; ----------------------------------------------
70 ; ----------------------------------------------
71 PROGRAMSTART .equ 0E000h ; Code space start
72 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
73 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
74 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
75 BSL_SIG1 .equ 0FF84h ;
76 BSL_SIG2 .equ 0FF86h ;
77 JTAG_PASSWORD .equ 0FF88h ; 256 bits
78 INTVECT .equ 0FFCEh ; FFCE-FFFF
79 BSL_PASSWORD .equ 0FFE0h ; 256 bits
80 ; ----------------------------------------------
83 ; ----------------------------------------------
84 ; Interrupt Vectors and signatures - MSP430FR57xx
85 ; ----------------------------------------------
88 ;;Start of JTAG and BSL signatures
89 ; .word 0 ; JTAG signature 1
90 ; .word 0 ; JTAG signature 2
91 ; .word 0 ; 5555h ; BSL signature 1 ; disable BSL
92 ; .word 0 ; BSL signature 2
94 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
96 .org INTVECT ; FFCE-FFFF 24 vectors + reset
97 .word reset ; $FFCE - RTC_B
98 .word reset ; $FFD0 - I/O Port 4
99 .word reset ; $FFD2 - I/O Port 3
100 .word reset ; $FFD4 - TB2_1
101 .word reset ; $FFD6 - TB2_0
102 .word reset ; $FFD8 - I/O Port P2
103 .word reset ; $FFDA - TB1_1
104 .word reset ; $FFDC - TB1_0
105 .word reset ; $FFDE - I/O Port P1
106 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
107 .word reset ; $FFE0 - TA1_1
108 .word reset ; $FFE2 - TA1_0
109 .word reset ; $FFE4 - DMA
110 .word reset ; $FFE6 - eUSCI_A1
111 .word reset ; $FFE8 - TA0_1
112 .word reset ; $FFEA - TA0_0
113 .word reset ; $FFEC - ADC10_B
114 .word reset ; $FFEE - eUSCI_B0
115 TERMVEC .word TERMINAL_INT ; $FFF0 - eUSCI_A0
116 .word reset ; $FFF2 - Watchdog
117 .word reset ; $FFF4 - TB0_1
118 .word reset ; $FFF6 - TB0_0
119 .word reset ; $FFF8 - COMP_D
120 .word reset ; $FFFA - userNMI
121 .word reset ; $FFFC - sysNMI
122 RST_ADR .word reset ; $FFFE - reset
125 .ENDIF ; DEVICE="MSP430fr5734
128 .IF DEVICE = "MSP430FR5738"
130 ; ----------------------------------------------------------------------
131 ; MSP430FR5738 Peripheral File Map
132 ; ----------------------------------------------------------------------
133 SFR_SFR .equ 0100h ; Special function
134 PMM_SFR .equ 0120h ; PMM
135 FRAM_SFR .equ 0140h ; FRAM control
137 WDT_A_SFR .equ 015Ch ; Watchdog
139 SYS_SFR .equ 0180h ; SYS
140 REF_SFR .equ 01B0h ; REF
141 PA_SFR .equ 0200h ; PORT1/2
142 PJ_SFR .equ 0320h ; PORTJ
150 DMA_CTRL_SFR .equ 0500h
151 DMA_CHN0_SFR .equ 0510h
152 DMA_CHN1_SFR .equ 0520h
153 DMA_CHN2_SFR .equ 0530h
154 MPU_SFR .equ 05A0h ; memory protect unit
155 eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
156 eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
157 ADC10_B_SFR .equ 0700h
158 COMP_D_SFR .equ 08C0h
161 ; ----------------------------------------------
162 ; MSP430FR5738 MEMORY MAP
163 ; ----------------------------------------------
164 ; 0000-0FFF = peripherals (4 KB)
165 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
166 ; 1800-187F = info B (FRAM 128 B)
167 ; 1880-18FF = info A (FRAM 128 B)
168 ; 1900-19FF = N/A (mirrored into info A/B)
169 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
170 ; 1A80-1BFF = unused (385 B)
171 ; 1C00-1FFF = RAM (1 KB)
172 ; 2000-C1FF = unused (41472 B)
173 ; C200-FF7F = code memory (FRAM 15743 B)
174 ; FF80-FFFF = interrupt vectors (FRAM 127 B)
175 ; ----------------------------------------------
176 PAGESIZE .equ 512 ; MPU unit
177 ; ----------------------------------------------
178 ; FRAM ; INFO B, A, TLV
179 ; ----------------------------------------------
180 INFOSTART .equ 01800h
181 INFOBSTART .equ 01800h
183 INFOASTART .equ 01880h
185 TLVSTAT .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
187 ; ----------------------------------------------
189 ; ----------------------------------------------
192 ; ----------------------------------------------
194 ; ----------------------------------------------
195 PROGRAMSTART .equ 0C200h ; Code space start
196 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
197 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
198 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
199 BSL_SIG1 .equ 0FF84h ;
200 BSL_SIG2 .equ 0FF86h ;
201 JTAG_PASSWORD .equ 0FF88h ; 256 bits
202 INTVECT .equ 0FFCEh ; FFCE-FFFF
203 BSL_PASSWORD .equ 0FFE0h ; 256 bits
204 ; ----------------------------------------------
207 ; ----------------------------------------------
208 ; Interrupt Vectors and signatures - MSP430FR57xx
209 ; ----------------------------------------------
212 ;;Start of JTAG and BSL signatures
213 ; .word 0 ; JTAG signature 1
214 ; .word 0 ; JTAG signature 2
215 ; .word 0 ; 5555h ; BSL signature 1 ; disable BSL
216 ; .word 0 ; BSL signature 2
218 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
220 .org INTVECT ; FFCE-FFFF 24 vectors + reset
221 .word reset ; $FFCE - RTC_B
222 .word reset ; $FFD0 - I/O Port 4
223 .word reset ; $FFD2 - I/O Port 3
224 .word reset ; $FFD4 - TB2_1
225 .word reset ; $FFD6 - TB2_0
226 .word reset ; $FFD8 - I/O Port P2
227 .word reset ; $FFDA - TB1_1
228 .word reset ; $FFDC - TB1_0
229 .word reset ; $FFDE - I/O Port P1
230 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
231 .word reset ; $FFE0 - TA1_1
232 .word reset ; $FFE2 - TA1_0
233 .word reset ; $FFE4 - DMA
234 .word reset ; $FFE6 - eUSCI_A1
235 .word reset ; $FFE8 - TA0_1
236 .word reset ; $FFEA - TA0_0
237 .word reset ; $FFEC - ADC10_B
238 .word reset ; $FFEE - eUSCI_B0
239 TERMVEC .word TERMINAL_INT ; $FFF0 - eUSCI_A0
240 .word reset ; $FFF2 - Watchdog
241 .word reset ; $FFF4 - TB0_1
242 .word reset ; $FFF6 - TB0_0
243 .word reset ; $FFF8 - COMP_D
244 .word reset ; $FFFA - userNMI
245 .word reset ; $FFFC - sysNMI
246 RST_ADR .word reset ; $FFFE - reset
249 .ENDIF ; DEVICE="MSP430fr5738
253 .IF DEVICE = "MSP430FR5739"
255 ; ----------------------------------------------------------------------
256 ; MSP430FR5739 Peripheral File Map
257 ; ----------------------------------------------------------------------
258 SFR_SFR .equ 0100h ; Special function
259 PMM_SFR .equ 0120h ; PMM
260 FRAM_SFR .equ 0140h ; FRAM control
262 WDT_A_SFR .equ 015Ch ; Watchdog
264 SYS_SFR .equ 0180h ; SYS
265 REF_SFR .equ 01B0h ; REF
266 PA_SFR .equ 0200h ; PORT1/2
267 PB_SFR .equ 0220h ; PORT3/4
268 PJ_SFR .equ 0320h ; PORTJ
276 DMA_CTRL_SFR .equ 0500h
277 DMA_CHN0_SFR .equ 0510h
278 DMA_CHN1_SFR .equ 0520h
279 DMA_CHN2_SFR .equ 0530h
280 MPU_SFR .equ 05A0h ; memory protect unit
281 eUSCI_A0_SFR .equ 05C0h ; eUSCI_A0
282 eUSCI_A1_SFR .equ 05E0h ; eUSCI_A1
283 eUSCI_B0_SFR .equ 0640h ; eUSCI_B0
284 ADC10_B_SFR .equ 0700h
285 COMP_D_SFR .equ 08C0h
287 ; ----------------------------------------------
288 ; MSP430FR5739 MEMORY MAP
289 ; ----------------------------------------------
290 ; 0000-0FFF = peripherals (4 KB)
291 ; 1000-17FF = ROM bootstrap loader BSL0..3 (4x512 B)
292 ; 1800-187F = info B (FRAM 128 B)
293 ; 1880-18FF = info A (FRAM 128 B)
294 ; 1900-19FF = N/A (mirrored into info A/B)
295 ; 1A00-1A7F = TLV device descriptor info (FRAM 128 B)
296 ; 1A80-1BFF = unused (385 B)
297 ; 1C00-1FFF = RAM (1 KB)
298 ; 2000-C1FF = unused (41472 B)
299 ; C200-FF7F = code memory (FRAM 15743 B)
300 ; FF80-FFFF = interrupt vectors (FRAM 127 B)
301 ; ----------------------------------------------
302 PAGESIZE .equ 512 ; MPU unit
303 ; ----------------------------------------------
304 ; FRAM ; INFO B, A, TLV
305 ; ----------------------------------------------
306 INFOSTART .equ 01800h
307 INFOBSTART .equ 01800h
309 INFOASTART .equ 01880h
311 TLVSTAT .equ 01A00h ; Device Descriptor Info (Tag-Lenght-Value)
313 ; ----------------------------------------------
315 ; ----------------------------------------------
318 ; ----------------------------------------------
320 ; ----------------------------------------------
321 PROGRAMSTART .equ 0C200h ; Code space start
322 SIGNATURES .equ 0FF80h ; JTAG/BSL signatures
323 JTAG_SIG1 .equ 0FF80h ; if 0 (electronic fuse=0) enable JTAG/SBW; must be reset by wipe.
324 JTAG_SIG2 .equ 0FF82h ; if JTAG_SIG1=0xAAAA, length of password string @ JTAG_PASSWORD
325 BSL_SIG1 .equ 0FF84h ;
326 BSL_SIG2 .equ 0FF86h ;
327 JTAG_PASSWORD .equ 0FF88h ; 256 bits
328 INTVECT .equ 0FFCEh ; FFCE-FFFF
329 BSL_PASSWORD .equ 0FFE0h ; 256 bits
330 ; ----------------------------------------------
332 ; ----------------------------------------------
333 ; Interrupt Vectors and signatures - MSP430FR57xx
334 ; ----------------------------------------------
337 ;;Start of JTAG and BSL signatures
338 ; .word 0 ; JTAG signature 1
339 ; .word 0 ; JTAG signature 2
340 ; .word 0 ; 5555h ; BSL signature 1; disable BSL
341 ; .word 0 ; BSL signature 2
343 ; .org JTAG_PASSWORD ;Start of JTAG PASSWORD
345 .org INTVECT ; FFCE-FFFF 24 vectors + reset
346 .word reset ; $FFCE - RTC_B
347 .word reset ; $FFD0 - I/O Port 4
348 .word reset ; $FFD2 - I/O Port 3
349 .word reset ; $FFD4 - TB2_1
350 .word reset ; $FFD6 - TB2_0
351 .word reset ; $FFD8 - I/O Port P2
352 .word reset ; $FFDA - TB1_1
353 .word reset ; $FFDC - TB1_0
354 .word reset ; $FFDE - I/O Port P1
355 ; .org BSL_PASSWORD ;Start of BSL PASSWORD
356 .word reset ; $FFE0 - TA1_1
357 .word reset ; $FFE2 - TA1_0
358 .word reset ; $FFE4 - DMA
360 TERMVEC .word TERMINAL_INT ; $FFE6 - eUSCI_A1
362 .word reset ; $FFE6 - eUSCI_A1
364 .word reset ; $FFE8 - TA0_1
365 .word reset ; $FFEA - TA0_0
366 .word reset ; $FFEC - ADC10_B
367 .word reset ; $FFEE - eUSCI_B0
369 TERMVEC .word TERMINAL_INT ; $FFF0 - eUSCI_A0
371 .word reset ; $FFF0 - eUSCI_A0
373 .word reset ; $FFF2 - Watchdog
374 .word reset ; $FFF4 - TB0_1
375 .word reset ; $FFF6 - TB0_0
376 .word reset ; $FFF8 - COMP_D
377 .word reset ; $FFFA - userNMI
378 .word reset ; $FFFC - sysNMI
379 RST_ADR .word reset ; $FFFE - reset
382 ; ----------------------------------------------------------------------
383 ; POWER ON RESET AND INITIALIZATION : PORT3/4
384 ; ----------------------------------------------------------------------
387 PBIN .set PB_SFR + 00h ; Port B Input
388 PBOUT .set PB_SFR + 02h ; Port B Output 1/0 or pullup/pulldown resistor
389 PBDIR .set PB_SFR + 04h ; Port B Direction
390 PBREN .set PB_SFR + 06h ; Port B Resistor Enable
391 PBSEL0 .set PB_SFR + 0Ah ; Port B Selection 0
392 PBSEL1 .set PB_SFR + 0Ch ; Port B Selection 1
393 PBSELC .set PB_SFR + 16h ; Port B Complement Selection
394 PBIES .set PB_SFR + 18h ; Port B Interrupt Edge Select
395 PBIE .set PB_SFR + 1Ah ; Port B Interrupt Enable
396 PBIFG .set PB_SFR + 1Ch ; Port B Interrupt Flag
398 P3IN .set PB_SFR + 00h ; Port 3 Input */
399 P3OUT .set PB_SFR + 02h ; Port 3 Output
400 P3DIR .set PB_SFR + 04h ; Port 3 Direction
401 P3REN .set PB_SFR + 06h ; Port 3 Resistor Enable
402 P3SEL0 .set PB_SFR + 0Ah ; Port 3 Selection 0
403 P3SEL1 .set PB_SFR + 0Ch ; Port 3 Selection 1
404 P3SELC .set PB_SFR + 16h ; Port 3 Complement Selection
405 P3IES .set PB_SFR + 18h ; Port 3 Interrupt Edge Select
406 P3IE .set PB_SFR + 1Ah ; Port 3 Interrupt Enable
407 P3IFG .set PB_SFR + 1Ch ; Port 3 Interrupt Flag
409 P4IN .set PB_SFR + 01h ; Port 4 Input */
410 P4OUT .set PB_SFR + 03h ; Port 4 Output
411 P4DIR .set PB_SFR + 05h ; Port 4 Direction
412 P4REN .set PB_SFR + 07h ; Port 4 Resistor Enable
413 P4SEL0 .set PB_SFR + 0Bh ; Port 4 Selection 0
414 P4SEL1 .set PB_SFR + 0Dh ; Port 4 Selection 1
415 P4SELC .set PB_SFR + 17h ; Port 4 Complement Selection
416 P4IES .set PB_SFR + 19h ; Port 4 Interrupt Edge Select
417 P4IE .set PB_SFR + 1Bh ; Port 4 Interrupt Enable
418 P4IFG .set PB_SFR + 1Dh ; Port 4 Interrupt Flag
420 ; ----------------------------------------------------------------------
422 ; ----------------------------------------------------------------------
425 TERMCTLW0 .equ eUSCI_A1_SFR + 00h ; eUSCI_A1 Control Word Register 0
426 TERMBRW .equ eUSCI_A1_SFR + 06h ; eUSCI_A1 Baud Word Rate 0
427 TERMMCTLW .equ eUSCI_A1_SFR + 08h ; eUSCI_A1 Modulation Control
428 TERMRXBUF .equ eUSCI_A1_SFR + 0Ch ; eUSCI_A1 Receive Buffer
429 TERMTXBUF .equ eUSCI_A1_SFR + 0Eh ; eUSCI_A1 Transmit Buffer
430 TERMIE .equ eUSCI_A1_SFR + 1Ah ; eUSCI_A1 Interrupt Enable Register
431 TERMIFG .equ eUSCI_A1_SFR + 1Ch ; eUSCI_A1 Interrupt Flags Register
434 .ENDIF ;DEVICE="MSP430FR5739"
439 ;=======================================================================
441 ;=======================================================================
443 UCSWRST .equ 1 ; eUSCI Software Reset
444 UCTXIE .equ 2 ; eUSCI Transmit Interrupt Enable
445 UCRXIE .equ 1 ; eUSCI Receive Interrupt Enable
446 UCTXIFG .equ 2 ; eUSCI Transmit Interrupt Flag
447 UCRXIFG .equ 1 ; eUSCI Receive Interrupt Flag
451 ; ----------------------------------------------------------------------
452 ; POWER ON RESET AND INITIALIZATION : LOCK I/O as high impedance state
453 ; ----------------------------------------------------------------------
457 PM5CTL0 .equ PMM_SFR + 10h ; Power mode 5 control register 0
460 ; ----------------------------------------------------------------------
461 ; POWER ON RESET AND INITIALIZATION : WATCHDOG TIMER A
462 ; ----------------------------------------------------------------------
464 WDTCTL .equ WDT_A_SFR + 00h ; Watchdog Timer Control */
466 ; WDTCTL Control Bits
468 WDTHOLD .equ 0080h ; WDT - Timer hold
469 WDTCNTCL .equ 0008h ; WDT timer counter clear
471 ; ----------------------------------------------------------------------
472 ; POWER ON RESET AND INITIALIZATION PAIN=PORT2:PORT1
473 ; ----------------------------------------------------------------------
475 PAIN .equ PA_SFR + 00h ; Port A INput
476 PAOUT .equ PA_SFR + 02h ; Port A OUTput
477 PADIR .equ PA_SFR + 04h ; Port A DIRection
478 PAREN .equ PA_SFR + 06h ; Port A Resistor ENable
479 PASEL0 .equ PA_SFR + 0Ah ; Port A SELection 0
480 PASEL1 .equ PA_SFR + 0Ch ; Port A SELection 1
481 PASELC .equ PA_SFR + 16h ; Port A SELection Complement
482 PAIES .equ PA_SFR + 18h ; Port A Interrupt Edge Select
483 PAIE .equ PA_SFR + 1Ah ; Port A Interrupt Enable
484 PAIFG .equ PA_SFR + 1Ch ; Port A Interrupt FlaG
486 P1IN .equ PA_SFR + 00h ; Port 1 INput
487 P1OUT .equ PA_SFR + 02h ; Port 1 OUTput
488 P1DIR .equ PA_SFR + 04h ; Port 1 DIRection
489 P1REN .equ PA_SFR + 06h ; Port 1 Resistor ENable
490 P1SEL0 .equ PA_SFR + 0Ah ; Port 1 SELection 0
491 P1SEL1 .equ PA_SFR + 0Ch ; Port 1 SELection 1
492 P1IV .equ PA_SFR + 0Eh ; Port 1 Interrupt Vector word
493 P1SELC .equ PA_SFR + 16h ; Port 1 SELection Complement
494 P1IES .equ PA_SFR + 18h ; Port 1 Interrupt Edge Select
495 P1IE .equ PA_SFR + 1Ah ; Port 1 Interrupt Enable
496 P1IFG .equ PA_SFR + 1Ch ; Port 1 Interrupt FlaG
498 P2IN .equ PA_SFR + 01h ; Port 2 INput
499 P2OUT .equ PA_SFR + 03h ; Port 2 OUTput
500 P2DIR .equ PA_SFR + 05h ; Port 2 DIRection
501 P2REN .equ PA_SFR + 07h ; Port 2 Resistor ENable
502 P2SEL0 .equ PA_SFR + 0Bh ; Port 2 SELection 0
503 P2SEL1 .equ PA_SFR + 0Dh ; Port 2 SELection 1
504 P2SELC .equ PA_SFR + 17h ; Port 2 SELection Complement
505 P2IES .equ PA_SFR + 19h ; Port 2 Interrupt Edge Select
506 P2IE .equ PA_SFR + 1Bh ; Port 2 Interrupt Enable
507 P2IFG .equ PA_SFR + 1Dh ; Port 2 Interrupt Flag
508 P2IV .equ PA_SFR + 1Eh ; Port 2 Interrupt Vector word
510 ; ----------------------------------------------------------------------
511 ; POWER ON RESET AND INITIALIZATION : PORTJ
512 ; ----------------------------------------------------------------------
514 PJIN .set PJ_SFR + 00h ; Port B Input
515 PJOUT .set PJ_SFR + 02h ; Port B Output
516 PJDIR .set PJ_SFR + 04h ; Port B Direction
517 PJREN .set PJ_SFR + 06h ; Port B Resistor Enable
518 PJSEL0 .set PJ_SFR + 0Ah ; Port B Selection 0
519 PJSEL1 .set PJ_SFR + 0Ch ; Port B Selection 1
520 PJSELC .set PJ_SFR + 16h ; Port B Complement Selection
522 ; ----------------------------------------------------------------------
523 ; POWER ON RESET AND INITIALIZATION : CLOCK SYSTEM
524 ; ----------------------------------------------------------------------
526 CSCTL0 .equ CS_SFR + 00h ; CS Control Register 0
527 CSCTL0_H .equ CS_SFR + 01h ; CS Control Register 0 high byte
528 CSCTL1 .equ CS_SFR + 02h ; CS Control Register 1
529 CSCTL2 .equ CS_SFR + 04h ; CS Control Register 2
530 CSCTL3 .equ CS_SFR + 06h ; CS Control Register 3
532 ; CSCTL0 Control Bits
533 CSKEY .equ 0A5h ; CS Password
534 ; CSCTL1 Control Bits
536 DCOFSEL0 .equ 0002h ; DCO frequency select Bit: 0
537 DCOFSEL1 .equ 0004h ; DCO frequency select Bit: 1
538 ; CSCTL2 Control Bits
539 ; SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
540 SELA_LFXCLK .equ 0000h ; 0 : ACLK Source Select LFXCLK
541 SELA_VLOCLK .equ 0100h ; 1 ACLK Source Select VLOCLK 10kHz
542 SELS_DCOCLK .equ 0030h ; 3 SMCLK Source Select DCOCLK
543 SELM_DCOCLK .equ 0003h ; 3 MCLK Source Select DCOCLK
544 ; CSCTL3 Control Bits
545 DIVA_0 .equ 0000h ; ACLK Source Divider 0
546 DIVS_0 .equ 0000h ; SMCLK Source Divider 0
547 DIVM_0 .equ 0000h ; MCLK Source Divider 0
548 DIVA_2 .equ 0100h ; ACLK Source Divider 0
549 DIVS_2 .equ 0010h ; SMCLK Source Divider 0
550 DIVM_2 .equ 0001h ; MCLK Source Divider 0
551 DIVA_4 .equ 0200h ; ACLK Source Divider 0
552 DIVS_4 .equ 0020h ; SMCLK Source Divider 0
553 DIVM_4 .equ 0002h ; MCLK Source Divider 0
554 DIVA_8 .equ 0300h ; ACLK Source Divider 0
555 DIVS_8 .equ 0030h ; SMCLK Source Divider 0
556 DIVM_8 .equ 0003h ; MCLK Source Divider 0
557 DIVA_16 .equ 0400h ; ACLK Source Divider 0
558 DIVS_16 .equ 0040h ; SMCLK Source Divider 0
559 DIVM_16 .equ 0004h ; MCLK Source Divider 0
560 DIVA_32 .equ 0500h ; ACLK Source Divider 0
561 DIVS_32 .equ 0050h ; SMCLK Source Divider 0
562 DIVM_32 .equ 0005h ; MCLK Source Divider 0
564 ; ----------------------------------------------------------------------
565 ; POWER ON RESET AND INITIALIZATION : REF
566 ; ----------------------------------------------------------------------
568 REFCTL .equ REF_SFR + 00h ; REF Shared Reference control register 0
570 ; REFCTL0 Control Bits
571 REFON .equ 0001h ; REF Reference On
572 REFTCOFF .equ 0008h ; REF Temp.Sensor off
575 ; ----------------------------------------------------------------------
577 ; ----------------------------------------------------------------------
579 MPY .equ MPY_SFR + 00h ; Multiply16 Unsigned/Operand 1 */
580 MPYS .equ MPY_SFR + 02h ; Multiply16 signed/Operand 1
581 MAC .equ MPY_SFR + 04h ; MultiplyAccumulate16 Unsigned/Operand 1 */
582 MACS .equ MPY_SFR + 06h ; MultiplyAccumulate16 signed/Operand 1
583 OP2 .equ MPY_SFR + 08h ; Operand2_16 */
584 RESLO .equ MPY_SFR + 0Ah ; 16x16-bit result low - least significant word */
585 RESHI .equ MPY_SFR + 0Ch ; 16x16-bit result high */
586 SUMEXT .equ MPY_SFR + 0Eh ; 16x16-bit sum extension register
587 MPY32L .equ MPY_SFR + 10h ; Multiply32 Unsigned/Operand 1
588 MPY32H .equ MPY_SFR + 12h ; Multiply32 Unsigned/Operand 1
589 MPYS32L .equ MPY_SFR + 14h ; Multiply32 signed/Operand 1
590 MPYS32H .equ MPY_SFR + 16h ; Multiply32 signed/Operand 1
591 MAC32L .equ MPY_SFR + 18h ; MultiplyAccumulate32 Unsigned/Operand 1
592 MAC32H .equ MPY_SFR + 1Ah ; MultiplyAccumulate32 Unsigned/Operand 1
593 MACS32L .equ MPY_SFR + 1Ch ; MultiplyAccumulate32 signed/Operand 1
594 MACS32H .equ MPY_SFR + 1Eh ; MultiplyAccumulate32 signed/Operand 1
595 OP2L .equ MPY_SFR + 20h ; Multiply32 Operand 2
596 OP2H .equ MPY_SFR + 22h ; Multiply32 Operand 2
597 RES0 .equ MPY_SFR + 24h ; 32x32-bit result 0 - least significant word */
598 RES1 .equ MPY_SFR + 26h ; 32x32-bit result 1 */
599 RES2 .equ MPY_SFR + 28h ; 32x32-bit result 2 */
600 RES3 .equ MPY_SFR + 2Ah ; 32x32-bit result 3 */
601 MPY32CTL0 .equ MPY_SFR + 2Ch ; MPY32 control register 0
604 ; ----------------------------------------------------------------------
606 ; ----------------------------------------------------------------------
609 TERMCTLW0 .equ eUSCI_A0_SFR + 00h ; eUSCI_A0 Control Word Register 0
610 TERMBRW .equ eUSCI_A0_SFR + 06h ; eUSCI_A0 Baud Word Rate 0
611 TERMMCTLW .equ eUSCI_A0_SFR + 08h ; eUSCI_A0 Modulation Control
612 TERMRXBUF .equ eUSCI_A0_SFR + 0Ch ; eUSCI_A0 Receive Buffer
613 TERMTXBUF .equ eUSCI_A0_SFR + 0Eh ; eUSCI_A0 Transmit Buffer
614 TERMIE .equ eUSCI_A0_SFR + 1Ah ; eUSCI_A0 Interrupt Enable Register
615 TERMIFG .equ eUSCI_A0_SFR + 1Ch ; eUSCI_A0 Interrupt Flags Register
618 ; ----------------------------------------------------------------------
620 ; ----------------------------------------------------------------------
622 SD_CTLW0 .equ eUSCI_B0_SFR + 00h ; USCI_B0 Control Word Register 0
623 SD_BRW .equ eUSCI_B0_SFR + 06h ; USCI_B0 Baud Word Rate 0
624 SD_RXBUF .equ eUSCI_B0_SFR + 0Ch ; USCI_B0 Receive Buffer 8
625 SD_TXBUF .equ eUSCI_B0_SFR + 0Eh ; USCI_B0 Transmit Buffer 8
626 SD_IFG .equ eUSCI_B0_SFR + 2Ch ; USCI_B0 Interrupt Flags Register
629 ; ----------------------------------------------------------------------
630 ; POWER ON RESET AND INITIALIZATION : RTC REGISTERS
631 ; ----------------------------------------------------------------------
632 RTC_B ; declare RTC type
633 RTCCTL01 .equ RTC_B_SFR + 00h
634 RTCCTL0 .equ RTC_B_SFR + 00h
635 RTCCTL1 .equ RTC_B_SFR + 01h
636 RTCCTL23 .equ RTC_B_SFR + 02h
637 RTCPS0CTL .equ RTC_B_SFR + 08h
638 RTCPS1CTL .equ RTC_B_SFR + 0Ah
639 RTCPS .equ RTC_B_SFR + 0Ch
640 RTCIV .equ RTC_B_SFR + 0Eh
641 RTCSEC .equ RTC_B_SFR + 10h
642 RTCMIN .equ RTC_B_SFR + 11h
643 RTCHOUR .equ RTC_B_SFR + 12h
644 RTCDOW .equ RTC_B_SFR + 13h
645 RTCDAY .equ RTC_B_SFR + 14h
646 RTCMON .equ RTC_B_SFR + 15h
647 RTCYEAR .equ RTC_B_SFR + 16h
653 ; ----------------------------------------------------------------------
654 ; POWER ON RESET AND INITIALIZATION : SYS REGISTERS
655 ; ----------------------------------------------------------------------
657 SYSRSTIV .equ SYS_SFR + 001Eh