2 * Copyright (C) 2008 Apple Inc. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
14 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
16 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
17 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
18 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
20 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
21 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
23 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #ifndef X86Assembler_h
27 #define X86Assembler_h
29 #if ENABLE(ASSEMBLER) && (CPU(X86) || CPU(X86_64))
31 #include "AssemblerBuffer.h"
33 #include <wtf/Assertions.h>
34 #include <wtf/Vector.h>
38 inline bool CAN_SIGN_EXTEND_8_32(int32_t value) { return value == (int32_t)(signed char)value; }
40 namespace X86Registers {
77 typedef X86Registers::RegisterID RegisterID;
78 typedef X86Registers::XMMRegisterID XMMRegisterID;
79 typedef XMMRegisterID FPRegisterID;
99 ConditionC = ConditionB,
100 ConditionNC = ConditionAE,
109 OP_2BYTE_ESCAPE = 0x0F,
114 PRE_PREDICT_BRANCH_NOT_TAKEN = 0x2E,
125 OP_MOVSXD_GvEv = 0x63,
127 PRE_OPERAND_SIZE = 0x66,
130 OP_IMUL_GvEvIz = 0x69,
131 OP_GROUP1_EbIb = 0x80,
132 OP_GROUP1_EvIz = 0x81,
133 OP_GROUP1_EvIb = 0x83,
139 OP_GROUP1A_Ev = 0x8F,
144 OP_GROUP2_EvIb = 0xC1,
146 OP_GROUP11_EvIz = 0xC7,
148 OP_GROUP2_Ev1 = 0xD1,
149 OP_GROUP2_EvCL = 0xD3,
150 OP_CALL_rel32 = 0xE8,
154 OP_GROUP3_EbIb = 0xF6,
156 OP_GROUP3_EvIz = 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test.
161 OP2_MOVSD_VsdWsd = 0x10,
162 OP2_MOVSD_WsdVsd = 0x11,
163 OP2_CVTSI2SD_VsdEd = 0x2A,
164 OP2_CVTTSD2SI_GdWsd = 0x2C,
165 OP2_UCOMISD_VsdWsd = 0x2E,
166 OP2_ADDSD_VsdWsd = 0x58,
167 OP2_MULSD_VsdWsd = 0x59,
168 OP2_SUBSD_VsdWsd = 0x5C,
169 OP2_DIVSD_VsdWsd = 0x5E,
170 OP2_SQRTSD_VsdWsd = 0x51,
171 OP2_XORPD_VpdWpd = 0x57,
172 OP2_MOVD_VdEd = 0x6E,
173 OP2_MOVD_EdVd = 0x7E,
174 OP2_JCC_rel32 = 0x80,
176 OP2_IMUL_GvEv = 0xAF,
177 OP2_MOVZX_GvEb = 0xB6,
178 OP2_MOVZX_GvEw = 0xB7,
179 OP2_PEXTRW_GdUdIb = 0xC5,
182 TwoByteOpcodeID jccRel32(Condition cond)
184 return (TwoByteOpcodeID)(OP2_JCC_rel32 + cond);
187 TwoByteOpcodeID setccOpcode(Condition cond)
189 return (TwoByteOpcodeID)(OP_SETCC + cond);
219 class X86InstructionFormatter;
223 friend class X86Assembler;
224 friend class X86InstructionFormatter;
241 friend class X86Assembler;
242 friend class X86InstructionFormatter;
250 bool isUsed() const { return m_used; }
251 bool isSet() const { return (m_offset != -1); }
252 void used() { m_used = true; }
258 ASSERT(m_offset == offset);
269 size_t size() const { return m_formatter.size(); }
273 void push_r(RegisterID reg)
275 m_formatter.oneByteOp(OP_PUSH_EAX, reg);
278 void pop_r(RegisterID reg)
280 m_formatter.oneByteOp(OP_POP_EAX, reg);
283 void push_i32(int imm)
285 m_formatter.oneByteOp(OP_PUSH_Iz);
286 m_formatter.immediate32(imm);
289 void push_m(int offset, RegisterID base)
291 m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_PUSH, base, offset);
294 void pop_m(int offset, RegisterID base)
296 m_formatter.oneByteOp(OP_GROUP1A_Ev, GROUP1A_OP_POP, base, offset);
299 // Arithmetic operations:
302 void adcl_im(int imm, void* addr)
304 if (CAN_SIGN_EXTEND_8_32(imm)) {
305 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADC, addr);
306 m_formatter.immediate8(imm);
308 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADC, addr);
309 m_formatter.immediate32(imm);
314 void addl_rr(RegisterID src, RegisterID dst)
316 m_formatter.oneByteOp(OP_ADD_EvGv, src, dst);
319 void addl_mr(int offset, RegisterID base, RegisterID dst)
321 m_formatter.oneByteOp(OP_ADD_GvEv, dst, base, offset);
324 void addl_rm(RegisterID src, int offset, RegisterID base)
326 m_formatter.oneByteOp(OP_ADD_EvGv, src, base, offset);
329 void addl_ir(int imm, RegisterID dst)
331 if (CAN_SIGN_EXTEND_8_32(imm)) {
332 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
333 m_formatter.immediate8(imm);
335 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
336 m_formatter.immediate32(imm);
340 void addl_im(int imm, int offset, RegisterID base)
342 if (CAN_SIGN_EXTEND_8_32(imm)) {
343 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
344 m_formatter.immediate8(imm);
346 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
347 m_formatter.immediate32(imm);
352 void addq_rr(RegisterID src, RegisterID dst)
354 m_formatter.oneByteOp64(OP_ADD_EvGv, src, dst);
357 void addq_ir(int imm, RegisterID dst)
359 if (CAN_SIGN_EXTEND_8_32(imm)) {
360 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, dst);
361 m_formatter.immediate8(imm);
363 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, dst);
364 m_formatter.immediate32(imm);
368 void addq_im(int imm, int offset, RegisterID base)
370 if (CAN_SIGN_EXTEND_8_32(imm)) {
371 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_ADD, base, offset);
372 m_formatter.immediate8(imm);
374 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_ADD, base, offset);
375 m_formatter.immediate32(imm);
379 void addl_im(int imm, void* addr)
381 if (CAN_SIGN_EXTEND_8_32(imm)) {
382 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_ADD, addr);
383 m_formatter.immediate8(imm);
385 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_ADD, addr);
386 m_formatter.immediate32(imm);
391 void andl_rr(RegisterID src, RegisterID dst)
393 m_formatter.oneByteOp(OP_AND_EvGv, src, dst);
396 void andl_mr(int offset, RegisterID base, RegisterID dst)
398 m_formatter.oneByteOp(OP_AND_GvEv, dst, base, offset);
401 void andl_rm(RegisterID src, int offset, RegisterID base)
403 m_formatter.oneByteOp(OP_AND_EvGv, src, base, offset);
406 void andl_ir(int imm, RegisterID dst)
408 if (CAN_SIGN_EXTEND_8_32(imm)) {
409 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);
410 m_formatter.immediate8(imm);
412 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);
413 m_formatter.immediate32(imm);
417 void andl_im(int imm, int offset, RegisterID base)
419 if (CAN_SIGN_EXTEND_8_32(imm)) {
420 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, base, offset);
421 m_formatter.immediate8(imm);
423 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, base, offset);
424 m_formatter.immediate32(imm);
429 void andq_rr(RegisterID src, RegisterID dst)
431 m_formatter.oneByteOp64(OP_AND_EvGv, src, dst);
434 void andq_ir(int imm, RegisterID dst)
436 if (CAN_SIGN_EXTEND_8_32(imm)) {
437 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_AND, dst);
438 m_formatter.immediate8(imm);
440 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_AND, dst);
441 m_formatter.immediate32(imm);
445 void andl_im(int imm, void* addr)
447 if (CAN_SIGN_EXTEND_8_32(imm)) {
448 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_AND, addr);
449 m_formatter.immediate8(imm);
451 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_AND, addr);
452 m_formatter.immediate32(imm);
457 void negl_r(RegisterID dst)
459 m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, dst);
462 void negl_m(int offset, RegisterID base)
464 m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NEG, base, offset);
467 void notl_r(RegisterID dst)
469 m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, dst);
472 void notl_m(int offset, RegisterID base)
474 m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_NOT, base, offset);
477 void orl_rr(RegisterID src, RegisterID dst)
479 m_formatter.oneByteOp(OP_OR_EvGv, src, dst);
482 void orl_mr(int offset, RegisterID base, RegisterID dst)
484 m_formatter.oneByteOp(OP_OR_GvEv, dst, base, offset);
487 void orl_rm(RegisterID src, int offset, RegisterID base)
489 m_formatter.oneByteOp(OP_OR_EvGv, src, base, offset);
492 void orl_ir(int imm, RegisterID dst)
494 if (CAN_SIGN_EXTEND_8_32(imm)) {
495 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);
496 m_formatter.immediate8(imm);
498 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
499 m_formatter.immediate32(imm);
503 void orl_im(int imm, int offset, RegisterID base)
505 if (CAN_SIGN_EXTEND_8_32(imm)) {
506 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, base, offset);
507 m_formatter.immediate8(imm);
509 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, base, offset);
510 m_formatter.immediate32(imm);
515 void orq_rr(RegisterID src, RegisterID dst)
517 m_formatter.oneByteOp64(OP_OR_EvGv, src, dst);
520 void orq_ir(int imm, RegisterID dst)
522 if (CAN_SIGN_EXTEND_8_32(imm)) {
523 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_OR, dst);
524 m_formatter.immediate8(imm);
526 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_OR, dst);
527 m_formatter.immediate32(imm);
531 void orl_im(int imm, void* addr)
533 if (CAN_SIGN_EXTEND_8_32(imm)) {
534 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_OR, addr);
535 m_formatter.immediate8(imm);
537 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_OR, addr);
538 m_formatter.immediate32(imm);
543 void subl_rr(RegisterID src, RegisterID dst)
545 m_formatter.oneByteOp(OP_SUB_EvGv, src, dst);
548 void subl_mr(int offset, RegisterID base, RegisterID dst)
550 m_formatter.oneByteOp(OP_SUB_GvEv, dst, base, offset);
553 void subl_rm(RegisterID src, int offset, RegisterID base)
555 m_formatter.oneByteOp(OP_SUB_EvGv, src, base, offset);
558 void subl_ir(int imm, RegisterID dst)
560 if (CAN_SIGN_EXTEND_8_32(imm)) {
561 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);
562 m_formatter.immediate8(imm);
564 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
565 m_formatter.immediate32(imm);
569 void subl_im(int imm, int offset, RegisterID base)
571 if (CAN_SIGN_EXTEND_8_32(imm)) {
572 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, base, offset);
573 m_formatter.immediate8(imm);
575 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, base, offset);
576 m_formatter.immediate32(imm);
581 void subq_rr(RegisterID src, RegisterID dst)
583 m_formatter.oneByteOp64(OP_SUB_EvGv, src, dst);
586 void subq_ir(int imm, RegisterID dst)
588 if (CAN_SIGN_EXTEND_8_32(imm)) {
589 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_SUB, dst);
590 m_formatter.immediate8(imm);
592 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_SUB, dst);
593 m_formatter.immediate32(imm);
597 void subl_im(int imm, void* addr)
599 if (CAN_SIGN_EXTEND_8_32(imm)) {
600 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_SUB, addr);
601 m_formatter.immediate8(imm);
603 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_SUB, addr);
604 m_formatter.immediate32(imm);
609 void xorl_rr(RegisterID src, RegisterID dst)
611 m_formatter.oneByteOp(OP_XOR_EvGv, src, dst);
614 void xorl_mr(int offset, RegisterID base, RegisterID dst)
616 m_formatter.oneByteOp(OP_XOR_GvEv, dst, base, offset);
619 void xorl_rm(RegisterID src, int offset, RegisterID base)
621 m_formatter.oneByteOp(OP_XOR_EvGv, src, base, offset);
624 void xorl_im(int imm, int offset, RegisterID base)
626 if (CAN_SIGN_EXTEND_8_32(imm)) {
627 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, base, offset);
628 m_formatter.immediate8(imm);
630 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, base, offset);
631 m_formatter.immediate32(imm);
635 void xorl_ir(int imm, RegisterID dst)
637 if (CAN_SIGN_EXTEND_8_32(imm)) {
638 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);
639 m_formatter.immediate8(imm);
641 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
642 m_formatter.immediate32(imm);
647 void xorq_rr(RegisterID src, RegisterID dst)
649 m_formatter.oneByteOp64(OP_XOR_EvGv, src, dst);
652 void xorq_ir(int imm, RegisterID dst)
654 if (CAN_SIGN_EXTEND_8_32(imm)) {
655 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_XOR, dst);
656 m_formatter.immediate8(imm);
658 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_XOR, dst);
659 m_formatter.immediate32(imm);
664 void sarl_i8r(int imm, RegisterID dst)
667 m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);
669 m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);
670 m_formatter.immediate8(imm);
674 void sarl_CLr(RegisterID dst)
676 m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);
679 void shrl_i8r(int imm, RegisterID dst)
682 m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst);
684 m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SHR, dst);
685 m_formatter.immediate8(imm);
689 void shrl_CLr(RegisterID dst)
691 m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHR, dst);
694 void shll_i8r(int imm, RegisterID dst)
697 m_formatter.oneByteOp(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst);
699 m_formatter.oneByteOp(OP_GROUP2_EvIb, GROUP2_OP_SHL, dst);
700 m_formatter.immediate8(imm);
704 void shll_CLr(RegisterID dst)
706 m_formatter.oneByteOp(OP_GROUP2_EvCL, GROUP2_OP_SHL, dst);
710 void sarq_CLr(RegisterID dst)
712 m_formatter.oneByteOp64(OP_GROUP2_EvCL, GROUP2_OP_SAR, dst);
715 void sarq_i8r(int imm, RegisterID dst)
718 m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SAR, dst);
720 m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SAR, dst);
721 m_formatter.immediate8(imm);
726 void imull_rr(RegisterID src, RegisterID dst)
728 m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, src);
731 void imull_mr(int offset, RegisterID base, RegisterID dst)
733 m_formatter.twoByteOp(OP2_IMUL_GvEv, dst, base, offset);
736 void imull_i32r(RegisterID src, int32_t value, RegisterID dst)
738 m_formatter.oneByteOp(OP_IMUL_GvEvIz, dst, src);
739 m_formatter.immediate32(value);
742 void idivl_r(RegisterID dst)
744 m_formatter.oneByteOp(OP_GROUP3_Ev, GROUP3_OP_IDIV, dst);
749 void cmpl_rr(RegisterID src, RegisterID dst)
751 m_formatter.oneByteOp(OP_CMP_EvGv, src, dst);
754 void cmpl_rm(RegisterID src, int offset, RegisterID base)
756 m_formatter.oneByteOp(OP_CMP_EvGv, src, base, offset);
759 void cmpl_mr(int offset, RegisterID base, RegisterID src)
761 m_formatter.oneByteOp(OP_CMP_GvEv, src, base, offset);
764 void cmpl_ir(int imm, RegisterID dst)
766 if (CAN_SIGN_EXTEND_8_32(imm)) {
767 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst);
768 m_formatter.immediate8(imm);
770 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
771 m_formatter.immediate32(imm);
775 void cmpl_ir_force32(int imm, RegisterID dst)
777 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
778 m_formatter.immediate32(imm);
781 void cmpl_im(int imm, int offset, RegisterID base)
783 if (CAN_SIGN_EXTEND_8_32(imm)) {
784 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, offset);
785 m_formatter.immediate8(imm);
787 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset);
788 m_formatter.immediate32(imm);
792 void cmpb_im(int imm, int offset, RegisterID base)
794 m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_CMP, base, offset);
795 m_formatter.immediate8(imm);
798 void cmpb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
800 m_formatter.oneByteOp(OP_GROUP1_EbIb, GROUP1_OP_CMP, base, index, scale, offset);
801 m_formatter.immediate8(imm);
804 void cmpl_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
806 if (CAN_SIGN_EXTEND_8_32(imm)) {
807 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, index, scale, offset);
808 m_formatter.immediate8(imm);
810 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, index, scale, offset);
811 m_formatter.immediate32(imm);
815 void cmpl_im_force32(int imm, int offset, RegisterID base)
817 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset);
818 m_formatter.immediate32(imm);
822 void cmpq_rr(RegisterID src, RegisterID dst)
824 m_formatter.oneByteOp64(OP_CMP_EvGv, src, dst);
827 void cmpq_rm(RegisterID src, int offset, RegisterID base)
829 m_formatter.oneByteOp64(OP_CMP_EvGv, src, base, offset);
832 void cmpq_mr(int offset, RegisterID base, RegisterID src)
834 m_formatter.oneByteOp64(OP_CMP_GvEv, src, base, offset);
837 void cmpq_ir(int imm, RegisterID dst)
839 if (CAN_SIGN_EXTEND_8_32(imm)) {
840 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, dst);
841 m_formatter.immediate8(imm);
843 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, dst);
844 m_formatter.immediate32(imm);
848 void cmpq_im(int imm, int offset, RegisterID base)
850 if (CAN_SIGN_EXTEND_8_32(imm)) {
851 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, offset);
852 m_formatter.immediate8(imm);
854 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, offset);
855 m_formatter.immediate32(imm);
859 void cmpq_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
861 if (CAN_SIGN_EXTEND_8_32(imm)) {
862 m_formatter.oneByteOp64(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, index, scale, offset);
863 m_formatter.immediate8(imm);
865 m_formatter.oneByteOp64(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, index, scale, offset);
866 m_formatter.immediate32(imm);
870 void cmpl_rm(RegisterID reg, void* addr)
872 m_formatter.oneByteOp(OP_CMP_EvGv, reg, addr);
875 void cmpl_im(int imm, void* addr)
877 if (CAN_SIGN_EXTEND_8_32(imm)) {
878 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, addr);
879 m_formatter.immediate8(imm);
881 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, addr);
882 m_formatter.immediate32(imm);
887 void cmpw_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
889 m_formatter.prefix(PRE_OPERAND_SIZE);
890 m_formatter.oneByteOp(OP_CMP_EvGv, src, base, index, scale, offset);
893 void cmpw_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
895 if (CAN_SIGN_EXTEND_8_32(imm)) {
896 m_formatter.prefix(PRE_OPERAND_SIZE);
897 m_formatter.oneByteOp(OP_GROUP1_EvIb, GROUP1_OP_CMP, base, index, scale, offset);
898 m_formatter.immediate8(imm);
900 m_formatter.prefix(PRE_OPERAND_SIZE);
901 m_formatter.oneByteOp(OP_GROUP1_EvIz, GROUP1_OP_CMP, base, index, scale, offset);
902 m_formatter.immediate16(imm);
906 void testl_rr(RegisterID src, RegisterID dst)
908 m_formatter.oneByteOp(OP_TEST_EvGv, src, dst);
911 void testl_i32r(int imm, RegisterID dst)
913 m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
914 m_formatter.immediate32(imm);
917 void testl_i32m(int imm, int offset, RegisterID base)
919 m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, offset);
920 m_formatter.immediate32(imm);
923 void testb_im(int imm, int offset, RegisterID base)
925 m_formatter.oneByteOp(OP_GROUP3_EbIb, GROUP3_OP_TEST, base, offset);
926 m_formatter.immediate8(imm);
929 void testb_im(int imm, int offset, RegisterID base, RegisterID index, int scale)
931 m_formatter.oneByteOp(OP_GROUP3_EbIb, GROUP3_OP_TEST, base, index, scale, offset);
932 m_formatter.immediate8(imm);
935 void testl_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
937 m_formatter.oneByteOp(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, index, scale, offset);
938 m_formatter.immediate32(imm);
942 void testq_rr(RegisterID src, RegisterID dst)
944 m_formatter.oneByteOp64(OP_TEST_EvGv, src, dst);
947 void testq_i32r(int imm, RegisterID dst)
949 m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, dst);
950 m_formatter.immediate32(imm);
953 void testq_i32m(int imm, int offset, RegisterID base)
955 m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, offset);
956 m_formatter.immediate32(imm);
959 void testq_i32m(int imm, int offset, RegisterID base, RegisterID index, int scale)
961 m_formatter.oneByteOp64(OP_GROUP3_EvIz, GROUP3_OP_TEST, base, index, scale, offset);
962 m_formatter.immediate32(imm);
966 void testw_rr(RegisterID src, RegisterID dst)
968 m_formatter.prefix(PRE_OPERAND_SIZE);
969 m_formatter.oneByteOp(OP_TEST_EvGv, src, dst);
972 void testb_i8r(int imm, RegisterID dst)
974 m_formatter.oneByteOp8(OP_GROUP3_EbIb, GROUP3_OP_TEST, dst);
975 m_formatter.immediate8(imm);
978 void setCC_r(Condition cond, RegisterID dst)
980 m_formatter.twoByteOp8(setccOpcode(cond), (GroupOpcodeID)0, dst);
983 void sete_r(RegisterID dst)
985 m_formatter.twoByteOp8(setccOpcode(ConditionE), (GroupOpcodeID)0, dst);
988 void setz_r(RegisterID dst)
993 void setne_r(RegisterID dst)
995 m_formatter.twoByteOp8(setccOpcode(ConditionNE), (GroupOpcodeID)0, dst);
998 void setnz_r(RegisterID dst)
1003 // Various move ops:
1007 m_formatter.oneByteOp(OP_CDQ);
1010 void xchgl_rr(RegisterID src, RegisterID dst)
1012 m_formatter.oneByteOp(OP_XCHG_EvGv, src, dst);
1016 void xchgq_rr(RegisterID src, RegisterID dst)
1018 m_formatter.oneByteOp64(OP_XCHG_EvGv, src, dst);
1022 void movl_rr(RegisterID src, RegisterID dst)
1024 m_formatter.oneByteOp(OP_MOV_EvGv, src, dst);
1027 void movl_rm(RegisterID src, int offset, RegisterID base)
1029 m_formatter.oneByteOp(OP_MOV_EvGv, src, base, offset);
1032 void movl_rm_disp32(RegisterID src, int offset, RegisterID base)
1034 m_formatter.oneByteOp_disp32(OP_MOV_EvGv, src, base, offset);
1037 void movl_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
1039 m_formatter.oneByteOp(OP_MOV_EvGv, src, base, index, scale, offset);
1042 void movl_mEAX(void* addr)
1044 m_formatter.oneByteOp(OP_MOV_EAXOv);
1046 m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
1048 m_formatter.immediate32(reinterpret_cast<int>(addr));
1052 void movl_mr(int offset, RegisterID base, RegisterID dst)
1054 m_formatter.oneByteOp(OP_MOV_GvEv, dst, base, offset);
1057 void movl_mr_disp32(int offset, RegisterID base, RegisterID dst)
1059 m_formatter.oneByteOp_disp32(OP_MOV_GvEv, dst, base, offset);
1062 void movl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
1064 m_formatter.oneByteOp(OP_MOV_GvEv, dst, base, index, scale, offset);
1067 void movl_i32r(int imm, RegisterID dst)
1069 m_formatter.oneByteOp(OP_MOV_EAXIv, dst);
1070 m_formatter.immediate32(imm);
1073 void movl_i32m(int imm, int offset, RegisterID base)
1075 m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, base, offset);
1076 m_formatter.immediate32(imm);
1079 void movl_EAXm(void* addr)
1081 m_formatter.oneByteOp(OP_MOV_OvEAX);
1083 m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
1085 m_formatter.immediate32(reinterpret_cast<int>(addr));
1090 void movq_rr(RegisterID src, RegisterID dst)
1092 m_formatter.oneByteOp64(OP_MOV_EvGv, src, dst);
1095 void movq_rm(RegisterID src, int offset, RegisterID base)
1097 m_formatter.oneByteOp64(OP_MOV_EvGv, src, base, offset);
1100 void movq_rm_disp32(RegisterID src, int offset, RegisterID base)
1102 m_formatter.oneByteOp64_disp32(OP_MOV_EvGv, src, base, offset);
1105 void movq_rm(RegisterID src, int offset, RegisterID base, RegisterID index, int scale)
1107 m_formatter.oneByteOp64(OP_MOV_EvGv, src, base, index, scale, offset);
1110 void movq_mEAX(void* addr)
1112 m_formatter.oneByteOp64(OP_MOV_EAXOv);
1113 m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
1116 void movq_EAXm(void* addr)
1118 m_formatter.oneByteOp64(OP_MOV_OvEAX);
1119 m_formatter.immediate64(reinterpret_cast<int64_t>(addr));
1122 void movq_mr(int offset, RegisterID base, RegisterID dst)
1124 m_formatter.oneByteOp64(OP_MOV_GvEv, dst, base, offset);
1127 void movq_mr_disp32(int offset, RegisterID base, RegisterID dst)
1129 m_formatter.oneByteOp64_disp32(OP_MOV_GvEv, dst, base, offset);
1132 void movq_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
1134 m_formatter.oneByteOp64(OP_MOV_GvEv, dst, base, index, scale, offset);
1137 void movq_i32m(int imm, int offset, RegisterID base)
1139 m_formatter.oneByteOp64(OP_GROUP11_EvIz, GROUP11_MOV, base, offset);
1140 m_formatter.immediate32(imm);
1143 void movq_i64r(int64_t imm, RegisterID dst)
1145 m_formatter.oneByteOp64(OP_MOV_EAXIv, dst);
1146 m_formatter.immediate64(imm);
1149 void movsxd_rr(RegisterID src, RegisterID dst)
1151 m_formatter.oneByteOp64(OP_MOVSXD_GvEv, dst, src);
1156 void movl_rm(RegisterID src, void* addr)
1158 if (src == X86Registers::eax)
1161 m_formatter.oneByteOp(OP_MOV_EvGv, src, addr);
1164 void movl_mr(void* addr, RegisterID dst)
1166 if (dst == X86Registers::eax)
1169 m_formatter.oneByteOp(OP_MOV_GvEv, dst, addr);
1172 void movl_i32m(int imm, void* addr)
1174 m_formatter.oneByteOp(OP_GROUP11_EvIz, GROUP11_MOV, addr);
1175 m_formatter.immediate32(imm);
1179 void movzwl_mr(int offset, RegisterID base, RegisterID dst)
1181 m_formatter.twoByteOp(OP2_MOVZX_GvEw, dst, base, offset);
1184 void movzwl_mr(int offset, RegisterID base, RegisterID index, int scale, RegisterID dst)
1186 m_formatter.twoByteOp(OP2_MOVZX_GvEw, dst, base, index, scale, offset);
1189 void movzbl_rr(RegisterID src, RegisterID dst)
1191 // In 64-bit, this may cause an unnecessary REX to be planted (if the dst register
1192 // is in the range ESP-EDI, and the src would not have required a REX). Unneeded
1193 // REX prefixes are defined to be silently ignored by the processor.
1194 m_formatter.twoByteOp8(OP2_MOVZX_GvEb, dst, src);
1197 void leal_mr(int offset, RegisterID base, RegisterID dst)
1199 m_formatter.oneByteOp(OP_LEA, dst, base, offset);
1202 void leaq_mr(int offset, RegisterID base, RegisterID dst)
1204 m_formatter.oneByteOp64(OP_LEA, dst, base, offset);
1212 m_formatter.oneByteOp(OP_CALL_rel32);
1213 return m_formatter.immediateRel32();
1216 JmpSrc call(RegisterID dst)
1218 m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_CALLN, dst);
1219 return JmpSrc(m_formatter.size());
1222 void call_m(int offset, RegisterID base)
1224 m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_CALLN, base, offset);
1229 m_formatter.oneByteOp(OP_JMP_rel32);
1230 return m_formatter.immediateRel32();
1233 // Return a JmpSrc so we have a label to the jump, so we can use this
1234 // To make a tail recursive call on x86-64. The MacroAssembler
1235 // really shouldn't wrap this as a Jump, since it can't be linked. :-/
1236 JmpSrc jmp_r(RegisterID dst)
1238 m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, dst);
1239 return JmpSrc(m_formatter.size());
1242 void jmp_m(int offset, RegisterID base)
1244 m_formatter.oneByteOp(OP_GROUP5_Ev, GROUP5_OP_JMPN, base, offset);
1249 m_formatter.twoByteOp(jccRel32(ConditionNE));
1250 return m_formatter.immediateRel32();
1260 m_formatter.twoByteOp(jccRel32(ConditionE));
1261 return m_formatter.immediateRel32();
1271 m_formatter.twoByteOp(jccRel32(ConditionL));
1272 return m_formatter.immediateRel32();
1277 m_formatter.twoByteOp(jccRel32(ConditionB));
1278 return m_formatter.immediateRel32();
1283 m_formatter.twoByteOp(jccRel32(ConditionLE));
1284 return m_formatter.immediateRel32();
1289 m_formatter.twoByteOp(jccRel32(ConditionBE));
1290 return m_formatter.immediateRel32();
1295 m_formatter.twoByteOp(jccRel32(ConditionGE));
1296 return m_formatter.immediateRel32();
1301 m_formatter.twoByteOp(jccRel32(ConditionG));
1302 return m_formatter.immediateRel32();
1307 m_formatter.twoByteOp(jccRel32(ConditionA));
1308 return m_formatter.immediateRel32();
1313 m_formatter.twoByteOp(jccRel32(ConditionAE));
1314 return m_formatter.immediateRel32();
1319 m_formatter.twoByteOp(jccRel32(ConditionO));
1320 return m_formatter.immediateRel32();
1325 m_formatter.twoByteOp(jccRel32(ConditionP));
1326 return m_formatter.immediateRel32();
1331 m_formatter.twoByteOp(jccRel32(ConditionS));
1332 return m_formatter.immediateRel32();
1335 JmpSrc jCC(Condition cond)
1337 m_formatter.twoByteOp(jccRel32(cond));
1338 return m_formatter.immediateRel32();
1343 void addsd_rr(XMMRegisterID src, XMMRegisterID dst)
1345 m_formatter.prefix(PRE_SSE_F2);
1346 m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1349 void addsd_mr(int offset, RegisterID base, XMMRegisterID dst)
1351 m_formatter.prefix(PRE_SSE_F2);
1352 m_formatter.twoByteOp(OP2_ADDSD_VsdWsd, (RegisterID)dst, base, offset);
1355 void cvtsi2sd_rr(RegisterID src, XMMRegisterID dst)
1357 m_formatter.prefix(PRE_SSE_F2);
1358 m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, src);
1361 void cvtsi2sd_mr(int offset, RegisterID base, XMMRegisterID dst)
1363 m_formatter.prefix(PRE_SSE_F2);
1364 m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, base, offset);
1368 void cvtsi2sd_mr(void* address, XMMRegisterID dst)
1370 m_formatter.prefix(PRE_SSE_F2);
1371 m_formatter.twoByteOp(OP2_CVTSI2SD_VsdEd, (RegisterID)dst, address);
1375 void cvttsd2si_rr(XMMRegisterID src, RegisterID dst)
1377 m_formatter.prefix(PRE_SSE_F2);
1378 m_formatter.twoByteOp(OP2_CVTTSD2SI_GdWsd, dst, (RegisterID)src);
1381 void movd_rr(XMMRegisterID src, RegisterID dst)
1383 m_formatter.prefix(PRE_SSE_66);
1384 m_formatter.twoByteOp(OP2_MOVD_EdVd, (RegisterID)src, dst);
1388 void movq_rr(XMMRegisterID src, RegisterID dst)
1390 m_formatter.prefix(PRE_SSE_66);
1391 m_formatter.twoByteOp64(OP2_MOVD_EdVd, (RegisterID)src, dst);
1394 void movq_rr(RegisterID src, XMMRegisterID dst)
1396 m_formatter.prefix(PRE_SSE_66);
1397 m_formatter.twoByteOp64(OP2_MOVD_VdEd, (RegisterID)dst, src);
1401 void movsd_rm(XMMRegisterID src, int offset, RegisterID base)
1403 m_formatter.prefix(PRE_SSE_F2);
1404 m_formatter.twoByteOp(OP2_MOVSD_WsdVsd, (RegisterID)src, base, offset);
1407 void movsd_mr(int offset, RegisterID base, XMMRegisterID dst)
1409 m_formatter.prefix(PRE_SSE_F2);
1410 m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, base, offset);
1414 void movsd_mr(const void* address, XMMRegisterID dst)
1416 m_formatter.prefix(PRE_SSE_F2);
1417 m_formatter.twoByteOp(OP2_MOVSD_VsdWsd, (RegisterID)dst, address);
1421 void mulsd_rr(XMMRegisterID src, XMMRegisterID dst)
1423 m_formatter.prefix(PRE_SSE_F2);
1424 m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1427 void mulsd_mr(int offset, RegisterID base, XMMRegisterID dst)
1429 m_formatter.prefix(PRE_SSE_F2);
1430 m_formatter.twoByteOp(OP2_MULSD_VsdWsd, (RegisterID)dst, base, offset);
1433 void pextrw_irr(int whichWord, XMMRegisterID src, RegisterID dst)
1435 m_formatter.prefix(PRE_SSE_66);
1436 m_formatter.twoByteOp(OP2_PEXTRW_GdUdIb, (RegisterID)dst, (RegisterID)src);
1437 m_formatter.immediate8(whichWord);
1440 void subsd_rr(XMMRegisterID src, XMMRegisterID dst)
1442 m_formatter.prefix(PRE_SSE_F2);
1443 m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1446 void subsd_mr(int offset, RegisterID base, XMMRegisterID dst)
1448 m_formatter.prefix(PRE_SSE_F2);
1449 m_formatter.twoByteOp(OP2_SUBSD_VsdWsd, (RegisterID)dst, base, offset);
1452 void ucomisd_rr(XMMRegisterID src, XMMRegisterID dst)
1454 m_formatter.prefix(PRE_SSE_66);
1455 m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1458 void ucomisd_mr(int offset, RegisterID base, XMMRegisterID dst)
1460 m_formatter.prefix(PRE_SSE_66);
1461 m_formatter.twoByteOp(OP2_UCOMISD_VsdWsd, (RegisterID)dst, base, offset);
1464 void divsd_rr(XMMRegisterID src, XMMRegisterID dst)
1466 m_formatter.prefix(PRE_SSE_F2);
1467 m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1470 void divsd_mr(int offset, RegisterID base, XMMRegisterID dst)
1472 m_formatter.prefix(PRE_SSE_F2);
1473 m_formatter.twoByteOp(OP2_DIVSD_VsdWsd, (RegisterID)dst, base, offset);
1476 void xorpd_rr(XMMRegisterID src, XMMRegisterID dst)
1478 m_formatter.prefix(PRE_SSE_66);
1479 m_formatter.twoByteOp(OP2_XORPD_VpdWpd, (RegisterID)dst, (RegisterID)src);
1482 void sqrtsd_rr(XMMRegisterID src, XMMRegisterID dst)
1484 m_formatter.prefix(PRE_SSE_F2);
1485 m_formatter.twoByteOp(OP2_SQRTSD_VsdWsd, (RegisterID)dst, (RegisterID)src);
1488 // Misc instructions:
1492 m_formatter.oneByteOp(OP_INT3);
1497 m_formatter.oneByteOp(OP_RET);
1500 void predictNotTaken()
1502 m_formatter.prefix(PRE_PREDICT_BRANCH_NOT_TAKEN);
1505 // Assembler admin methods:
1509 return JmpDst(m_formatter.size());
1512 static JmpDst labelFor(JmpSrc jump, intptr_t offset = 0)
1514 return JmpDst(jump.m_offset + offset);
1517 JmpDst align(int alignment)
1519 while (!m_formatter.isAligned(alignment))
1520 m_formatter.oneByteOp(OP_HLT);
1525 // Linking & patching:
1527 // 'link' and 'patch' methods are for use on unprotected code - such as the code
1528 // within the AssemblerBuffer, and code being patched by the patch buffer. Once
1529 // code has been finalized it is (platform support permitting) within a non-
1530 // writable region of memory; to modify the code in an execute-only execuable
1531 // pool the 'repatch' and 'relink' methods should be used.
1533 void linkJump(JmpSrc from, JmpDst to)
1535 ASSERT(from.m_offset != -1);
1536 ASSERT(to.m_offset != -1);
1538 char* code = reinterpret_cast<char*>(m_formatter.data());
1539 setRel32(code + from.m_offset, code + to.m_offset);
1542 static void linkJump(void* code, JmpSrc from, void* to)
1544 ASSERT(from.m_offset != -1);
1546 setRel32(reinterpret_cast<char*>(code) + from.m_offset, to);
1549 static void linkCall(void* code, JmpSrc from, void* to)
1551 ASSERT(from.m_offset != -1);
1553 setRel32(reinterpret_cast<char*>(code) + from.m_offset, to);
1556 static void linkPointer(void* code, JmpDst where, void* value)
1558 ASSERT(where.m_offset != -1);
1560 setPointer(reinterpret_cast<char*>(code) + where.m_offset, value);
1563 static void relinkJump(void* from, void* to)
1568 static void relinkCall(void* from, void* to)
1573 static void repatchInt32(void* where, int32_t value)
1575 setInt32(where, value);
1578 static void repatchPointer(void* where, void* value)
1580 setPointer(where, value);
1583 static unsigned getCallReturnOffset(JmpSrc call)
1585 ASSERT(call.m_offset >= 0);
1586 return call.m_offset;
1589 static void* getRelocatedAddress(void* code, JmpSrc jump)
1591 ASSERT(jump.m_offset != -1);
1593 return reinterpret_cast<void*>(reinterpret_cast<ptrdiff_t>(code) + jump.m_offset);
1596 static void* getRelocatedAddress(void* code, JmpDst destination)
1598 ASSERT(destination.m_offset != -1);
1600 return reinterpret_cast<void*>(reinterpret_cast<ptrdiff_t>(code) + destination.m_offset);
1603 static int getDifferenceBetweenLabels(JmpDst src, JmpDst dst)
1605 return dst.m_offset - src.m_offset;
1608 static int getDifferenceBetweenLabels(JmpDst src, JmpSrc dst)
1610 return dst.m_offset - src.m_offset;
1613 static int getDifferenceBetweenLabels(JmpSrc src, JmpDst dst)
1615 return dst.m_offset - src.m_offset;
1618 void* executableCopy(ExecutablePool* allocator)
1620 void* copy = m_formatter.executableCopy(allocator);
1627 static void setPointer(void* where, void* value)
1629 reinterpret_cast<void**>(where)[-1] = value;
1632 static void setInt32(void* where, int32_t value)
1634 reinterpret_cast<int32_t*>(where)[-1] = value;
1637 static void setRel32(void* from, void* to)
1639 intptr_t offset = reinterpret_cast<intptr_t>(to) - reinterpret_cast<intptr_t>(from);
1640 ASSERT(offset == static_cast<int32_t>(offset));
1642 setInt32(from, offset);
1645 class X86InstructionFormatter {
1647 static const int maxInstructionSize = 16;
1651 // Legacy prefix bytes:
1653 // These are emmitted prior to the instruction.
1655 void prefix(OneByteOpcodeID pre)
1657 m_buffer.putByte(pre);
1660 // Word-sized operands / no operand instruction formatters.
1662 // In addition to the opcode, the following operand permutations are supported:
1663 // * None - instruction takes no operands.
1664 // * One register - the low three bits of the RegisterID are added into the opcode.
1665 // * Two registers - encode a register form ModRm (for all ModRm formats, the reg field is passed first, and a GroupOpcodeID may be passed in its place).
1666 // * Three argument ModRM - a register, and a register and an offset describing a memory operand.
1667 // * Five argument ModRM - a register, and a base register, an index, scale, and offset describing a memory operand.
1669 // For 32-bit x86 targets, the address operand may also be provided as a void*.
1670 // On 64-bit targets REX prefixes will be planted as necessary, where high numbered registers are used.
1672 // The twoByteOp methods plant two-byte Intel instructions sequences (first opcode byte 0x0F).
1674 void oneByteOp(OneByteOpcodeID opcode)
1676 m_buffer.ensureSpace(maxInstructionSize);
1677 m_buffer.putByteUnchecked(opcode);
1680 void oneByteOp(OneByteOpcodeID opcode, RegisterID reg)
1682 m_buffer.ensureSpace(maxInstructionSize);
1683 emitRexIfNeeded(0, 0, reg);
1684 m_buffer.putByteUnchecked(opcode + (reg & 7));
1687 void oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID rm)
1689 m_buffer.ensureSpace(maxInstructionSize);
1690 emitRexIfNeeded(reg, 0, rm);
1691 m_buffer.putByteUnchecked(opcode);
1692 registerModRM(reg, rm);
1695 void oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
1697 m_buffer.ensureSpace(maxInstructionSize);
1698 emitRexIfNeeded(reg, 0, base);
1699 m_buffer.putByteUnchecked(opcode);
1700 memoryModRM(reg, base, offset);
1703 void oneByteOp_disp32(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
1705 m_buffer.ensureSpace(maxInstructionSize);
1706 emitRexIfNeeded(reg, 0, base);
1707 m_buffer.putByteUnchecked(opcode);
1708 memoryModRM_disp32(reg, base, offset);
1711 void oneByteOp(OneByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
1713 m_buffer.ensureSpace(maxInstructionSize);
1714 emitRexIfNeeded(reg, index, base);
1715 m_buffer.putByteUnchecked(opcode);
1716 memoryModRM(reg, base, index, scale, offset);
1720 void oneByteOp(OneByteOpcodeID opcode, int reg, void* address)
1722 m_buffer.ensureSpace(maxInstructionSize);
1723 m_buffer.putByteUnchecked(opcode);
1724 memoryModRM(reg, address);
1728 void twoByteOp(TwoByteOpcodeID opcode)
1730 m_buffer.ensureSpace(maxInstructionSize);
1731 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1732 m_buffer.putByteUnchecked(opcode);
1735 void twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID rm)
1737 m_buffer.ensureSpace(maxInstructionSize);
1738 emitRexIfNeeded(reg, 0, rm);
1739 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1740 m_buffer.putByteUnchecked(opcode);
1741 registerModRM(reg, rm);
1744 void twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID base, int offset)
1746 m_buffer.ensureSpace(maxInstructionSize);
1747 emitRexIfNeeded(reg, 0, base);
1748 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1749 m_buffer.putByteUnchecked(opcode);
1750 memoryModRM(reg, base, offset);
1753 void twoByteOp(TwoByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
1755 m_buffer.ensureSpace(maxInstructionSize);
1756 emitRexIfNeeded(reg, index, base);
1757 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1758 m_buffer.putByteUnchecked(opcode);
1759 memoryModRM(reg, base, index, scale, offset);
1763 void twoByteOp(TwoByteOpcodeID opcode, int reg, const void* address)
1765 m_buffer.ensureSpace(maxInstructionSize);
1766 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1767 m_buffer.putByteUnchecked(opcode);
1768 memoryModRM(reg, address);
1773 // Quad-word-sized operands:
1775 // Used to format 64-bit operantions, planting a REX.w prefix.
1776 // When planting d64 or f64 instructions, not requiring a REX.w prefix,
1777 // the normal (non-'64'-postfixed) formatters should be used.
1779 void oneByteOp64(OneByteOpcodeID opcode)
1781 m_buffer.ensureSpace(maxInstructionSize);
1783 m_buffer.putByteUnchecked(opcode);
1786 void oneByteOp64(OneByteOpcodeID opcode, RegisterID reg)
1788 m_buffer.ensureSpace(maxInstructionSize);
1789 emitRexW(0, 0, reg);
1790 m_buffer.putByteUnchecked(opcode + (reg & 7));
1793 void oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID rm)
1795 m_buffer.ensureSpace(maxInstructionSize);
1796 emitRexW(reg, 0, rm);
1797 m_buffer.putByteUnchecked(opcode);
1798 registerModRM(reg, rm);
1801 void oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
1803 m_buffer.ensureSpace(maxInstructionSize);
1804 emitRexW(reg, 0, base);
1805 m_buffer.putByteUnchecked(opcode);
1806 memoryModRM(reg, base, offset);
1809 void oneByteOp64_disp32(OneByteOpcodeID opcode, int reg, RegisterID base, int offset)
1811 m_buffer.ensureSpace(maxInstructionSize);
1812 emitRexW(reg, 0, base);
1813 m_buffer.putByteUnchecked(opcode);
1814 memoryModRM_disp32(reg, base, offset);
1817 void oneByteOp64(OneByteOpcodeID opcode, int reg, RegisterID base, RegisterID index, int scale, int offset)
1819 m_buffer.ensureSpace(maxInstructionSize);
1820 emitRexW(reg, index, base);
1821 m_buffer.putByteUnchecked(opcode);
1822 memoryModRM(reg, base, index, scale, offset);
1825 void twoByteOp64(TwoByteOpcodeID opcode, int reg, RegisterID rm)
1827 m_buffer.ensureSpace(maxInstructionSize);
1828 emitRexW(reg, 0, rm);
1829 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1830 m_buffer.putByteUnchecked(opcode);
1831 registerModRM(reg, rm);
1837 // These methods format byte operations. Byte operations differ from the normal
1838 // formatters in the circumstances under which they will decide to emit REX prefixes.
1839 // These should be used where any register operand signifies a byte register.
1841 // The disctinction is due to the handling of register numbers in the range 4..7 on
1842 // x86-64. These register numbers may either represent the second byte of the first
1843 // four registers (ah..bh) or the first byte of the second four registers (spl..dil).
1845 // Since ah..bh cannot be used in all permutations of operands (specifically cannot
1846 // be accessed where a REX prefix is present), these are likely best treated as
1847 // deprecated. In order to ensure the correct registers spl..dil are selected a
1848 // REX prefix will be emitted for any byte register operand in the range 4..15.
1850 // These formatters may be used in instructions where a mix of operand sizes, in which
1851 // case an unnecessary REX will be emitted, for example:
1853 // In this case a REX will be planted since edi is 7 (and were this a byte operand
1854 // a REX would be required to specify dil instead of bh). Unneeded REX prefixes will
1855 // be silently ignored by the processor.
1857 // Address operands should still be checked using regRequiresRex(), while byteRegRequiresRex()
1858 // is provided to check byte register operands.
1860 void oneByteOp8(OneByteOpcodeID opcode, GroupOpcodeID groupOp, RegisterID rm)
1862 m_buffer.ensureSpace(maxInstructionSize);
1863 emitRexIf(byteRegRequiresRex(rm), 0, 0, rm);
1864 m_buffer.putByteUnchecked(opcode);
1865 registerModRM(groupOp, rm);
1868 void twoByteOp8(TwoByteOpcodeID opcode, RegisterID reg, RegisterID rm)
1870 m_buffer.ensureSpace(maxInstructionSize);
1871 emitRexIf(byteRegRequiresRex(reg)|byteRegRequiresRex(rm), reg, 0, rm);
1872 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1873 m_buffer.putByteUnchecked(opcode);
1874 registerModRM(reg, rm);
1877 void twoByteOp8(TwoByteOpcodeID opcode, GroupOpcodeID groupOp, RegisterID rm)
1879 m_buffer.ensureSpace(maxInstructionSize);
1880 emitRexIf(byteRegRequiresRex(rm), 0, 0, rm);
1881 m_buffer.putByteUnchecked(OP_2BYTE_ESCAPE);
1882 m_buffer.putByteUnchecked(opcode);
1883 registerModRM(groupOp, rm);
1888 // An immedaite should be appended where appropriate after an op has been emitted.
1889 // The writes are unchecked since the opcode formatters above will have ensured space.
1891 void immediate8(int imm)
1893 m_buffer.putByteUnchecked(imm);
1896 void immediate16(int imm)
1898 m_buffer.putShortUnchecked(imm);
1901 void immediate32(int imm)
1903 m_buffer.putIntUnchecked(imm);
1906 void immediate64(int64_t imm)
1908 m_buffer.putInt64Unchecked(imm);
1911 JmpSrc immediateRel32()
1913 m_buffer.putIntUnchecked(0);
1914 return JmpSrc(m_buffer.size());
1917 // Administrative methods:
1919 size_t size() const { return m_buffer.size(); }
1920 bool isAligned(int alignment) const { return m_buffer.isAligned(alignment); }
1921 void* data() const { return m_buffer.data(); }
1922 void* executableCopy(ExecutablePool* allocator) { return m_buffer.executableCopy(allocator); }
1926 // Internals; ModRm and REX formatters.
1928 static const RegisterID noBase = X86Registers::ebp;
1929 static const RegisterID hasSib = X86Registers::esp;
1930 static const RegisterID noIndex = X86Registers::esp;
1932 static const RegisterID noBase2 = X86Registers::r13;
1933 static const RegisterID hasSib2 = X86Registers::r12;
1935 // Registers r8 & above require a REX prefixe.
1936 inline bool regRequiresRex(int reg)
1938 return (reg >= X86Registers::r8);
1941 // Byte operand register spl & above require a REX prefix (to prevent the 'H' registers be accessed).
1942 inline bool byteRegRequiresRex(int reg)
1944 return (reg >= X86Registers::esp);
1947 // Format a REX prefix byte.
1948 inline void emitRex(bool w, int r, int x, int b)
1950 m_buffer.putByteUnchecked(PRE_REX | ((int)w << 3) | ((r>>3)<<2) | ((x>>3)<<1) | (b>>3));
1953 // Used to plant a REX byte with REX.w set (for 64-bit operations).
1954 inline void emitRexW(int r, int x, int b)
1956 emitRex(true, r, x, b);
1959 // Used for operations with byte operands - use byteRegRequiresRex() to check register operands,
1960 // regRequiresRex() to check other registers (i.e. address base & index).
1961 inline void emitRexIf(bool condition, int r, int x, int b)
1963 if (condition) emitRex(false, r, x, b);
1966 // Used for word sized operations, will plant a REX prefix if necessary (if any register is r8 or above).
1967 inline void emitRexIfNeeded(int r, int x, int b)
1969 emitRexIf(regRequiresRex(r) || regRequiresRex(x) || regRequiresRex(b), r, x, b);
1972 // No REX prefix bytes on 32-bit x86.
1973 inline bool regRequiresRex(int) { return false; }
1974 inline bool byteRegRequiresRex(int) { return false; }
1975 inline void emitRexIf(bool, int, int, int) {}
1976 inline void emitRexIfNeeded(int, int, int) {}
1986 void putModRm(ModRmMode mode, int reg, RegisterID rm)
1988 m_buffer.putByteUnchecked((mode << 6) | ((reg & 7) << 3) | (rm & 7));
1991 void putModRmSib(ModRmMode mode, int reg, RegisterID base, RegisterID index, int scale)
1993 ASSERT(mode != ModRmRegister);
1995 putModRm(mode, reg, hasSib);
1996 m_buffer.putByteUnchecked((scale << 6) | ((index & 7) << 3) | (base & 7));
1999 void registerModRM(int reg, RegisterID rm)
2001 putModRm(ModRmRegister, reg, rm);
2004 void memoryModRM(int reg, RegisterID base, int offset)
2006 // A base of esp or r12 would be interpreted as a sib, so force a sib with no index & put the base in there.
2008 if ((base == hasSib) || (base == hasSib2)) {
2010 if (base == hasSib) {
2012 if (!offset) // No need to check if the base is noBase, since we know it is hasSib!
2013 putModRmSib(ModRmMemoryNoDisp, reg, base, noIndex, 0);
2014 else if (CAN_SIGN_EXTEND_8_32(offset)) {
2015 putModRmSib(ModRmMemoryDisp8, reg, base, noIndex, 0);
2016 m_buffer.putByteUnchecked(offset);
2018 putModRmSib(ModRmMemoryDisp32, reg, base, noIndex, 0);
2019 m_buffer.putIntUnchecked(offset);
2023 if (!offset && (base != noBase) && (base != noBase2))
2025 if (!offset && (base != noBase))
2027 putModRm(ModRmMemoryNoDisp, reg, base);
2028 else if (CAN_SIGN_EXTEND_8_32(offset)) {
2029 putModRm(ModRmMemoryDisp8, reg, base);
2030 m_buffer.putByteUnchecked(offset);
2032 putModRm(ModRmMemoryDisp32, reg, base);
2033 m_buffer.putIntUnchecked(offset);
2038 void memoryModRM_disp32(int reg, RegisterID base, int offset)
2040 // A base of esp or r12 would be interpreted as a sib, so force a sib with no index & put the base in there.
2042 if ((base == hasSib) || (base == hasSib2)) {
2044 if (base == hasSib) {
2046 putModRmSib(ModRmMemoryDisp32, reg, base, noIndex, 0);
2047 m_buffer.putIntUnchecked(offset);
2049 putModRm(ModRmMemoryDisp32, reg, base);
2050 m_buffer.putIntUnchecked(offset);
2054 void memoryModRM(int reg, RegisterID base, RegisterID index, int scale, int offset)
2056 ASSERT(index != noIndex);
2059 if (!offset && (base != noBase) && (base != noBase2))
2061 if (!offset && (base != noBase))
2063 putModRmSib(ModRmMemoryNoDisp, reg, base, index, scale);
2064 else if (CAN_SIGN_EXTEND_8_32(offset)) {
2065 putModRmSib(ModRmMemoryDisp8, reg, base, index, scale);
2066 m_buffer.putByteUnchecked(offset);
2068 putModRmSib(ModRmMemoryDisp32, reg, base, index, scale);
2069 m_buffer.putIntUnchecked(offset);
2074 void memoryModRM(int reg, const void* address)
2076 // noBase + ModRmMemoryNoDisp means noBase + ModRmMemoryDisp32!
2077 putModRm(ModRmMemoryNoDisp, reg, noBase);
2078 m_buffer.putIntUnchecked(reinterpret_cast<int32_t>(address));
2082 AssemblerBuffer m_buffer;
2088 #endif // ENABLE(ASSEMBLER) && CPU(X86)
2090 #endif // X86Assembler_h