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Change-Id: Ic2b1f4775d24a1cf729a0dde1c8d2e1d6a85ef95
[oca1/test.git]
/
VGADisplay
/
Verilog
/
tb.v
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`timescale 1ns / 1ps
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//synthesis translate_off
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module tb ;
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parameter tCYC=2 ;
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parameter tPD=(tCYC/10) ;
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integer i ;
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reg p_reset, m_clock ;
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reg [13:0] iRadrs ;
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wire [15:0] oRdata ;
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reg fiRd_req ;
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wire foRd_ack ;
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reg [7:0] iWdata ;
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reg [13:0] iWadrs ;
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reg fiWr_req ;
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exp_ctrl uut(
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.p_reset(p_reset),
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.m_clock(m_clock),
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.iRadrs(iRadrs),
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.oRdata(oRdata),
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.fiRd_req(fiRd_req),
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.foRd_ack(foRd_ack),
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.iWdata(iWdata),
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.iWadrs(iWadrs),
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.fiWr_req(fiWr_req)
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) ;
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initial forever #(tCYC/2) m_clock = ~m_clock ;
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initial begin
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#(tPD)
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p_reset = 1 ;
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m_clock = 0 ;
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// Initialize
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iRadrs <= 14'd0 ;
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fiRd_req <= 0 ;
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iWdata <= 8'd0 ;
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iWadrs <= 14'd0 ;
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fiWr_req <= 0 ;
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#(tCYC)
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p_reset = 0 ;
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#(tCYC*5) ;
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for(i=0; i<1000; i=i+1) begin
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fiWr_req <= 1 ;
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iWdata <= i[7:0] ;
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iWadrs <= i[13:0] ;
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#(tCYC) ;
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fiWr_req <= 0 ;
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#(tCYC) ;
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end
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#(tCYC*5) ;
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for(i=0; i<100; i=i+1) begin
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fiRd_req <= 1 ;
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iRadrs <= i[13:0] ;
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#(tCYC) ;
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fiRd_req <= 0 ;
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#(tCYC*2) ;
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end
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end
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endmodule
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//synthesis translate_on