VGADisplay/Verilog/tb.v

   1 `timescale      1ns / 1ps
   2
   3 //synthesis translate_off
   4 module tb ;
   5         parameter tCYC=2 ;
   6         parameter tPD=(tCYC/10) ;
   7
   8         integer i ;
   9
  10         reg  p_reset, m_clock ;
  11         reg  [13:0] iRadrs ;
  12         wire [15:0] oRdata ;
  13         reg             fiRd_req ;
  14         wire            foRd_ack ;
  15
  16         reg  [7:0]      iWdata ;
  17         reg  [13:0] iWadrs ;
  18         reg             fiWr_req ;
  19
  20         exp_ctrl uut(
  21                 .p_reset(p_reset),
  22                 .m_clock(m_clock),
  23                 .iRadrs(iRadrs),
  24                 .oRdata(oRdata),
  25                 .fiRd_req(fiRd_req),
  26                 .foRd_ack(foRd_ack),
  27                 .iWdata(iWdata),
  28                 .iWadrs(iWadrs),
  29                 .fiWr_req(fiWr_req)
  30         ) ;
  31
  32         initial forever #(tCYC/2) m_clock = ~m_clock ;
  33
  34         initial begin
  35                 #(tPD)
  36                         p_reset = 1 ;
  37                         m_clock = 0 ;
  38                         // Initialize
  39                         iRadrs   <= 14'd0 ;
  40                         fiRd_req <= 0 ;
  41                         iWdata   <= 8'd0 ;
  42                         iWadrs   <= 14'd0 ;
  43                         fiWr_req <= 0 ;
  44                 #(tCYC)
  45                         p_reset = 0 ;
  46                 #(tCYC*5) ;
  47                         for(i=0; i<1000; i=i+1) begin
  48                                 fiWr_req <= 1 ;
  49                                 iWdata <= i[7:0] ;
  50                                 iWadrs <= i[13:0] ;
  51                         #(tCYC) ;
  52                                 fiWr_req <= 0 ;
  53                         #(tCYC) ;
  54                         end
  55                 #(tCYC*5) ;
  56                         for(i=0; i<100; i=i+1) begin
  57                                 fiRd_req <= 1 ;
  58                                 iRadrs <= i[13:0] ;
  59                         #(tCYC) ;
  60                                 fiRd_req <= 0 ;
  61                         #(tCYC*2) ;
  62                         end
  63         end
  64
  65 endmodule
  66
  67 //synthesis translate_on