2 Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 12:10:33 2011
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3 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:
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6 module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , q );
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7 input p_reset, m_clock;
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10 input [13:0] rdaddress;
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11 input [13:0] wraddress;
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14 reg [7:0] m_vram [0:16383];
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15 reg [7:0] r_ram_data;
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17 assign q = r_ram_data;
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18 always @(posedge m_clock)
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21 m_vram[wraddress] <= data;
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23 always @(posedge m_clock or posedge p_reset)
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26 r_ram_data <= 8'b00000000;
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27 else r_ram_data <= m_vram[rdaddress];
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31 Produced by NSL Core(version=20110302), IP ARCH, Inc. Fri Jul 08 12:10:34 2011
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32 Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp
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