VGADisplay/src/vga_gen.nsl

   1 /**
   2 *       Video Graphic Array\81@Signal Generate Circuit
   3 *       Module name is "vga_generate"
   4 *       @auther Yujiro Kaneko
   5 *       @version 1.2
   6 **/
   7
   8 #include "vga_ram.nsh"  // vga ram module
   9
  10 #define H_ACT_MAX        10'd640
  11 #define H_FRONTP_MAX 10'd655
  12 #define H_SYNC_MAX       10'd751
  13 #define H_BACKP_MAX      10'd799
  14
  15 #define V_ACT_MAX        10'd480
  16 #define V_FRONTP_MAX 10'd489
  17 #define V_SYNC_MAX       10'd491
  18 #define V_BACKP_MAX      10'd519
  19
  20 #define VCNT_1SEC       26'd25000000
  21
  22 declare vga_gen interface {
  23         input  i_clk50 ;                // 50MHz main clock
  24         input  i_fifo_rst ;             // FIFO rst
  25         input  m_clock ;
  26         input  p_reset ;
  27         output o_vsync ;                // Vertical Sync
  28         output o_hsync ;                // Horizontal Hync
  29         output o_vga_r[4] ;             // VGA RED
  30         output o_vga_g[4] ;             // VGA GREEN
  31         output o_vga_b[4] ;             // VGA BLUE
  32         output o_dummy_rgb[3] ; // VGA dummy signal
  33         output o_vcnt[10] ;             // V sync Count
  34
  35         /* FIFO write terminal */
  36         input  i_wrdata[8] ;
  37         func_in fi_fifo_write( i_wrdata ) ;
  38
  39         /* FIFO terminal */
  40         output o_rdack ;
  41
  42         output o_led ;
  43 }
  44
  45 module vga_gen {
  46         func_self fs_fifo_read() ;      // FIFO read terminal
  47         wire w_rddata[8] ;                      // FIFO read wire
  48         func_self fs_fifo_ack(w_rddata) ;
  49         func_self fs_initialize() ;
  50
  51         reg r_data1[8] = 0 ;
  52         reg r_data2[8] = 0 ;
  53         reg r_reg_cnt = 0 ;
  54         reg r_bit_cnt[3] = 0 ;
  55
  56         reg r_vsync = 0 ;
  57         reg r_hsync = 0 ;
  58         reg r_vcnt[10] = 0 ;
  59         reg r_hcnt[10] = 0 ;
  60         reg r_cnt[26] = 0 ;
  61         reg r_outcnt[3] = 0 ;
  62         reg r_outclr[7] = 0 ;
  63         reg r_vcnt_hld = 0 ;
  64
  65         reg r_led = 0 ;
  66         reg r_init_flg = 0 ;
  67         reg r_trg[3] = 0 ;
  68         reg r_cnt1[26] = 0, r_cnt2[26] = 0, r_cnt3[26] = 0 ;
  69         reg r_buff1 = 0 ;
  70
  71         vga_ram u_FIFO ;
  72
  73         {
  74                 r_trg := { r_trg[1:0], 0b1 } ;
  75                 if(r_trg == 0b011) fs_initialize() ;
  76
  77                 /* VGA Generate Node */
  78                 o_vsync = r_vsync ;
  79                 o_hsync = r_hsync ;
  80                 o_vcnt  = r_vcnt ;
  81
  82                 /* FIFO assign */
  83                 u_FIFO.i_clk50  = i_clk50 ;
  84                 u_FIFO.i_clk25  = m_clock ;
  85                 o_rdack                 = u_FIFO.o_rdack ;
  86                 u_FIFO.i_we             = fi_fifo_write ;
  87                 u_FIFO.i_wrdata = i_wrdata ;
  88                 u_FIFO.i_rst    = i_fifo_rst ;
  89                 u_FIFO.i_re             = fs_fifo_read ;
  90
  91                 /* TEST LED cnt routine */
  92                 o_led = r_led ;
  93
  94                 any {
  95                         r_cnt == VCNT_1SEC : {
  96                                 r_cnt := 0 ;
  97                                 r_led := ~r_led ;
  98                         }
  99                         else : {
 100                                 r_cnt++ ;
 101                         }
 102                 }
 103
 104                 /* VSync & HSync\81@\90¶\90¬\83\8b\81[\83`\83\93 */
 105                 if(r_init_flg) {
 106                         if( r_hcnt < H_BACKP_MAX ) {
 107                                 r_hcnt++ ;
 108                         } else {
 109                                 r_hcnt := 0 ;
 110                                         if( r_vcnt < V_BACKP_MAX ) {
 111                                         r_vcnt++ ;
 112                                 } else {
 113                                         r_vcnt := 0 ;
 114                                 }
 115                         }
 116                 }
 117
 118                 // HACTMAX640 VACTMAX480 \83J\83\89\81[\95`\89æ\83G\83\8a\83A
 119                 if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) && r_vsync ) {
 120
 121                         // \83f\81[\83^\83o\83b\83t\83@\89^\97p\83J\83E\83\93\83^\81i\83e\83X\83g\97p\81j
 122                         if( r_init_flg ) {
 123
 124                                 r_bit_cnt++ ;   // \83r\83b\83g\83J\83E\83\93\83g\83A\83b\83v
 125
 126                                 // \83\8c\83W\83X\83^\83J\83E\83\93\83g\94½\93]
 127                                 if(r_bit_cnt==0b111) {
 128                                         r_reg_cnt := ~r_reg_cnt ;
 129                                         fs_fifo_read() ;
 130                                 }
 131
 132                                 // FIFO\93Ç\82Ý\8fo\82µ\92l\83o\83b\83t\83@\83\8a\83\93\83O
 133                                 if( fs_fifo_ack ) {
 134                                         any {
 135                                                 ~r_reg_cnt : r_data2 := w_rddata ;
 136                                                 r_reg_cnt  : r_data1 := w_rddata ;
 137                                         }
 138                                 }
 139
 140                                 any {
 141                                         r_reg_cnt == 0b0 : o_dummy_rgb = 3#(r_data1[r_bit_cnt]) ;
 142                                         // (r_reg_cnt == 0b1)
 143                                         else                     : o_dummy_rgb = 3#(r_data2[r_bit_cnt]) ;
 144                                 }
 145                         }
 146
 147
 148                         /* \83J\83\89\81[\83o\81[\8dì\90¬ */
 149                         if( r_outcnt < 3'd4 ) {
 150                                 r_outcnt++ ;
 151                         } else {
 152                                 r_outcnt := 0 ;
 153                                 r_outclr++ ;
 154                         }
 155
 156                         if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ;
 157                         else o_vga_b = 0 ;
 158                         if( ~r_outclr[5]) o_vga_r = ~r_outclr[3:0] ;
 159                         else o_vga_r = 0 ;
 160                         if( ~r_outclr[6]) o_vga_g = ~r_outclr[3:0] ;
 161                         else o_vga_g = 0 ;
 162
 163                 } else {
 164                         // \83J\83\89\81[\95`\89æ\82µ\82È\82¢\83G\83\8a\83A
 165                         any {
 166                                 r_hcnt == H_ACT_MAX : {
 167                                         o_vga_r = 0 ;
 168                                         o_vga_g = 0 ;
 169                                         o_vga_b = 0 ;
 170                                         r_outcnt := 0 ;
 171                                         r_outclr := 0 ;
 172                                         o_dummy_rgb = 0 ;
 173                                 }
 174                                 r_hcnt == H_FRONTP_MAX : {
 175                                         r_hsync := 0 ;
 176                                 }
 177                                 r_hcnt == H_SYNC_MAX : {
 178                                         r_hsync := 1 ;
 179                                 }
 180                         }
 181
 182                         // FIFO\93Ç\82Ý\8fo\82µ\92l\83o\83b\83t\83@\83\8a\83\93\83O
 183                         if( fs_fifo_ack ) {
 184                                 any {
 185                                         ~r_reg_cnt      : r_data2 := w_rddata ;
 186                                         r_reg_cnt       : r_data1 := w_rddata ;
 187                                 }
 188                         }
 189                 }
 190
 191                 any {
 192                         r_vcnt == V_ACT_MAX     :  ;
 193                         r_vcnt == V_FRONTP_MAX  : r_vsync := 0 ;
 194                         r_vcnt == V_SYNC_MAX    : r_vsync := 1 ;
 195                 }
 196         }       // public end ;
 197
 198         // VGA Gen initialize command
 199         func fs_initialize seq {
 200                 // \83f\81[\83^\83o\83b\83t\83@\82P\81C\82Q\82ÉFIFO\82Ì\92l\82ð\8ai\94[
 201 //              fs_fifo_read() ;
 202                 r_data1 := u_FIFO.o_rddata ;
 203                 fs_fifo_read() ;
 204                 r_data2 := u_FIFO.o_rddata ;
 205                 r_init_flg := 1 ;
 206         }
 207
 208         // FIFO read command
 209         func fs_fifo_read seq {
 210                 ;
 211                 fs_fifo_ack( u_FIFO.o_rddata ) ;
 212         }
 213 }
 214 //module end