VGADisplay/src/vga_gen.nsl

   1 /**
   2 *       VGA\81@Signal Generate Circuit
   3 *       Module name is "vga_generate"
   4 *       @auther Yujiro Kaneko
   5 *       @version 1.2
   6 */
   7
   8 #include "vga_ram.nsh"  // vga ram module
   9
  10 #define H_ACT_MAX        10'd640
  11 #define H_FRONTP_MAX 10'd656
  12 #define H_SYNC_MAX       10'd752
  13 #define H_BACKP_MAX      10'd800
  14
  15 #define V_ACT_MAX        10'd480
  16 #define V_FRONTP_MAX 10'd490
  17 #define V_SYNC_MAX       10'd492
  18 #define V_BACKP_MAX      10'd521
  19
  20 #define VCNT_1SEC       26'd25000000
  21
  22 declare vga_gen interface {
  23         input  i_clk50M ;               // 50MHz main clock
  24         input  m_clock ;
  25         input  p_reset ;
  26         output o_vsync ;
  27         output o_hsync ;
  28         output o_vga_r[4] ;
  29         output o_vga_g[4] ;
  30         output o_vga_b[4] ;
  31
  32         input  i_wrdata1[8] ;
  33         input  i_wrdata2[8] ;
  34         input  i_wradrs1[8] ;
  35         input  i_wradrs2[8] ;
  36
  37         func_in fi_fifo1_write( i_wradrs1, i_wrdata1 ) ;
  38         func_in fi_fifo2_write( i_wradrs2, i_wrdata2 ) ;
  39
  40         output outled ;
  41         output o_vcnt[10] ;
  42 }
  43 module vga_gen {
  44         func_self fs_fifo1_read() ;
  45         func_self fs_fifo2_read() ;
  46
  47         func_self fs_fifo1_exec() ;
  48         func_self fs_fifo2_exec() ;
  49
  50         func_self fs_fifo1_reset() ;
  51         func_self fs_fifo2_reset() ;
  52
  53         reg r_bit_number[5] = 0 ;
  54
  55         reg r_vsync = 0 ;
  56         reg r_hsync = 0 ;
  57         reg r_vcnt[10] = 0 ;
  58         reg r_hcnt[10] = 0 ;
  59         reg cnt[26] = 0 ;
  60         reg testled = 0 ;
  61         reg r_outcnt[3] = 0 ;
  62         reg r_outclr[7] = 0 ;
  63         reg r_vcnt_hld = 0 ;
  64
  65         wire w_rddata1[24] ;
  66         wire w_rddata2[24] ;
  67
  68         reg r_rdadrs1[8] = 0 ;
  69         reg r_rdadrs2[8] = 0 ;
  70
  71         vga_ram u_FIFO ;
  72
  73         {
  74                 /* FIFO assign */
  75                 u_FIFO.i_clock          = i_clk50M ;
  76                 u_FIFO.m_clock      = m_clock ;
  77
  78                 u_FIFO.i_we1            = fi_fifo1_write ;
  79                 u_FIFO.i_we2            = fi_fifo2_write ;
  80                 u_FIFO.i_wrdata1        = i_wrdata1 ;
  81                 u_FIFO.i_wrdata2        = i_wrdata2 ;
  82                 u_FIFO.i_wradrs1        = i_wradrs1 ;
  83                 u_FIFO.i_wradrs2        = i_wradrs2 ;
  84                 u_FIFO.i_re1            = fs_fifo1_read ;
  85                 u_FIFO.i_re2            = fs_fifo2_read ;
  86                 w_rddata1                       = u_FIFO.o_rddata1 ;
  87                 w_rddata2                       = u_FIFO.o_rddata2 ;
  88                 u_FIFO.i_rdadrs1        = r_rdadrs1 ;
  89                 u_FIFO.i_rdadrs2        = r_rdadrs2 ;
  90                 o_vcnt                          = r_vcnt ;
  91
  92                 r_vcnt_hld                      := r_vcnt[0] ;
  93
  94                 /* LED test */
  95                 outled = testled ;
  96                 o_vsync = r_vsync ;
  97                 o_hsync = r_hsync ;
  98
  99                 any {
 100                         ~r_vcnt_hld &  r_vcnt[0] : {
 101                                 fs_fifo1_reset() ;
 102                         }
 103                          r_vcnt_hld & ~r_vcnt[0] : {
 104                                 fs_fifo2_reset() ;
 105                         }
 106                 }
 107
 108                 /* test led count routine */
 109                 any {
 110                         cnt == VCNT_1SEC : {
 111                                 cnt := 0 ;
 112                                 testled := ~testled ;
 113                         }
 114                         else : {
 115                                 cnt++ ;
 116                         }
 117                 }
 118
 119                 /* vsync hsync generate routine */
 120                 if( r_hcnt < H_BACKP_MAX ) {
 121                         r_hcnt++ ;
 122                 } else {
 123                         r_hcnt := 0 ;
 124                         if( r_vcnt < V_BACKP_MAX ) {
 125                                 r_vcnt++ ;
 126                         } else {
 127                                 r_vcnt := 0 ;
 128                         }
 129                 }
 130
 131                 // HACTMAX640 VACTMAX480
 132                 if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
 133
 134                         any {
 135                                 ~r_vcnt[0] : fs_fifo1_exec() ;
 136                                  r_vcnt[0] : fs_fifo2_exec() ;
 137                         }
 138
 139                         any {
 140                                 r_bit_number == 5'd23 : {
 141                                         r_bit_number := 0 ;
 142                                         any {
 143                                                 ~r_vcnt[0] : fs_fifo1_read() ;
 144                                                 r_vcnt[0]  : fs_fifo2_read() ;
 145                                         }
 146                                 }
 147                                 else : {
 148                                         r_bit_number++ ;
 149                                 }
 150                         }
 151
 152                         /* \83J\83\89\81[\83o\81[\8dì\90¬ */
 153 /*
 154                         if( r_outcnt < 3'd4 ) {
 155                                 r_outcnt++ ;
 156                         } else {
 157                                 r_outcnt := 0 ;
 158                                 r_outclr++ ;
 159                         }
 160
 161                         if( ~r_outclr[4]) o_vga_b = ~r_outclr[3:0] ;
 162                         else o_vga_b = 0 ;
 163
 164                         if( ~r_outclr[5]) o_vga_r = ~r_outclr[3:0] ;
 165                         else o_vga_r = 0 ;
 166
 167                         if( ~r_outclr[6]) o_vga_g = ~r_outclr[3:0] ;
 168                         else o_vga_g = 0 ;
 169 */
 170                 } else {
 171                         any {
 172                                 r_hcnt == H_ACT_MAX : {
 173                                         /* VGA\81@null\81@ */
 174                                         o_vga_r = 0 ;
 175                                         o_vga_g = 0 ;
 176                                         o_vga_b = 0 ;
 177                                         r_outcnt := 0 ;
 178                                         r_outclr := 0 ;
 179                                         r_bit_number := 0 ;
 180                                 }
 181                                 r_hcnt == H_FRONTP_MAX : {
 182                                         r_hsync := 0 ;
 183                                 }
 184                                 r_hcnt == H_SYNC_MAX : {
 185                                         r_hsync := 1 ;
 186                                 }
 187                         }
 188                 }
 189
 190                 any {
 191                         r_vcnt == V_ACT_MAX : {
 192                                 ;
 193                         }
 194                         r_vcnt == V_FRONTP_MAX : {
 195                                 r_vsync := 0 ;
 196                         }
 197                         r_vcnt == V_SYNC_MAX : {
 198                                 r_vsync := 1 ;
 199                         }
 200                 }
 201         }
 202
 203         func fs_fifo1_exec {
 204                 if(w_rddata1[r_bit_number]){
 205                         o_vga_r = 4'b1111 ;
 206                         o_vga_g = 4'b1111 ;
 207                         o_vga_b = 4'b1111 ;
 208                 } else {
 209                         o_vga_r = 4'b0000 ;
 210                         o_vga_g = 4'b0000 ;
 211                         o_vga_b = 4'b0000 ;
 212                 }
 213         }
 214
 215         func fs_fifo2_exec {
 216                 if(w_rddata2[r_bit_number]){
 217                         o_vga_r = 4'b1111 ;
 218                         o_vga_g = 4'b1111 ;
 219                         o_vga_b = 4'b1111 ;
 220                 } else {
 221                         o_vga_r = 4'b0000 ;
 222                         o_vga_g = 4'b0000 ;
 223                         o_vga_b = 4'b0000 ;
 224
 225                 }
 226         }
 227
 228         func fs_fifo1_read {
 229                 r_rdadrs1 := r_rdadrs1 + 8'd3 ;
 230         }
 231
 232         func fs_fifo2_read {
 233                 r_rdadrs2 := r_rdadrs2 + 8'd3 ;
 234         }
 235
 236         func fs_fifo1_reset {
 237                 r_rdadrs1 := 8'd0 ;
 238         }
 239
 240         func fs_fifo2_reset {
 241                 r_rdadrs2 := 8'd0 ;
 242         }
 243 } //module end