2 * emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qapi/error.h"
23 #include "qapi/type-helpers.h"
24 #include "hw/core/tcg-cpu-ops.h"
26 #include "disas/disas.h"
27 #include "exec/exec-all.h"
29 #include "qemu/atomic.h"
32 #include "qemu/main-loop.h"
33 #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
34 #include "hw/i386/apic.h"
36 #include "sysemu/cpus.h"
37 #include "exec/cpu-all.h"
38 #include "sysemu/cpu-timers.h"
39 #include "exec/replay-core.h"
40 #include "sysemu/tcg.h"
41 #include "exec/helper-proto.h"
42 #include "tb-jmp-cache.h"
44 #include "tb-context.h"
47 /* -icount align implementation. */
49 typedef struct SyncClocks {
51 int64_t last_cpu_icount;
52 int64_t realtime_clock;
55 #if !defined(CONFIG_USER_ONLY)
56 /* Allow the guest to have a max 3ms advance.
57 * The difference between the 2 clocks could therefore
60 #define VM_CLOCK_ADVANCE 3000000
61 #define THRESHOLD_REDUCE 1.5
62 #define MAX_DELAY_PRINT_RATE 2000000000LL
63 #define MAX_NB_PRINTS 100
68 static void align_clocks(SyncClocks *sc, CPUState *cpu)
72 if (!icount_align_option) {
76 cpu_icount = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
77 sc->diff_clk += icount_to_ns(sc->last_cpu_icount - cpu_icount);
78 sc->last_cpu_icount = cpu_icount;
80 if (sc->diff_clk > VM_CLOCK_ADVANCE) {
82 struct timespec sleep_delay, rem_delay;
83 sleep_delay.tv_sec = sc->diff_clk / 1000000000LL;
84 sleep_delay.tv_nsec = sc->diff_clk % 1000000000LL;
85 if (nanosleep(&sleep_delay, &rem_delay) < 0) {
86 sc->diff_clk = rem_delay.tv_sec * 1000000000LL + rem_delay.tv_nsec;
91 Sleep(sc->diff_clk / SCALE_MS);
97 static void print_delay(const SyncClocks *sc)
99 static float threshold_delay;
100 static int64_t last_realtime_clock;
101 static int nb_prints;
103 if (icount_align_option &&
104 sc->realtime_clock - last_realtime_clock >= MAX_DELAY_PRINT_RATE &&
105 nb_prints < MAX_NB_PRINTS) {
106 if ((-sc->diff_clk / (float)1000000000LL > threshold_delay) ||
107 (-sc->diff_clk / (float)1000000000LL <
108 (threshold_delay - THRESHOLD_REDUCE))) {
109 threshold_delay = (-sc->diff_clk / 1000000000LL) + 1;
110 qemu_printf("Warning: The guest is now late by %.1f to %.1f seconds\n",
114 last_realtime_clock = sc->realtime_clock;
119 static void init_delay_params(SyncClocks *sc, CPUState *cpu)
121 if (!icount_align_option) {
124 sc->realtime_clock = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL_RT);
125 sc->diff_clk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - sc->realtime_clock;
127 = cpu->icount_extra + cpu_neg(cpu)->icount_decr.u16.low;
128 if (sc->diff_clk < max_delay) {
129 max_delay = sc->diff_clk;
131 if (sc->diff_clk > max_advance) {
132 max_advance = sc->diff_clk;
135 /* Print every 2s max if the guest is late. We limit the number
136 of printed messages to NB_PRINT_MAX(currently 100) */
140 static void align_clocks(SyncClocks *sc, const CPUState *cpu)
144 static void init_delay_params(SyncClocks *sc, const CPUState *cpu)
147 #endif /* CONFIG USER ONLY */
149 uint32_t curr_cflags(CPUState *cpu)
151 uint32_t cflags = cpu->tcg_cflags;
154 * Record gdb single-step. We should be exiting the TB by raising
155 * EXCP_DEBUG, but to simplify other tests, disable chaining too.
157 * For singlestep and -d nochain, suppress goto_tb so that
158 * we can log -d cpu,exec after every TB.
160 if (unlikely(cpu->singlestep_enabled)) {
161 cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | CF_SINGLE_STEP | 1;
162 } else if (qatomic_read(&one_insn_per_tb)) {
163 cflags |= CF_NO_GOTO_TB | 1;
164 } else if (qemu_loglevel_mask(CPU_LOG_TB_NOCHAIN)) {
165 cflags |= CF_NO_GOTO_TB;
173 target_ulong cs_base;
175 tb_page_addr_t page_addr0;
180 static bool tb_lookup_cmp(const void *p, const void *d)
182 const TranslationBlock *tb = p;
183 const struct tb_desc *desc = d;
185 if ((tb_cflags(tb) & CF_PCREL || tb->pc == desc->pc) &&
186 tb_page_addr0(tb) == desc->page_addr0 &&
187 tb->cs_base == desc->cs_base &&
188 tb->flags == desc->flags &&
189 tb_cflags(tb) == desc->cflags) {
190 /* check next page if needed */
191 tb_page_addr_t tb_phys_page1 = tb_page_addr1(tb);
192 if (tb_phys_page1 == -1) {
195 tb_page_addr_t phys_page1;
196 target_ulong virt_page1;
199 * We know that the first page matched, and an otherwise valid TB
200 * encountered an incomplete instruction at the end of that page,
201 * therefore we know that generating a new TB from the current PC
202 * must also require reading from the next page -- even if the
203 * second pages do not match, and therefore the resulting insn
204 * is different for the new TB. Therefore any exception raised
205 * here by the faulting lookup is not premature.
207 virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
208 phys_page1 = get_page_addr_code(desc->env, virt_page1);
209 if (tb_phys_page1 == phys_page1) {
217 static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
218 target_ulong cs_base, uint32_t flags,
221 tb_page_addr_t phys_pc;
225 desc.env = cpu->env_ptr;
226 desc.cs_base = cs_base;
228 desc.cflags = cflags;
230 phys_pc = get_page_addr_code(desc.env, pc);
234 desc.page_addr0 = phys_pc;
235 h = tb_hash_func(phys_pc, (cflags & CF_PCREL ? 0 : pc),
237 return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
240 /* Might cause an exception, so have a longjmp destination ready */
241 static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
242 target_ulong cs_base,
243 uint32_t flags, uint32_t cflags)
245 TranslationBlock *tb;
249 /* we should never be trying to look up an INVALID tb */
250 tcg_debug_assert(!(cflags & CF_INVALID));
252 hash = tb_jmp_cache_hash_func(pc);
253 jc = cpu->tb_jmp_cache;
255 if (cflags & CF_PCREL) {
256 /* Use acquire to ensure current load of pc from jc. */
257 tb = qatomic_load_acquire(&jc->array[hash].tb);
260 jc->array[hash].pc == pc &&
261 tb->cs_base == cs_base &&
262 tb->flags == flags &&
263 tb_cflags(tb) == cflags)) {
266 tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
270 jc->array[hash].pc = pc;
271 /* Ensure pc is written first. */
272 qatomic_store_release(&jc->array[hash].tb, tb);
274 /* Use rcu_read to ensure current load of pc from *tb. */
275 tb = qatomic_rcu_read(&jc->array[hash].tb);
279 tb->cs_base == cs_base &&
280 tb->flags == flags &&
281 tb_cflags(tb) == cflags)) {
284 tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
288 /* Use the pc value already stored in tb->pc. */
289 qatomic_set(&jc->array[hash].tb, tb);
295 static void log_cpu_exec(target_ulong pc, CPUState *cpu,
296 const TranslationBlock *tb)
298 if (qemu_log_in_addr_range(pc)) {
299 qemu_log_mask(CPU_LOG_EXEC,
300 "Trace %d: %p [" TARGET_FMT_lx
301 "/" TARGET_FMT_lx "/%08x/%08x] %s\n",
302 cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
303 tb->flags, tb->cflags, lookup_symbol(pc));
305 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
306 FILE *logfile = qemu_log_trylock();
310 if (qemu_loglevel_mask(CPU_LOG_TB_FPU)) {
311 flags |= CPU_DUMP_FPU;
313 #if defined(TARGET_I386)
314 flags |= CPU_DUMP_CCOP;
316 cpu_dump_state(cpu, logfile, flags);
317 qemu_log_unlock(logfile);
323 static bool check_for_breakpoints_slow(CPUState *cpu, target_ulong pc,
327 bool match_page = false;
330 * Singlestep overrides breakpoints.
331 * This requirement is visible in the record-replay tests, where
332 * we would fail to make forward progress in reverse-continue.
334 * TODO: gdb singlestep should only override gdb breakpoints,
335 * so that one could (gdb) singlestep into the guest kernel's
336 * architectural breakpoint handler.
338 if (cpu->singlestep_enabled) {
342 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) {
344 * If we have an exact pc match, trigger the breakpoint.
345 * Otherwise, note matches within the page.
348 bool match_bp = false;
350 if (bp->flags & BP_GDB) {
352 } else if (bp->flags & BP_CPU) {
353 #ifdef CONFIG_USER_ONLY
354 g_assert_not_reached();
356 CPUClass *cc = CPU_GET_CLASS(cpu);
357 assert(cc->tcg_ops->debug_check_breakpoint);
358 match_bp = cc->tcg_ops->debug_check_breakpoint(cpu);
363 cpu->exception_index = EXCP_DEBUG;
366 } else if (((pc ^ bp->pc) & TARGET_PAGE_MASK) == 0) {
372 * Within the same page as a breakpoint, single-step,
373 * returning to helper_lookup_tb_ptr after each insn looking
374 * for the actual breakpoint.
376 * TODO: Perhaps better to record all of the TBs associated
377 * with a given virtual page that contains a breakpoint, and
378 * then invalidate them when a new overlapping breakpoint is
379 * set on the page. Non-overlapping TBs would not be
380 * invalidated, nor would any TB need to be invalidated as
381 * breakpoints are removed.
384 *cflags = (*cflags & ~CF_COUNT_MASK) | CF_NO_GOTO_TB | 1;
389 static inline bool check_for_breakpoints(CPUState *cpu, target_ulong pc,
392 return unlikely(!QTAILQ_EMPTY(&cpu->breakpoints)) &&
393 check_for_breakpoints_slow(cpu, pc, cflags);
397 * helper_lookup_tb_ptr: quick check for next tb
398 * @env: current cpu state
400 * Look for an existing TB matching the current cpu state.
401 * If found, return the code pointer. If not found, return
402 * the tcg epilogue so that we return into cpu_tb_exec.
404 const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
406 CPUState *cpu = env_cpu(env);
407 TranslationBlock *tb;
408 target_ulong cs_base, pc;
409 uint32_t flags, cflags;
411 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
413 cflags = curr_cflags(cpu);
414 if (check_for_breakpoints(cpu, pc, &cflags)) {
418 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
420 return tcg_code_gen_epilogue;
423 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
424 log_cpu_exec(pc, cpu, tb);
430 /* Execute a TB, and fix up the CPU state afterwards if necessary */
432 * Disable CFI checks.
433 * TCG creates binary blobs at runtime, with the transformed code.
434 * A TB is a blob of binary code, created at runtime and called with an
435 * indirect function call. Since such function did not exist at compile time,
436 * the CFI runtime has no way to verify its signature and would fail.
437 * TCG is not considered a security-sensitive part of QEMU so this does not
438 * affect the impact of CFI in environment with high security requirements
440 static inline TranslationBlock * QEMU_DISABLE_CFI
441 cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
443 CPUArchState *env = cpu->env_ptr;
445 TranslationBlock *last_tb;
446 const void *tb_ptr = itb->tc.ptr;
448 if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
449 log_cpu_exec(log_pc(cpu, itb), cpu, itb);
452 qemu_thread_jit_execute();
453 ret = tcg_qemu_tb_exec(env, tb_ptr);
455 qemu_plugin_disable_mem_helpers(cpu);
457 * TODO: Delay swapping back to the read-write region of the TB
458 * until we actually need to modify the TB. The read-only copy,
459 * coming from the rx region, shares the same host TLB entry as
460 * the code that executed the exit_tb opcode that arrived here.
461 * If we insist on touching both the RX and the RW pages, we
462 * double the host TLB pressure.
464 last_tb = tcg_splitwx_to_rw((void *)(ret & ~TB_EXIT_MASK));
465 *tb_exit = ret & TB_EXIT_MASK;
467 trace_exec_tb_exit(last_tb, *tb_exit);
469 if (*tb_exit > TB_EXIT_IDX1) {
470 /* We didn't start executing this TB (eg because the instruction
471 * counter hit zero); we must restore the guest PC to the address
472 * of the start of the TB.
474 CPUClass *cc = CPU_GET_CLASS(cpu);
476 if (cc->tcg_ops->synchronize_from_tb) {
477 cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
479 tcg_debug_assert(!(tb_cflags(last_tb) & CF_PCREL));
481 cc->set_pc(cpu, last_tb->pc);
483 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
484 target_ulong pc = log_pc(cpu, last_tb);
485 if (qemu_log_in_addr_range(pc)) {
486 qemu_log("Stopped execution of TB chain before %p ["
487 TARGET_FMT_lx "] %s\n",
488 last_tb->tc.ptr, pc, lookup_symbol(pc));
494 * If gdb single-step, and we haven't raised another exception,
495 * raise a debug exception. Single-step with another exception
496 * is handled in cpu_handle_exception.
498 if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
499 cpu->exception_index = EXCP_DEBUG;
507 static void cpu_exec_enter(CPUState *cpu)
509 CPUClass *cc = CPU_GET_CLASS(cpu);
511 if (cc->tcg_ops->cpu_exec_enter) {
512 cc->tcg_ops->cpu_exec_enter(cpu);
516 static void cpu_exec_exit(CPUState *cpu)
518 CPUClass *cc = CPU_GET_CLASS(cpu);
520 if (cc->tcg_ops->cpu_exec_exit) {
521 cc->tcg_ops->cpu_exec_exit(cpu);
525 void cpu_exec_step_atomic(CPUState *cpu)
527 CPUArchState *env = cpu->env_ptr;
528 TranslationBlock *tb;
529 target_ulong cs_base, pc;
530 uint32_t flags, cflags;
533 if (sigsetjmp(cpu->jmp_env, 0) == 0) {
535 g_assert(cpu == current_cpu);
536 g_assert(!cpu->running);
539 cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
541 cflags = curr_cflags(cpu);
542 /* Execute in a serial context. */
543 cflags &= ~CF_PARALLEL;
544 /* After 1 insn, return and release the exclusive lock. */
545 cflags |= CF_NO_GOTO_TB | CF_NO_GOTO_PTR | 1;
547 * No need to check_for_breakpoints here.
548 * We only arrive in cpu_exec_step_atomic after beginning execution
549 * of an insn that includes an atomic operation we can't handle.
550 * Any breakpoint for this insn will have been recognized earlier.
553 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
556 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
561 /* execute the generated code */
562 trace_exec_tb(tb, pc);
563 cpu_tb_exec(cpu, tb, &tb_exit);
566 #ifndef CONFIG_SOFTMMU
567 clear_helper_retaddr();
568 if (have_mmap_lock()) {
572 if (qemu_mutex_iothread_locked()) {
573 qemu_mutex_unlock_iothread();
575 assert_no_pages_locked();
579 * As we start the exclusive region before codegen we must still
580 * be in the region if we longjump out of either the codegen or
583 g_assert(cpu_in_exclusive_context(cpu));
584 cpu->running = false;
588 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
591 * Get the rx view of the structure, from which we find the
592 * executable code address, and tb_target_set_jmp_target can
593 * produce a pc-relative displacement to jmp_target_addr[n].
595 const TranslationBlock *c_tb = tcg_splitwx_to_rx(tb);
596 uintptr_t offset = tb->jmp_insn_offset[n];
597 uintptr_t jmp_rx = (uintptr_t)tb->tc.ptr + offset;
598 uintptr_t jmp_rw = jmp_rx - tcg_splitwx_diff;
600 tb->jmp_target_addr[n] = addr;
601 tb_target_set_jmp_target(c_tb, n, jmp_rx, jmp_rw);
604 static inline void tb_add_jump(TranslationBlock *tb, int n,
605 TranslationBlock *tb_next)
609 qemu_thread_jit_write();
610 assert(n < ARRAY_SIZE(tb->jmp_list_next));
611 qemu_spin_lock(&tb_next->jmp_lock);
613 /* make sure the destination TB is valid */
614 if (tb_next->cflags & CF_INVALID) {
615 goto out_unlock_next;
617 /* Atomically claim the jump destination slot only if it was NULL */
618 old = qatomic_cmpxchg(&tb->jmp_dest[n], (uintptr_t)NULL,
621 goto out_unlock_next;
624 /* patch the native jump address */
625 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc.ptr);
627 /* add in TB jmp list */
628 tb->jmp_list_next[n] = tb_next->jmp_list_head;
629 tb_next->jmp_list_head = (uintptr_t)tb | n;
631 qemu_spin_unlock(&tb_next->jmp_lock);
633 qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n",
634 tb->tc.ptr, n, tb_next->tc.ptr);
638 qemu_spin_unlock(&tb_next->jmp_lock);
642 static inline bool cpu_handle_halt(CPUState *cpu)
644 #ifndef CONFIG_USER_ONLY
646 #if defined(TARGET_I386)
647 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) {
648 X86CPU *x86_cpu = X86_CPU(cpu);
649 qemu_mutex_lock_iothread();
650 apic_poll_irq(x86_cpu->apic_state);
651 cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL);
652 qemu_mutex_unlock_iothread();
654 #endif /* TARGET_I386 */
655 if (!cpu_has_work(cpu)) {
661 #endif /* !CONFIG_USER_ONLY */
666 static inline void cpu_handle_debug_exception(CPUState *cpu)
668 CPUClass *cc = CPU_GET_CLASS(cpu);
671 if (!cpu->watchpoint_hit) {
672 QTAILQ_FOREACH(wp, &cpu->watchpoints, entry) {
673 wp->flags &= ~BP_WATCHPOINT_HIT;
677 if (cc->tcg_ops->debug_excp_handler) {
678 cc->tcg_ops->debug_excp_handler(cpu);
682 static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
684 if (cpu->exception_index < 0) {
685 #ifndef CONFIG_USER_ONLY
686 if (replay_has_exception()
687 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0) {
688 /* Execute just one insn to trigger exception pending in the log */
689 cpu->cflags_next_tb = (curr_cflags(cpu) & ~CF_USE_ICOUNT)
695 if (cpu->exception_index >= EXCP_INTERRUPT) {
696 /* exit request from the cpu execution loop */
697 *ret = cpu->exception_index;
698 if (*ret == EXCP_DEBUG) {
699 cpu_handle_debug_exception(cpu);
701 cpu->exception_index = -1;
704 #if defined(CONFIG_USER_ONLY)
705 /* if user mode only, we simulate a fake exception
706 which will be handled outside the cpu execution
708 #if defined(TARGET_I386)
709 CPUClass *cc = CPU_GET_CLASS(cpu);
710 cc->tcg_ops->fake_user_interrupt(cpu);
711 #endif /* TARGET_I386 */
712 *ret = cpu->exception_index;
713 cpu->exception_index = -1;
716 if (replay_exception()) {
717 CPUClass *cc = CPU_GET_CLASS(cpu);
718 qemu_mutex_lock_iothread();
719 cc->tcg_ops->do_interrupt(cpu);
720 qemu_mutex_unlock_iothread();
721 cpu->exception_index = -1;
723 if (unlikely(cpu->singlestep_enabled)) {
725 * After processing the exception, ensure an EXCP_DEBUG is
726 * raised when single-stepping so that GDB doesn't miss the
730 cpu_handle_debug_exception(cpu);
733 } else if (!replay_has_interrupt()) {
734 /* give a chance to iothread in replay mode */
735 *ret = EXCP_INTERRUPT;
744 #ifndef CONFIG_USER_ONLY
746 * CPU_INTERRUPT_POLL is a virtual event which gets converted into a
747 * "real" interrupt event later. It does not need to be recorded for
750 static inline bool need_replay_interrupt(int interrupt_request)
752 #if defined(TARGET_I386)
753 return !(interrupt_request & CPU_INTERRUPT_POLL);
758 #endif /* !CONFIG_USER_ONLY */
760 static inline bool cpu_handle_interrupt(CPUState *cpu,
761 TranslationBlock **last_tb)
764 * If we have requested custom cflags with CF_NOIRQ we should
765 * skip checking here. Any pending interrupts will get picked up
766 * by the next TB we execute under normal cflags.
768 if (cpu->cflags_next_tb != -1 && cpu->cflags_next_tb & CF_NOIRQ) {
772 /* Clear the interrupt flag now since we're processing
773 * cpu->interrupt_request and cpu->exit_request.
774 * Ensure zeroing happens before reading cpu->exit_request or
775 * cpu->interrupt_request (see also smp_wmb in cpu_exit())
777 qatomic_mb_set(&cpu_neg(cpu)->icount_decr.u16.high, 0);
779 if (unlikely(qatomic_read(&cpu->interrupt_request))) {
780 int interrupt_request;
781 qemu_mutex_lock_iothread();
782 interrupt_request = cpu->interrupt_request;
783 if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
784 /* Mask out external interrupts for this step. */
785 interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
787 if (interrupt_request & CPU_INTERRUPT_DEBUG) {
788 cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
789 cpu->exception_index = EXCP_DEBUG;
790 qemu_mutex_unlock_iothread();
793 #if !defined(CONFIG_USER_ONLY)
794 if (replay_mode == REPLAY_MODE_PLAY && !replay_has_interrupt()) {
796 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
798 cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
800 cpu->exception_index = EXCP_HLT;
801 qemu_mutex_unlock_iothread();
804 #if defined(TARGET_I386)
805 else if (interrupt_request & CPU_INTERRUPT_INIT) {
806 X86CPU *x86_cpu = X86_CPU(cpu);
807 CPUArchState *env = &x86_cpu->env;
809 cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0, 0);
810 do_cpu_init(x86_cpu);
811 cpu->exception_index = EXCP_HALTED;
812 qemu_mutex_unlock_iothread();
816 else if (interrupt_request & CPU_INTERRUPT_RESET) {
819 qemu_mutex_unlock_iothread();
822 #endif /* !TARGET_I386 */
823 /* The target hook has 3 exit conditions:
824 False when the interrupt isn't processed,
825 True when it is, and we should restart on a new TB,
826 and via longjmp via cpu_loop_exit. */
828 CPUClass *cc = CPU_GET_CLASS(cpu);
830 if (cc->tcg_ops->cpu_exec_interrupt &&
831 cc->tcg_ops->cpu_exec_interrupt(cpu, interrupt_request)) {
832 if (need_replay_interrupt(interrupt_request)) {
836 * After processing the interrupt, ensure an EXCP_DEBUG is
837 * raised when single-stepping so that GDB doesn't miss the
840 if (unlikely(cpu->singlestep_enabled)) {
841 cpu->exception_index = EXCP_DEBUG;
842 qemu_mutex_unlock_iothread();
845 cpu->exception_index = -1;
848 /* The target hook may have updated the 'cpu->interrupt_request';
849 * reload the 'interrupt_request' value */
850 interrupt_request = cpu->interrupt_request;
852 #endif /* !CONFIG_USER_ONLY */
853 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
854 cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
855 /* ensure that no TB jump will be modified as
856 the program flow was changed */
860 /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */
861 qemu_mutex_unlock_iothread();
864 /* Finally, check if we need to exit to the main loop. */
865 if (unlikely(qatomic_read(&cpu->exit_request))
867 && (cpu->cflags_next_tb == -1 || cpu->cflags_next_tb & CF_USE_ICOUNT)
868 && cpu_neg(cpu)->icount_decr.u16.low + cpu->icount_extra == 0)) {
869 qatomic_set(&cpu->exit_request, 0);
870 if (cpu->exception_index == -1) {
871 cpu->exception_index = EXCP_INTERRUPT;
879 static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
881 TranslationBlock **last_tb, int *tb_exit)
885 trace_exec_tb(tb, pc);
886 tb = cpu_tb_exec(cpu, tb, tb_exit);
887 if (*tb_exit != TB_EXIT_REQUESTED) {
893 insns_left = qatomic_read(&cpu_neg(cpu)->icount_decr.u32);
894 if (insns_left < 0) {
895 /* Something asked us to stop executing chained TBs; just
896 * continue round the main loop. Whatever requested the exit
897 * will also have set something else (eg exit_request or
898 * interrupt_request) which will be handled by
899 * cpu_handle_interrupt. cpu_handle_interrupt will also
900 * clear cpu->icount_decr.u16.high.
905 /* Instruction counter expired. */
906 assert(icount_enabled());
907 #ifndef CONFIG_USER_ONLY
908 /* Ensure global icount has gone forward */
910 /* Refill decrementer and continue execution. */
911 insns_left = MIN(0xffff, cpu->icount_budget);
912 cpu_neg(cpu)->icount_decr.u16.low = insns_left;
913 cpu->icount_extra = cpu->icount_budget - insns_left;
916 * If the next tb has more instructions than we have left to
917 * execute we need to ensure we find/generate a TB with exactly
918 * insns_left instructions in it.
920 if (insns_left > 0 && insns_left < tb->icount) {
921 assert(insns_left <= CF_COUNT_MASK);
922 assert(cpu->icount_extra == 0);
923 cpu->cflags_next_tb = (tb->cflags & ~CF_COUNT_MASK) | insns_left;
928 /* main execution loop */
930 static int __attribute__((noinline))
931 cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
935 /* if an exception is pending, we execute it here */
936 while (!cpu_handle_exception(cpu, &ret)) {
937 TranslationBlock *last_tb = NULL;
940 while (!cpu_handle_interrupt(cpu, &last_tb)) {
941 TranslationBlock *tb;
942 target_ulong cs_base, pc;
943 uint32_t flags, cflags;
945 cpu_get_tb_cpu_state(cpu->env_ptr, &pc, &cs_base, &flags);
948 * When requested, use an exact setting for cflags for the next
949 * execution. This is used for icount, precise smc, and stop-
950 * after-access watchpoints. Since this request should never
951 * have CF_INVALID set, -1 is a convenient invalid value that
952 * does not require tcg headers for cpu_common_reset.
954 cflags = cpu->cflags_next_tb;
956 cflags = curr_cflags(cpu);
958 cpu->cflags_next_tb = -1;
961 if (check_for_breakpoints(cpu, pc, &cflags)) {
965 tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
971 tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
975 * We add the TB in the virtual pc hash table
976 * for the fast lookup
978 h = tb_jmp_cache_hash_func(pc);
979 jc = cpu->tb_jmp_cache;
980 if (cflags & CF_PCREL) {
981 jc->array[h].pc = pc;
982 /* Ensure pc is written first. */
983 qatomic_store_release(&jc->array[h].tb, tb);
985 /* Use the pc value already stored in tb->pc. */
986 qatomic_set(&jc->array[h].tb, tb);
990 #ifndef CONFIG_USER_ONLY
992 * We don't take care of direct jumps when address mapping
993 * changes in system emulation. So it's not safe to make a
994 * direct jump to a TB spanning two pages because the mapping
995 * for the second page can change.
997 if (tb_page_addr1(tb) != -1) {
1001 /* See if we can patch the calling TB. */
1003 tb_add_jump(last_tb, tb_exit, tb);
1006 cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit);
1008 /* Try to align the host and virtual clocks
1009 if the guest is in advance */
1010 align_clocks(sc, cpu);
1016 static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
1018 /* Prepare setjmp context for exception handling. */
1019 if (unlikely(sigsetjmp(cpu->jmp_env, 0) != 0)) {
1020 /* Non-buggy compilers preserve this; assert the correct value. */
1021 g_assert(cpu == current_cpu);
1023 #ifndef CONFIG_SOFTMMU
1024 clear_helper_retaddr();
1025 if (have_mmap_lock()) {
1029 if (qemu_mutex_iothread_locked()) {
1030 qemu_mutex_unlock_iothread();
1033 assert_no_pages_locked();
1036 return cpu_exec_loop(cpu, sc);
1039 int cpu_exec(CPUState *cpu)
1042 SyncClocks sc = { 0 };
1044 /* replay_interrupt may need current_cpu */
1047 if (cpu_handle_halt(cpu)) {
1052 cpu_exec_enter(cpu);
1055 * Calculate difference between guest clock and host clock.
1056 * This delay includes the delay of the last cycle, so
1057 * what we have to do is sleep until it is 0. As for the
1058 * advance/delay we gain here, we try to fix it next time.
1060 init_delay_params(&sc, cpu);
1062 ret = cpu_exec_setjmp(cpu, &sc);
1070 void tcg_exec_realizefn(CPUState *cpu, Error **errp)
1072 static bool tcg_target_initialized;
1073 CPUClass *cc = CPU_GET_CLASS(cpu);
1075 if (!tcg_target_initialized) {
1076 cc->tcg_ops->initialize();
1077 tcg_target_initialized = true;
1080 cpu->tb_jmp_cache = g_new0(CPUJumpCache, 1);
1082 #ifndef CONFIG_USER_ONLY
1083 tcg_iommu_init_notifier_list(cpu);
1084 #endif /* !CONFIG_USER_ONLY */
1085 /* qemu_plugin_vcpu_init_hook delayed until cpu_index assigned. */
1088 /* undo the initializations in reverse order */
1089 void tcg_exec_unrealizefn(CPUState *cpu)
1091 #ifndef CONFIG_USER_ONLY
1092 tcg_iommu_free_notifier_list(cpu);
1093 #endif /* !CONFIG_USER_ONLY */
1096 g_free_rcu(cpu->tb_jmp_cache, rcu);