2 * Copyright 2014 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 * Declare public libdrm_amdgpu API
29 * This file define API exposed by libdrm_amdgpu library.
30 * User wanted to use libdrm_amdgpu functionality must include
40 struct drm_amdgpu_info_hw_ip;
42 /*--------------------------------------------------------------------------*/
43 /* --------------------------- Defines ------------------------------------ */
44 /*--------------------------------------------------------------------------*/
47 * Define max. number of Command Buffers (IB) which could be sent to the single
48 * hardware IP to accommodate CE/DE requirements
50 * \sa amdgpu_cs_ib_info
52 #define AMDGPU_CS_MAX_IBS_PER_SUBMIT 4
55 * Special timeout value meaning that the timeout is infinite.
57 #define AMDGPU_TIMEOUT_INFINITE 0xffffffffffffffffull
60 * Used in amdgpu_cs_query_fence_status(), meaning that the given timeout
63 #define AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE (1 << 0)
65 /*--------------------------------------------------------------------------*/
66 /* ----------------------------- Enums ------------------------------------ */
67 /*--------------------------------------------------------------------------*/
70 * Enum describing possible handle types
72 * \sa amdgpu_bo_import, amdgpu_bo_export
75 enum amdgpu_bo_handle_type {
76 /** GEM flink name (needs DRM authentication, used by DRI2) */
77 amdgpu_bo_handle_type_gem_flink_name = 0,
79 /** KMS handle which is used by all driver ioctls */
80 amdgpu_bo_handle_type_kms = 1,
82 /** DMA-buf fd handle */
83 amdgpu_bo_handle_type_dma_buf_fd = 2
86 /** Define known types of GPU VM VA ranges */
87 enum amdgpu_gpu_va_range
89 /** Allocate from "normal"/general range */
90 amdgpu_gpu_va_range_general = 0
93 /*--------------------------------------------------------------------------*/
94 /* -------------------------- Datatypes ----------------------------------- */
95 /*--------------------------------------------------------------------------*/
98 * Define opaque pointer to context associated with fd.
99 * This context will be returned as the result of
100 * "initialize" function and should be pass as the first
101 * parameter to any API call
103 typedef struct amdgpu_device *amdgpu_device_handle;
106 * Define GPU Context type as pointer to opaque structure
107 * Example of GPU Context is the "rendering" context associated
108 * with OpenGL context (glCreateContext)
110 typedef struct amdgpu_context *amdgpu_context_handle;
113 * Define handle for amdgpu resources: buffer, GDS, etc.
115 typedef struct amdgpu_bo *amdgpu_bo_handle;
118 * Define handle for list of BOs
120 typedef struct amdgpu_bo_list *amdgpu_bo_list_handle;
123 * Define handle to be used to work with VA allocated ranges
125 typedef struct amdgpu_va *amdgpu_va_handle;
128 * Define handle for semaphore
130 typedef struct amdgpu_semaphore *amdgpu_semaphore_handle;
132 /*--------------------------------------------------------------------------*/
133 /* -------------------------- Structures ---------------------------------- */
134 /*--------------------------------------------------------------------------*/
137 * Structure describing memory allocation request
139 * \sa amdgpu_bo_alloc()
142 struct amdgpu_bo_alloc_request {
143 /** Allocation request. It must be aligned correctly. */
147 * It may be required to have some specific alignment requirements
148 * for physical back-up storage (e.g. for displayable surface).
149 * If 0 there is no special alignment requirement
151 uint64_t phys_alignment;
154 * UMD should specify where to allocate memory and how it
155 * will be accessed by the CPU.
157 uint32_t preferred_heap;
159 /** Additional flags passed on allocation */
164 * Special UMD specific information associated with buffer.
166 * It may be need to pass some buffer charactersitic as part
167 * of buffer sharing. Such information are defined UMD and
168 * opaque for libdrm_amdgpu as well for kernel driver.
170 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info,
171 * amdgpu_bo_import(), amdgpu_bo_export
174 struct amdgpu_bo_metadata {
175 /** Special flag associated with surface */
179 * ASIC-specific tiling information (also used by DCE).
180 * The encoding is defined by the AMDGPU_TILING_* definitions.
182 uint64_t tiling_info;
184 /** Size of metadata associated with the buffer, in bytes. */
185 uint32_t size_metadata;
187 /** UMD specific metadata. Opaque for kernel */
188 uint32_t umd_metadata[64];
192 * Structure describing allocated buffer. Client may need
193 * to query such information as part of 'sharing' buffers mechanism
195 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_query_info(),
196 * amdgpu_bo_import(), amdgpu_bo_export()
198 struct amdgpu_bo_info {
199 /** Allocated memory size */
203 * It may be required to have some specific alignment requirements
204 * for physical back-up storage.
206 uint64_t phys_alignment;
208 /** Heap where to allocate memory. */
209 uint32_t preferred_heap;
211 /** Additional allocation flags. */
212 uint64_t alloc_flags;
214 /** Metadata associated with buffer if any. */
215 struct amdgpu_bo_metadata metadata;
219 * Structure with information about "imported" buffer
221 * \sa amdgpu_bo_import()
224 struct amdgpu_bo_import_result {
225 /** Handle of memory/buffer to use */
226 amdgpu_bo_handle buf_handle;
234 * Structure to describe GDS partitioning information.
235 * \note OA and GWS resources are asscoiated with GDS partition
237 * \sa amdgpu_gpu_resource_query_gds_info
240 struct amdgpu_gds_resource_info {
241 uint32_t gds_gfx_partition_size;
242 uint32_t compute_partition_size;
243 uint32_t gds_total_size;
244 uint32_t gws_per_gfx_partition;
245 uint32_t gws_per_compute_partition;
246 uint32_t oa_per_gfx_partition;
247 uint32_t oa_per_compute_partition;
251 * Structure describing CS fence
253 * \sa amdgpu_cs_query_fence_status(), amdgpu_cs_request, amdgpu_cs_submit()
256 struct amdgpu_cs_fence {
258 /** In which context IB was sent to execution */
259 amdgpu_context_handle context;
261 /** To which HW IP type the fence belongs */
264 /** IP instance index if there are several IPs of the same type. */
265 uint32_t ip_instance;
267 /** Ring index of the HW IP */
270 /** Specify fence for which we need to check submission status.*/
275 * Structure describing IB
277 * \sa amdgpu_cs_request, amdgpu_cs_submit()
280 struct amdgpu_cs_ib_info {
284 /** Virtual MC address of the command buffer */
285 uint64_t ib_mc_address;
288 * Size of Command Buffer to be submitted.
289 * - The size is in units of dwords (4 bytes).
296 * Structure describing fence information
298 * \sa amdgpu_cs_request, amdgpu_cs_query_fence,
299 * amdgpu_cs_submit(), amdgpu_cs_query_fence_status()
301 struct amdgpu_cs_fence_info {
302 /** buffer object for the fence */
303 amdgpu_bo_handle handle;
305 /** fence offset in the unit of sizeof(uint64_t) */
310 * Structure describing submission request
312 * \note We could have several IBs as packet. e.g. CE, CE, DE case for gfx
314 * \sa amdgpu_cs_submit()
316 struct amdgpu_cs_request {
317 /** Specify flags with additional information */
320 /** Specify HW IP block type to which to send the IB. */
323 /** IP instance index if there are several IPs of the same type. */
324 unsigned ip_instance;
327 * Specify ring index of the IP. We could have several rings
328 * in the same IP. E.g. 0 for SDMA0 and 1 for SDMA1.
333 * List handle with resources used by this request.
335 amdgpu_bo_list_handle resources;
338 * Number of dependencies this Command submission needs to
339 * wait for before starting execution.
341 uint32_t number_of_dependencies;
344 * Array of dependencies which need to be met before
345 * execution can start.
347 struct amdgpu_cs_fence *dependencies;
349 /** Number of IBs to submit in the field ibs. */
350 uint32_t number_of_ibs;
353 * IBs to submit. Those IBs will be submit together as single entity
355 struct amdgpu_cs_ib_info *ibs;
358 * The returned sequence number for the command submission
363 * The fence information
365 struct amdgpu_cs_fence_info fence_info;
369 * Structure which provide information about GPU VM MC Address space
370 * alignments requirements
372 * \sa amdgpu_query_buffer_size_alignment
374 struct amdgpu_buffer_size_alignments {
375 /** Size alignment requirement for allocation in
380 * Size alignment requirement for allocation in remote memory
382 uint64_t size_remote;
386 * Structure which provide information about heap
388 * \sa amdgpu_query_heap_info()
391 struct amdgpu_heap_info {
392 /** Theoretical max. available memory in the given heap */
396 * Number of bytes allocated in the heap. This includes all processes
397 * and private allocations in the kernel. It changes when new buffers
398 * are allocated, freed, and moved. It cannot be larger than
404 * Theoretical possible max. size of buffer which
405 * could be allocated in the given heap
407 uint64_t max_allocation;
411 * Describe GPU h/w info needed for UMD correct initialization
413 * \sa amdgpu_query_gpu_info()
415 struct amdgpu_gpu_info {
420 /** Chip external revision */
421 uint32_t chip_external_rev;
426 /** max engine clock*/
427 uint64_t max_engine_clk;
428 /** max memory clock */
429 uint64_t max_memory_clk;
430 /** number of shader engines */
431 uint32_t num_shader_engines;
432 /** number of shader arrays per engine */
433 uint32_t num_shader_arrays_per_engine;
434 /** Number of available good shader pipes */
435 uint32_t avail_quad_shader_pipes;
436 /** Max. number of shader pipes.(including good and bad pipes */
437 uint32_t max_quad_shader_pipes;
438 /** Number of parameter cache entries per shader quad pipe */
439 uint32_t cache_entries_per_quad_pipe;
440 /** Number of available graphics context */
441 uint32_t num_hw_gfx_contexts;
442 /** Number of render backend pipes */
444 /** Enabled render backend pipe mask */
445 uint32_t enabled_rb_pipes_mask;
446 /** Frequency of GPU Counter */
447 uint32_t gpu_counter_freq;
448 /** CC_RB_BACKEND_DISABLE.BACKEND_DISABLE per SE */
449 uint32_t backend_disable[4];
450 /** Value of MC_ARB_RAMCFG register*/
451 uint32_t mc_arb_ramcfg;
452 /** Value of GB_ADDR_CONFIG */
453 uint32_t gb_addr_cfg;
454 /** Values of the GB_TILE_MODE0..31 registers */
455 uint32_t gb_tile_mode[32];
456 /** Values of GB_MACROTILE_MODE0..15 registers */
457 uint32_t gb_macro_tile_mode[16];
458 /** Value of PA_SC_RASTER_CONFIG register per SE */
459 uint32_t pa_sc_raster_cfg[4];
460 /** Value of PA_SC_RASTER_CONFIG_1 register per SE */
461 uint32_t pa_sc_raster_cfg1[4];
463 uint32_t cu_active_number;
465 uint32_t cu_bitmap[4][4];
466 /* video memory type info*/
468 /* video memory bit width*/
469 uint32_t vram_bit_width;
470 /** constant engine ram size*/
471 uint32_t ce_ram_size;
472 /* vce harvesting instance */
473 uint32_t vce_harvest_config;
474 /* PCI revision ID */
479 /*--------------------------------------------------------------------------*/
480 /*------------------------- Functions --------------------------------------*/
481 /*--------------------------------------------------------------------------*/
484 * Initialization / Cleanup
490 * \param fd - \c [in] File descriptor for AMD GPU device
491 * received previously as the result of
492 * e.g. drmOpen() call.
493 * For legacy fd type, the DRI2/DRI3
494 * authentication should be done before
495 * calling this function.
496 * \param major_version - \c [out] Major version of library. It is assumed
497 * that adding new functionality will cause
498 * increase in major version
499 * \param minor_version - \c [out] Minor version of library
500 * \param device_handle - \c [out] Pointer to opaque context which should
501 * be passed as the first parameter on each
505 * \return 0 on success\n
506 * <0 - Negative POSIX Error code
509 * \sa amdgpu_device_deinitialize()
511 int amdgpu_device_initialize(int fd,
512 uint32_t *major_version,
513 uint32_t *minor_version,
514 amdgpu_device_handle *device_handle);
518 * When access to such library does not needed any more the special
519 * function must be call giving opportunity to clean up any
520 * resources if needed.
522 * \param device_handle - \c [in] Context associated with file
523 * descriptor for AMD GPU device
524 * received previously as the
525 * result e.g. of drmOpen() call.
527 * \return 0 on success\n
528 * <0 - Negative POSIX Error code
530 * \sa amdgpu_device_initialize()
533 int amdgpu_device_deinitialize(amdgpu_device_handle device_handle);
541 * Allocate memory to be used by UMD for GPU related operations
543 * \param dev - \c [in] Device handle.
544 * See #amdgpu_device_initialize()
545 * \param alloc_buffer - \c [in] Pointer to the structure describing an
547 * \param buf_handle - \c [out] Allocated buffer handle
549 * \return 0 on success\n
550 * <0 - Negative POSIX Error code
552 * \sa amdgpu_bo_free()
554 int amdgpu_bo_alloc(amdgpu_device_handle dev,
555 struct amdgpu_bo_alloc_request *alloc_buffer,
556 amdgpu_bo_handle *buf_handle);
559 * Associate opaque data with buffer to be queried by another UMD
561 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
562 * \param buf_handle - \c [in] Buffer handle
563 * \param info - \c [in] Metadata to associated with buffer
565 * \return 0 on success\n
566 * <0 - Negative POSIX Error code
568 int amdgpu_bo_set_metadata(amdgpu_bo_handle buf_handle,
569 struct amdgpu_bo_metadata *info);
572 * Query buffer information including metadata previusly associated with
575 * \param dev - \c [in] Device handle.
576 * See #amdgpu_device_initialize()
577 * \param buf_handle - \c [in] Buffer handle
578 * \param info - \c [out] Structure describing buffer
580 * \return 0 on success\n
581 * <0 - Negative POSIX Error code
583 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
585 int amdgpu_bo_query_info(amdgpu_bo_handle buf_handle,
586 struct amdgpu_bo_info *info);
589 * Allow others to get access to buffer
591 * \param dev - \c [in] Device handle.
592 * See #amdgpu_device_initialize()
593 * \param buf_handle - \c [in] Buffer handle
594 * \param type - \c [in] Type of handle requested
595 * \param shared_handle - \c [out] Special "shared" handle
597 * \return 0 on success\n
598 * <0 - Negative POSIX Error code
600 * \sa amdgpu_bo_import()
603 int amdgpu_bo_export(amdgpu_bo_handle buf_handle,
604 enum amdgpu_bo_handle_type type,
605 uint32_t *shared_handle);
608 * Request access to "shared" buffer
610 * \param dev - \c [in] Device handle.
611 * See #amdgpu_device_initialize()
612 * \param type - \c [in] Type of handle requested
613 * \param shared_handle - \c [in] Shared handle received as result "import"
615 * \param output - \c [out] Pointer to structure with information
616 * about imported buffer
618 * \return 0 on success\n
619 * <0 - Negative POSIX Error code
621 * \note Buffer must be "imported" only using new "fd" (different from
622 * one used by "exporter").
624 * \sa amdgpu_bo_export()
627 int amdgpu_bo_import(amdgpu_device_handle dev,
628 enum amdgpu_bo_handle_type type,
629 uint32_t shared_handle,
630 struct amdgpu_bo_import_result *output);
633 * Request GPU access to user allocated memory e.g. via "malloc"
635 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
636 * \param cpu - [in] CPU address of user allocated memory which we
637 * want to map to GPU address space (make GPU accessible)
638 * (This address must be correctly aligned).
639 * \param size - [in] Size of allocation (must be correctly aligned)
640 * \param buf_handle - [out] Buffer handle for the userptr memory
641 * resource on submission and be used in other operations.
644 * \return 0 on success\n
645 * <0 - Negative POSIX Error code
648 * This call doesn't guarantee that such memory will be persistently
649 * "locked" / make non-pageable. The purpose of this call is to provide
650 * opportunity for GPU get access to this resource during submission.
652 * The maximum amount of memory which could be mapped in this call depends
653 * if overcommit is disabled or not. If overcommit is disabled than the max.
654 * amount of memory to be pinned will be limited by left "free" size in total
655 * amount of memory which could be locked simultaneously ("GART" size).
657 * Supported (theoretical) max. size of mapping is restricted only by
660 * It is responsibility of caller to correctly specify access rights
663 int amdgpu_create_bo_from_user_mem(amdgpu_device_handle dev,
664 void *cpu, uint64_t size,
665 amdgpu_bo_handle *buf_handle);
668 * Free previosuly allocated memory
670 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
671 * \param buf_handle - \c [in] Buffer handle to free
673 * \return 0 on success\n
674 * <0 - Negative POSIX Error code
676 * \note In the case of memory shared between different applications all
677 * resources will be “physically” freed only all such applications
679 * \note If is UMD responsibility to ‘free’ buffer only when there is no
682 * \sa amdgpu_bo_set_metadata(), amdgpu_bo_alloc()
685 int amdgpu_bo_free(amdgpu_bo_handle buf_handle);
688 * Request CPU access to GPU accessible memory
690 * \param buf_handle - \c [in] Buffer handle
691 * \param cpu - \c [out] CPU address to be used for access
693 * \return 0 on success\n
694 * <0 - Negative POSIX Error code
696 * \sa amdgpu_bo_cpu_unmap()
699 int amdgpu_bo_cpu_map(amdgpu_bo_handle buf_handle, void **cpu);
702 * Release CPU access to GPU memory
704 * \param buf_handle - \c [in] Buffer handle
706 * \return 0 on success\n
707 * <0 - Negative POSIX Error code
709 * \sa amdgpu_bo_cpu_map()
712 int amdgpu_bo_cpu_unmap(amdgpu_bo_handle buf_handle);
715 * Wait until a buffer is not used by the device.
717 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
718 * \param buf_handle - \c [in] Buffer handle.
719 * \param timeout_ns - Timeout in nanoseconds.
720 * \param buffer_busy - 0 if buffer is idle, all GPU access was completed
721 * and no GPU access is scheduled.
722 * 1 GPU access is in fly or scheduled
724 * \return 0 - on success
725 * <0 - Negative POSIX Error code
727 int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle,
732 * Creates a BO list handle for command submission.
734 * \param dev - \c [in] Device handle.
735 * See #amdgpu_device_initialize()
736 * \param number_of_resources - \c [in] Number of BOs in the list
737 * \param resources - \c [in] List of BO handles
738 * \param resource_prios - \c [in] Optional priority for each handle
739 * \param result - \c [out] Created BO list handle
741 * \return 0 on success\n
742 * <0 - Negative POSIX Error code
744 * \sa amdgpu_bo_list_destroy()
746 int amdgpu_bo_list_create(amdgpu_device_handle dev,
747 uint32_t number_of_resources,
748 amdgpu_bo_handle *resources,
749 uint8_t *resource_prios,
750 amdgpu_bo_list_handle *result);
753 * Destroys a BO list handle.
755 * \param handle - \c [in] BO list handle.
757 * \return 0 on success\n
758 * <0 - Negative POSIX Error code
760 * \sa amdgpu_bo_list_create()
762 int amdgpu_bo_list_destroy(amdgpu_bo_list_handle handle);
765 * Update resources for existing BO list
767 * \param handle - \c [in] BO list handle
768 * \param number_of_resources - \c [in] Number of BOs in the list
769 * \param resources - \c [in] List of BO handles
770 * \param resource_prios - \c [in] Optional priority for each handle
772 * \return 0 on success\n
773 * <0 - Negative POSIX Error code
775 * \sa amdgpu_bo_list_update()
777 int amdgpu_bo_list_update(amdgpu_bo_list_handle handle,
778 uint32_t number_of_resources,
779 amdgpu_bo_handle *resources,
780 uint8_t *resource_prios);
783 * GPU Execution context
788 * Create GPU execution Context
790 * For the purpose of GPU Scheduler and GPU Robustness extensions it is
791 * necessary to have information/identify rendering/compute contexts.
792 * It also may be needed to associate some specific requirements with such
793 * contexts. Kernel driver will guarantee that submission from the same
794 * context will always be executed in order (first come, first serve).
797 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
798 * \param context - \c [out] GPU Context handle
800 * \return 0 on success\n
801 * <0 - Negative POSIX Error code
803 * \sa amdgpu_cs_ctx_free()
806 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
807 amdgpu_context_handle *context);
811 * Destroy GPU execution context when not needed any more
813 * \param context - \c [in] GPU Context handle
815 * \return 0 on success\n
816 * <0 - Negative POSIX Error code
818 * \sa amdgpu_cs_ctx_create()
821 int amdgpu_cs_ctx_free(amdgpu_context_handle context);
824 * Query reset state for the specific GPU Context
826 * \param context - \c [in] GPU Context handle
827 * \param state - \c [out] One of AMDGPU_CTX_*_RESET
828 * \param hangs - \c [out] Number of hangs caused by the context.
830 * \return 0 on success\n
831 * <0 - Negative POSIX Error code
833 * \sa amdgpu_cs_ctx_create()
836 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
837 uint32_t *state, uint32_t *hangs);
840 * Command Buffers Management
845 * Send request to submit command buffers to hardware.
847 * Kernel driver could use GPU Scheduler to make decision when physically
848 * sent this request to the hardware. Accordingly this request could be put
849 * in queue and sent for execution later. The only guarantee is that request
850 * from the same GPU context to the same ip:ip_instance:ring will be executed in
853 * The caller can specify the user fence buffer/location with the fence_info in the
854 * cs_request.The sequence number is returned via the 'seq_no' parameter
855 * in ibs_request structure.
858 * \param dev - \c [in] Device handle.
859 * See #amdgpu_device_initialize()
860 * \param context - \c [in] GPU Context
861 * \param flags - \c [in] Global submission flags
862 * \param ibs_request - \c [in/out] Pointer to submission requests.
863 * We could submit to the several
864 * engines/rings simulteniously as
866 * \param number_of_requests - \c [in] Number of submission requests
868 * \return 0 on success\n
869 * <0 - Negative POSIX Error code
871 * \note It is required to pass correct resource list with buffer handles
872 * which will be accessible by command buffers from submission
873 * This will allow kernel driver to correctly implement "paging".
874 * Failure to do so will have unpredictable results.
876 * \sa amdgpu_command_buffer_alloc(), amdgpu_command_buffer_free(),
877 * amdgpu_cs_query_fence_status()
880 int amdgpu_cs_submit(amdgpu_context_handle context,
882 struct amdgpu_cs_request *ibs_request,
883 uint32_t number_of_requests);
886 * Query status of Command Buffer Submission
888 * \param fence - \c [in] Structure describing fence to query
889 * \param timeout_ns - \c [in] Timeout value to wait
890 * \param flags - \c [in] Flags for the query
891 * \param expired - \c [out] If fence expired or not.\n
892 * 0 – if fence is not expired\n
895 * \return 0 on success\n
896 * <0 - Negative POSIX Error code
898 * \note If UMD wants only to check operation status and returned immediately
899 * then timeout value as 0 must be passed. In this case success will be
900 * returned in the case if submission was completed or timeout error
903 * \sa amdgpu_cs_submit()
905 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
916 * Query allocation size alignments
918 * UMD should query information about GPU VM MC size alignments requirements
919 * to be able correctly choose required allocation size and implement
920 * internal optimization if needed.
922 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
923 * \param info - \c [out] Pointer to structure to get size alignment
926 * \return 0 on success\n
927 * <0 - Negative POSIX Error code
930 int amdgpu_query_buffer_size_alignment(amdgpu_device_handle dev,
931 struct amdgpu_buffer_size_alignments
935 * Query firmware versions
937 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
938 * \param fw_type - \c [in] AMDGPU_INFO_FW_*
939 * \param ip_instance - \c [in] Index of the IP block of the same type.
940 * \param index - \c [in] Index of the engine. (for SDMA and MEC)
941 * \param version - \c [out] Pointer to to the "version" return value
942 * \param feature - \c [out] Pointer to to the "feature" return value
944 * \return 0 on success\n
945 * <0 - Negative POSIX Error code
948 int amdgpu_query_firmware_version(amdgpu_device_handle dev, unsigned fw_type,
949 unsigned ip_instance, unsigned index,
950 uint32_t *version, uint32_t *feature);
953 * Query the number of HW IP instances of a certain type.
955 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
956 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
957 * \param count - \c [out] Pointer to structure to get information
959 * \return 0 on success\n
960 * <0 - Negative POSIX Error code
962 int amdgpu_query_hw_ip_count(amdgpu_device_handle dev, unsigned type,
966 * Query engine information
968 * This query allows UMD to query information different engines and their
971 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
972 * \param type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
973 * \param ip_instance - \c [in] Index of the IP block of the same type.
974 * \param info - \c [out] Pointer to structure to get information
976 * \return 0 on success\n
977 * <0 - Negative POSIX Error code
979 int amdgpu_query_hw_ip_info(amdgpu_device_handle dev, unsigned type,
980 unsigned ip_instance,
981 struct drm_amdgpu_info_hw_ip *info);
984 * Query heap information
986 * This query allows UMD to query potentially available memory resources and
987 * adjust their logic if necessary.
989 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
990 * \param heap - \c [in] Heap type
991 * \param info - \c [in] Pointer to structure to get needed information
993 * \return 0 on success\n
994 * <0 - Negative POSIX Error code
997 int amdgpu_query_heap_info(amdgpu_device_handle dev, uint32_t heap,
998 uint32_t flags, struct amdgpu_heap_info *info);
1001 * Get the CRTC ID from the mode object ID
1003 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1004 * \param id - \c [in] Mode object ID
1005 * \param result - \c [in] Pointer to the CRTC ID
1007 * \return 0 on success\n
1008 * <0 - Negative POSIX Error code
1011 int amdgpu_query_crtc_from_id(amdgpu_device_handle dev, unsigned id,
1015 * Query GPU H/w Info
1017 * Query hardware specific information
1019 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1020 * \param heap - \c [in] Heap type
1021 * \param info - \c [in] Pointer to structure to get needed information
1023 * \return 0 on success\n
1024 * <0 - Negative POSIX Error code
1027 int amdgpu_query_gpu_info(amdgpu_device_handle dev,
1028 struct amdgpu_gpu_info *info);
1031 * Query hardware or driver information.
1033 * The return size is query-specific and depends on the "info_id" parameter.
1034 * No more than "size" bytes is returned.
1036 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1037 * \param info_id - \c [in] AMDGPU_INFO_*
1038 * \param size - \c [in] Size of the returned value.
1039 * \param value - \c [out] Pointer to the return value.
1041 * \return 0 on success\n
1042 * <0 - Negative POSIX error code
1045 int amdgpu_query_info(amdgpu_device_handle dev, unsigned info_id,
1046 unsigned size, void *value);
1049 * Query information about GDS
1051 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize()
1052 * \param gds_info - \c [out] Pointer to structure to get GDS information
1054 * \return 0 on success\n
1055 * <0 - Negative POSIX Error code
1058 int amdgpu_query_gds_info(amdgpu_device_handle dev,
1059 struct amdgpu_gds_resource_info *gds_info);
1062 * Read a set of consecutive memory-mapped registers.
1063 * Not all registers are allowed to be read by userspace.
1065 * \param dev - \c [in] Device handle. See #amdgpu_device_initialize(
1066 * \param dword_offset - \c [in] Register offset in dwords
1067 * \param count - \c [in] The number of registers to read starting
1069 * \param instance - \c [in] GRBM_GFX_INDEX selector. It may have other
1070 * uses. Set it to 0xffffffff if unsure.
1071 * \param flags - \c [in] Flags with additional information.
1072 * \param values - \c [out] The pointer to return values.
1074 * \return 0 on success\n
1075 * <0 - Negative POSIX error code
1078 int amdgpu_read_mm_registers(amdgpu_device_handle dev, unsigned dword_offset,
1079 unsigned count, uint32_t instance, uint32_t flags,
1083 * Flag to request VA address range in the 32bit address space
1085 #define AMDGPU_VA_RANGE_32_BIT 0x1
1088 * Allocate virtual address range
1090 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1091 * \param va_range_type - \c [in] Type of MC va range from which to allocate
1092 * \param size - \c [in] Size of range. Size must be correctly* aligned.
1093 * It is client responsibility to correctly aligned size based on the future
1094 * usage of allocated range.
1095 * \param va_base_alignment - \c [in] Overwrite base address alignment
1096 * requirement for GPU VM MC virtual
1097 * address assignment. Must be multiple of size alignments received as
1098 * 'amdgpu_buffer_size_alignments'.
1099 * If 0 use the default one.
1100 * \param va_base_required - \c [in] Specified required va base address.
1101 * If 0 then library choose available one.
1102 * If !0 value will be passed and those value already "in use" then
1103 * corresponding error status will be returned.
1104 * \param va_base_allocated - \c [out] On return: Allocated VA base to be used
1106 * \param va_range_handle - \c [out] On return: Handle assigned to allocation
1107 * \param flags - \c [in] flags for special VA range
1109 * \return 0 on success\n
1110 * >0 - AMD specific error code\n
1111 * <0 - Negative POSIX Error code
1114 * It is client responsibility to correctly handle VA assignments and usage.
1115 * Neither kernel driver nor libdrm_amdpgu are able to prevent and
1116 * detect wrong va assignemnt.
1118 * It is client responsibility to correctly handle multi-GPU cases and to pass
1119 * the corresponding arrays of all devices handles where corresponding VA will
1123 int amdgpu_va_range_alloc(amdgpu_device_handle dev,
1124 enum amdgpu_gpu_va_range va_range_type,
1126 uint64_t va_base_alignment,
1127 uint64_t va_base_required,
1128 uint64_t *va_base_allocated,
1129 amdgpu_va_handle *va_range_handle,
1133 * Free previously allocated virtual address range
1136 * \param va_range_handle - \c [in] Handle assigned to VA allocation
1138 * \return 0 on success\n
1139 * >0 - AMD specific error code\n
1140 * <0 - Negative POSIX Error code
1143 int amdgpu_va_range_free(amdgpu_va_handle va_range_handle);
1146 * Query virtual address range
1148 * UMD can query GPU VM range supported by each device
1149 * to initialize its own VAM accordingly.
1151 * \param dev - [in] Device handle. See #amdgpu_device_initialize()
1152 * \param type - \c [in] Type of virtual address range
1153 * \param offset - \c [out] Start offset of virtual address range
1154 * \param size - \c [out] Size of virtual address range
1156 * \return 0 on success\n
1157 * <0 - Negative POSIX Error code
1161 int amdgpu_va_range_query(amdgpu_device_handle dev,
1162 enum amdgpu_gpu_va_range type,
1167 * VA mapping/unmapping for the buffer object
1169 * \param bo - \c [in] BO handle
1170 * \param offset - \c [in] Start offset to map
1171 * \param size - \c [in] Size to map
1172 * \param addr - \c [in] Start virtual address.
1173 * \param flags - \c [in] Supported flags for mapping/unmapping
1174 * \param ops - \c [in] AMDGPU_VA_OP_MAP or AMDGPU_VA_OP_UNMAP
1176 * \return 0 on success\n
1177 * <0 - Negative POSIX Error code
1181 int amdgpu_bo_va_op(amdgpu_bo_handle bo,
1191 * \param sem - \c [out] semaphore handle
1193 * \return 0 on success\n
1194 * <0 - Negative POSIX Error code
1197 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem);
1202 * \param context - \c [in] GPU Context
1203 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1204 * \param ip_instance - \c [in] Index of the IP block of the same type
1205 * \param ring - \c [in] Specify ring index of the IP
1206 * \param sem - \c [in] semaphore handle
1208 * \return 0 on success\n
1209 * <0 - Negative POSIX Error code
1212 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
1214 uint32_t ip_instance,
1216 amdgpu_semaphore_handle sem);
1221 * \param context - \c [in] GPU Context
1222 * \param ip_type - \c [in] Hardware IP block type = AMDGPU_HW_IP_*
1223 * \param ip_instance - \c [in] Index of the IP block of the same type
1224 * \param ring - \c [in] Specify ring index of the IP
1225 * \param sem - \c [in] semaphore handle
1227 * \return 0 on success\n
1228 * <0 - Negative POSIX Error code
1231 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
1233 uint32_t ip_instance,
1235 amdgpu_semaphore_handle sem);
1240 * \param sem - \c [in] semaphore handle
1242 * \return 0 on success\n
1243 * <0 - Negative POSIX Error code
1246 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem);
1248 #endif /* #ifdef _AMDGPU_H_ */