amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22 */
  23 #include <stdlib.h>
  24 #include <stdio.h>
  25 #include <string.h>
  26 #include <errno.h>
  27 #include <pthread.h>
  28 #include <sched.h>
  29 #include <sys/ioctl.h>
  30
  31 #include "xf86drm.h"
  32 #include "amdgpu_drm.h"
  33 #include "amdgpu_internal.h"
  34
  35 /**
  36  * Create command submission context
  37  *
  38  * \param   dev - \c [in] amdgpu device handle
  39  * \param   context - \c [out] amdgpu context handle
  40  *
  41  * \return  0 on success otherwise POSIX Error code
  42 */
  43 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
  44                          amdgpu_context_handle *context)
  45 {
  46         struct amdgpu_bo_alloc_request alloc_buffer = {};
  47         struct amdgpu_bo_alloc_result info = {};
  48         struct amdgpu_context *gpu_context;
  49         union drm_amdgpu_ctx args;
  50         int r;
  51
  52         if (NULL == dev)
  53                 return -EINVAL;
  54         if (NULL == context)
  55                 return -EINVAL;
  56
  57         gpu_context = calloc(1, sizeof(struct amdgpu_context));
  58         if (NULL == gpu_context)
  59                 return -ENOMEM;
  60
  61         gpu_context->dev = dev;
  62
  63         r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
  64         if (r)
  65                 goto error_mutex;
  66
  67         /* Create the fence BO */
  68         alloc_buffer.alloc_size = 4 * 1024;
  69         alloc_buffer.phys_alignment = 4 * 1024;
  70         alloc_buffer.preferred_heap = AMDGPU_GEM_DOMAIN_GTT;
  71
  72         r = amdgpu_bo_alloc(dev, &alloc_buffer, &info);
  73         if (r)
  74                 goto error_fence_alloc;
  75         gpu_context->fence_bo = info.buf_handle;
  76
  77         r = amdgpu_bo_cpu_map(gpu_context->fence_bo, &gpu_context->fence_cpu);
  78         if (r)
  79                 goto error_fence_map;
  80
  81         /* Create the context */
  82         memset(&args, 0, sizeof(args));
  83         args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
  84         r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
  85         if (r)
  86                 goto error_kernel;
  87
  88         gpu_context->id = args.out.alloc.ctx_id;
  89         *context = (amdgpu_context_handle)gpu_context;
  90
  91         return 0;
  92
  93 error_kernel:
  94         amdgpu_bo_cpu_unmap(gpu_context->fence_bo);
  95
  96 error_fence_map:
  97         amdgpu_bo_free(gpu_context->fence_bo);
  98
  99 error_fence_alloc:
 100         pthread_mutex_destroy(&gpu_context->sequence_mutex);
 101
 102 error_mutex:
 103         free(gpu_context);
 104         return r;
 105 }
 106
 107 /**
 108  * Release command submission context
 109  *
 110  * \param   dev - \c [in] amdgpu device handle
 111  * \param   context - \c [in] amdgpu context handle
 112  *
 113  * \return  0 on success otherwise POSIX Error code
 114 */
 115 int amdgpu_cs_ctx_free(amdgpu_context_handle context)
 116 {
 117         union drm_amdgpu_ctx args;
 118         int r;
 119
 120         if (NULL == context)
 121                 return -EINVAL;
 122
 123         r = amdgpu_bo_cpu_unmap(context->fence_bo);
 124         if (r)
 125                 return r;
 126
 127         r = amdgpu_bo_free(context->fence_bo);
 128         if (r)
 129                 return r;
 130
 131         pthread_mutex_destroy(&context->sequence_mutex);
 132
 133         /* now deal with kernel side */
 134         memset(&args, 0, sizeof(args));
 135         args.in.op = AMDGPU_CTX_OP_FREE_CTX;
 136         args.in.ctx_id = context->id;
 137         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 138                                 &args, sizeof(args));
 139
 140         free(context);
 141
 142         return r;
 143 }
 144
 145 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
 146                                 uint32_t *state, uint32_t *hangs)
 147 {
 148         union drm_amdgpu_ctx args;
 149         int r;
 150
 151         if (!context)
 152                 return -EINVAL;
 153
 154         memset(&args, 0, sizeof(args));
 155         args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
 156         args.in.ctx_id = context->id;
 157         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 158                                 &args, sizeof(args));
 159         if (!r) {
 160                 *state = args.out.state.reset_status;
 161                 *hangs = args.out.state.hangs;
 162         }
 163         return r;
 164 }
 165
 166 static uint32_t amdgpu_cs_fence_index(unsigned ip, unsigned ring)
 167 {
 168         return ip * AMDGPU_CS_MAX_RINGS + ring;
 169 }
 170
 171 /**
 172  * Submit command to kernel DRM
 173  * \param   dev - \c [in]  Device handle
 174  * \param   context - \c [in]  GPU Context
 175  * \param   ibs_request - \c [in]  Pointer to submission requests
 176  * \param   fence - \c [out] return fence for this submission
 177  *
 178  * \return  0 on success otherwise POSIX Error code
 179  * \sa amdgpu_cs_submit()
 180 */
 181 static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 182                                 struct amdgpu_cs_request *ibs_request,
 183                                 uint64_t *fence)
 184 {
 185         union drm_amdgpu_cs cs;
 186         uint64_t *chunk_array;
 187         struct drm_amdgpu_cs_chunk *chunks;
 188         struct drm_amdgpu_cs_chunk_data *chunk_data;
 189         struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
 190         uint32_t i, size;
 191         int r = 0;
 192
 193         if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
 194                 return -EINVAL;
 195         if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
 196                 return -EINVAL;
 197         if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT)
 198                 return -EINVAL;
 199
 200         size = ibs_request->number_of_ibs + 2;
 201
 202         chunk_array = alloca(sizeof(uint64_t) * size);
 203         chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
 204
 205         size = ibs_request->number_of_ibs + 1;
 206         chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
 207
 208         memset(&cs, 0, sizeof(cs));
 209         cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
 210         cs.in.ctx_id = context->id;
 211         if (ibs_request->resources)
 212                 cs.in.bo_list_handle = ibs_request->resources->handle;
 213         cs.in.num_chunks = ibs_request->number_of_ibs;
 214         /* IB chunks */
 215         for (i = 0; i < ibs_request->number_of_ibs; i++) {
 216                 struct amdgpu_cs_ib_info *ib;
 217                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 218                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
 219                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
 220                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 221
 222                 ib = &ibs_request->ibs[i];
 223
 224                 chunk_data[i].ib_data._pad = 0;
 225                 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
 226                 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
 227                 chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
 228                 chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
 229                 chunk_data[i].ib_data.ring = ibs_request->ring;
 230                 chunk_data[i].ib_data.flags = ib->flags;
 231         }
 232
 233         pthread_mutex_lock(&context->sequence_mutex);
 234
 235         if (ibs_request->ip_type != AMDGPU_HW_IP_UVD &&
 236             ibs_request->ip_type != AMDGPU_HW_IP_VCE) {
 237                 i = cs.in.num_chunks++;
 238
 239                 /* fence chunk */
 240                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 241                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
 242                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
 243                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 244
 245                 /* fence bo handle */
 246                 chunk_data[i].fence_data.handle = context->fence_bo->handle;
 247                 /* offset */
 248                 chunk_data[i].fence_data.offset = amdgpu_cs_fence_index(
 249                         ibs_request->ip_type, ibs_request->ring);
 250                 chunk_data[i].fence_data.offset *= sizeof(uint64_t);
 251         }
 252
 253         if (ibs_request->number_of_dependencies) {
 254                 dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) *
 255                         ibs_request->number_of_dependencies);
 256                 if (!dependencies) {
 257                         r = -ENOMEM;
 258                         goto error_unlock;
 259                 }
 260
 261                 for (i = 0; i < ibs_request->number_of_dependencies; ++i) {
 262                         struct amdgpu_cs_dep_info *info = &ibs_request->dependencies[i];
 263                         struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i];
 264                         dep->ip_type = info->ip_type;
 265                         dep->ip_instance = info->ip_instance;
 266                         dep->ring = info->ring;
 267                         dep->ctx_id = info->context->id;
 268                         dep->handle = info->fence;
 269                 }
 270
 271                 i = cs.in.num_chunks++;
 272
 273                 /* dependencies chunk */
 274                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 275                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
 276                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
 277                         * ibs_request->number_of_dependencies;
 278                 chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies;
 279         }
 280
 281         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
 282                                 &cs, sizeof(cs));
 283         if (r)
 284                 goto error_unlock;
 285
 286         *fence = cs.out.handle;
 287
 288 error_unlock:
 289         pthread_mutex_unlock(&context->sequence_mutex);
 290         free(dependencies);
 291         return r;
 292 }
 293
 294 int amdgpu_cs_submit(amdgpu_context_handle context,
 295                      uint64_t flags,
 296                      struct amdgpu_cs_request *ibs_request,
 297                      uint32_t number_of_requests,
 298                      uint64_t *fences)
 299 {
 300         uint32_t i;
 301         int r;
 302
 303         if (NULL == context)
 304                 return -EINVAL;
 305         if (NULL == ibs_request)
 306                 return -EINVAL;
 307         if (NULL == fences)
 308                 return -EINVAL;
 309
 310         r = 0;
 311         for (i = 0; i < number_of_requests; i++) {
 312                 r = amdgpu_cs_submit_one(context, ibs_request, fences);
 313                 if (r)
 314                         break;
 315                 fences++;
 316                 ibs_request++;
 317         }
 318
 319         return r;
 320 }
 321
 322 /**
 323  * Calculate absolute timeout.
 324  *
 325  * \param   timeout - \c [in] timeout in nanoseconds.
 326  *
 327  * \return  absolute timeout in nanoseconds
 328 */
 329 uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
 330 {
 331         int r;
 332
 333         if (timeout != AMDGPU_TIMEOUT_INFINITE) {
 334                 struct timespec current;
 335                 r = clock_gettime(CLOCK_MONOTONIC, &current);
 336                 if (r)
 337                         return r;
 338
 339                 timeout += ((uint64_t)current.tv_sec) * 1000000000ull;
 340                 timeout += current.tv_nsec;
 341         }
 342         return timeout;
 343 }
 344
 345 static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
 346                                 unsigned ip,
 347                                 unsigned ip_instance,
 348                                 uint32_t ring,
 349                                 uint64_t handle,
 350                                 uint64_t timeout_ns,
 351                                 uint64_t flags,
 352                                 bool *busy)
 353 {
 354         amdgpu_device_handle dev = context->dev;
 355         union drm_amdgpu_wait_cs args;
 356         int r;
 357
 358         memset(&args, 0, sizeof(args));
 359         args.in.handle = handle;
 360         args.in.ip_type = ip;
 361         args.in.ip_instance = ip_instance;
 362         args.in.ring = ring;
 363         args.in.ctx_id = context->id;
 364
 365         if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE)
 366                 args.in.timeout = timeout_ns;
 367         else
 368                 args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
 369
 370         /* Handle errors manually here because of timeout */
 371         r = ioctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
 372         if (r == -1 && (errno == EINTR || errno == EAGAIN)) {
 373                 *busy = true;
 374                 return 0;
 375         } else if (r)
 376                 return -errno;
 377
 378         *busy = args.out.status;
 379         return 0;
 380 }
 381
 382 int amdgpu_cs_query_fence_status(struct amdgpu_cs_query_fence *fence,
 383                                  uint32_t *expired)
 384 {
 385         amdgpu_context_handle context;
 386         uint64_t *expired_fence;
 387         unsigned ip_type, ip_instance;
 388         uint32_t ring;
 389         bool busy = true;
 390         int r;
 391
 392         if (NULL == fence)
 393                 return -EINVAL;
 394         if (NULL == expired)
 395                 return -EINVAL;
 396         if (NULL == fence->context)
 397                 return -EINVAL;
 398         if (fence->ip_type >= AMDGPU_HW_IP_NUM)
 399                 return -EINVAL;
 400         if (fence->ring >= AMDGPU_CS_MAX_RINGS)
 401                 return -EINVAL;
 402
 403         context = fence->context;
 404         ip_type = fence->ip_type;
 405         ip_instance = fence->ip_instance;
 406         ring = fence->ring;
 407         expired_fence = &context->expired_fences[ip_type][ip_instance][ring];
 408         *expired = false;
 409
 410         pthread_mutex_lock(&context->sequence_mutex);
 411         if (fence->fence <= *expired_fence) {
 412                 /* This fence value is expired already. */
 413                 pthread_mutex_unlock(&context->sequence_mutex);
 414                 *expired = true;
 415                 return 0;
 416         }
 417
 418         /* Check the user fence only if the IP supports user fences. */
 419         if (fence->ip_type != AMDGPU_HW_IP_UVD &&
 420             fence->ip_type != AMDGPU_HW_IP_VCE) {
 421                 uint64_t *signaled_fence = context->fence_cpu;
 422                 signaled_fence += amdgpu_cs_fence_index(ip_type, ring);
 423
 424                 if (fence->fence <= *signaled_fence) {
 425                         /* This fence value is signaled already. */
 426                         *expired_fence = *signaled_fence;
 427                         pthread_mutex_unlock(&context->sequence_mutex);
 428                         *expired = true;
 429                         return 0;
 430                 }
 431
 432                 /* Checking the user fence is enough. */
 433                 if (fence->timeout_ns == 0) {
 434                         pthread_mutex_unlock(&context->sequence_mutex);
 435                         return 0;
 436                 }
 437         }
 438
 439         pthread_mutex_unlock(&context->sequence_mutex);
 440
 441         r = amdgpu_ioctl_wait_cs(context, ip_type, ip_instance, ring,
 442                                  fence->fence, fence->timeout_ns,
 443                                  fence->flags, &busy);
 444         if (!r && !busy) {
 445                 *expired = true;
 446                 pthread_mutex_lock(&context->sequence_mutex);
 447                 /* The thread doesn't hold sequence_mutex. Other thread could
 448                    update *expired_fence already. Check whether there is a
 449                    newerly expired fence. */
 450                 if (fence->fence > *expired_fence)
 451                         *expired_fence = fence->fence;
 452                 pthread_mutex_unlock(&context->sequence_mutex);
 453         }
 454
 455         return r;
 456 }
 457