amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #ifdef HAVE_CONFIG_H
  25 #include "config.h"
  26 #endif
  27
  28 #include <stdlib.h>
  29 #include <stdio.h>
  30 #include <string.h>
  31 #include <errno.h>
  32 #include <pthread.h>
  33 #include <sched.h>
  34 #include <sys/ioctl.h>
  35 #ifdef HAVE_ALLOCA_H
  36 # include <alloca.h>
  37 #endif
  38
  39 #include "xf86drm.h"
  40 #include "amdgpu_drm.h"
  41 #include "amdgpu_internal.h"
  42
  43 static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem);
  44 static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem);
  45
  46 /**
  47  * Create command submission context
  48  *
  49  * \param   dev - \c [in] amdgpu device handle
  50  * \param   context - \c [out] amdgpu context handle
  51  *
  52  * \return  0 on success otherwise POSIX Error code
  53 */
  54 int amdgpu_cs_ctx_create(amdgpu_device_handle dev,
  55                          amdgpu_context_handle *context)
  56 {
  57         struct amdgpu_context *gpu_context;
  58         union drm_amdgpu_ctx args;
  59         int i, j, k;
  60         int r;
  61
  62         if (!dev || !context)
  63                 return -EINVAL;
  64
  65         gpu_context = calloc(1, sizeof(struct amdgpu_context));
  66         if (!gpu_context)
  67                 return -ENOMEM;
  68
  69         gpu_context->dev = dev;
  70
  71         r = pthread_mutex_init(&gpu_context->sequence_mutex, NULL);
  72         if (r)
  73                 goto error;
  74
  75         /* Create the context */
  76         memset(&args, 0, sizeof(args));
  77         args.in.op = AMDGPU_CTX_OP_ALLOC_CTX;
  78         r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CTX, &args, sizeof(args));
  79         if (r)
  80                 goto error;
  81
  82         gpu_context->id = args.out.alloc.ctx_id;
  83         for (i = 0; i < AMDGPU_HW_IP_NUM; i++)
  84                 for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++)
  85                         for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++)
  86                                 list_inithead(&gpu_context->sem_list[i][j][k]);
  87         *context = (amdgpu_context_handle)gpu_context;
  88
  89         return 0;
  90
  91 error:
  92         pthread_mutex_destroy(&gpu_context->sequence_mutex);
  93         free(gpu_context);
  94         return r;
  95 }
  96
  97 /**
  98  * Release command submission context
  99  *
 100  * \param   dev - \c [in] amdgpu device handle
 101  * \param   context - \c [in] amdgpu context handle
 102  *
 103  * \return  0 on success otherwise POSIX Error code
 104 */
 105 int amdgpu_cs_ctx_free(amdgpu_context_handle context)
 106 {
 107         union drm_amdgpu_ctx args;
 108         int i, j, k;
 109         int r;
 110
 111         if (!context)
 112                 return -EINVAL;
 113
 114         pthread_mutex_destroy(&context->sequence_mutex);
 115
 116         /* now deal with kernel side */
 117         memset(&args, 0, sizeof(args));
 118         args.in.op = AMDGPU_CTX_OP_FREE_CTX;
 119         args.in.ctx_id = context->id;
 120         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 121                                 &args, sizeof(args));
 122         for (i = 0; i < AMDGPU_HW_IP_NUM; i++) {
 123                 for (j = 0; j < AMDGPU_HW_IP_INSTANCE_MAX_COUNT; j++) {
 124                         for (k = 0; k < AMDGPU_CS_MAX_RINGS; k++) {
 125                                 amdgpu_semaphore_handle sem;
 126                                 LIST_FOR_EACH_ENTRY(sem, &context->sem_list[i][j][k], list) {
 127                                         list_del(&sem->list);
 128                                         amdgpu_cs_reset_sem(sem);
 129                                         amdgpu_cs_unreference_sem(sem);
 130                                 }
 131                         }
 132                 }
 133         }
 134         free(context);
 135
 136         return r;
 137 }
 138
 139 int amdgpu_cs_query_reset_state(amdgpu_context_handle context,
 140                                 uint32_t *state, uint32_t *hangs)
 141 {
 142         union drm_amdgpu_ctx args;
 143         int r;
 144
 145         if (!context)
 146                 return -EINVAL;
 147
 148         memset(&args, 0, sizeof(args));
 149         args.in.op = AMDGPU_CTX_OP_QUERY_STATE;
 150         args.in.ctx_id = context->id;
 151         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CTX,
 152                                 &args, sizeof(args));
 153         if (!r) {
 154                 *state = args.out.state.reset_status;
 155                 *hangs = args.out.state.hangs;
 156         }
 157         return r;
 158 }
 159
 160 /**
 161  * Submit command to kernel DRM
 162  * \param   dev - \c [in]  Device handle
 163  * \param   context - \c [in]  GPU Context
 164  * \param   ibs_request - \c [in]  Pointer to submission requests
 165  * \param   fence - \c [out] return fence for this submission
 166  *
 167  * \return  0 on success otherwise POSIX Error code
 168  * \sa amdgpu_cs_submit()
 169 */
 170 static int amdgpu_cs_submit_one(amdgpu_context_handle context,
 171                                 struct amdgpu_cs_request *ibs_request)
 172 {
 173         union drm_amdgpu_cs cs;
 174         uint64_t *chunk_array;
 175         struct drm_amdgpu_cs_chunk *chunks;
 176         struct drm_amdgpu_cs_chunk_data *chunk_data;
 177         struct drm_amdgpu_cs_chunk_dep *dependencies = NULL;
 178         struct drm_amdgpu_cs_chunk_dep *sem_dependencies = NULL;
 179         struct list_head *sem_list;
 180         amdgpu_semaphore_handle sem, tmp;
 181         uint32_t i, size, sem_count = 0;
 182         bool user_fence;
 183         int r = 0;
 184
 185         if (ibs_request->ip_type >= AMDGPU_HW_IP_NUM)
 186                 return -EINVAL;
 187         if (ibs_request->ring >= AMDGPU_CS_MAX_RINGS)
 188                 return -EINVAL;
 189         if (ibs_request->number_of_ibs > AMDGPU_CS_MAX_IBS_PER_SUBMIT)
 190                 return -EINVAL;
 191         if (ibs_request->number_of_ibs == 0) {
 192                 ibs_request->seq_no = AMDGPU_NULL_SUBMIT_SEQ;
 193                 return 0;
 194         }
 195         user_fence = (ibs_request->fence_info.handle != NULL);
 196
 197         size = ibs_request->number_of_ibs + (user_fence ? 2 : 1) + 1;
 198
 199         chunk_array = alloca(sizeof(uint64_t) * size);
 200         chunks = alloca(sizeof(struct drm_amdgpu_cs_chunk) * size);
 201
 202         size = ibs_request->number_of_ibs + (user_fence ? 1 : 0);
 203
 204         chunk_data = alloca(sizeof(struct drm_amdgpu_cs_chunk_data) * size);
 205
 206         memset(&cs, 0, sizeof(cs));
 207         cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
 208         cs.in.ctx_id = context->id;
 209         if (ibs_request->resources)
 210                 cs.in.bo_list_handle = ibs_request->resources->handle;
 211         cs.in.num_chunks = ibs_request->number_of_ibs;
 212         /* IB chunks */
 213         for (i = 0; i < ibs_request->number_of_ibs; i++) {
 214                 struct amdgpu_cs_ib_info *ib;
 215                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 216                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_IB;
 217                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
 218                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 219
 220                 ib = &ibs_request->ibs[i];
 221
 222                 chunk_data[i].ib_data._pad = 0;
 223                 chunk_data[i].ib_data.va_start = ib->ib_mc_address;
 224                 chunk_data[i].ib_data.ib_bytes = ib->size * 4;
 225                 chunk_data[i].ib_data.ip_type = ibs_request->ip_type;
 226                 chunk_data[i].ib_data.ip_instance = ibs_request->ip_instance;
 227                 chunk_data[i].ib_data.ring = ibs_request->ring;
 228                 chunk_data[i].ib_data.flags = ib->flags;
 229         }
 230
 231         pthread_mutex_lock(&context->sequence_mutex);
 232
 233         if (user_fence) {
 234                 i = cs.in.num_chunks++;
 235
 236                 /* fence chunk */
 237                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 238                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_FENCE;
 239                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_fence) / 4;
 240                 chunks[i].chunk_data = (uint64_t)(uintptr_t)&chunk_data[i];
 241
 242                 /* fence bo handle */
 243                 chunk_data[i].fence_data.handle = ibs_request->fence_info.handle->handle;
 244                 /* offset */
 245                 chunk_data[i].fence_data.offset =
 246                         ibs_request->fence_info.offset * sizeof(uint64_t);
 247         }
 248
 249         if (ibs_request->number_of_dependencies) {
 250                 dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) *
 251                         ibs_request->number_of_dependencies);
 252                 if (!dependencies) {
 253                         r = -ENOMEM;
 254                         goto error_unlock;
 255                 }
 256
 257                 for (i = 0; i < ibs_request->number_of_dependencies; ++i) {
 258                         struct amdgpu_cs_fence *info = &ibs_request->dependencies[i];
 259                         struct drm_amdgpu_cs_chunk_dep *dep = &dependencies[i];
 260                         dep->ip_type = info->ip_type;
 261                         dep->ip_instance = info->ip_instance;
 262                         dep->ring = info->ring;
 263                         dep->ctx_id = info->context->id;
 264                         dep->handle = info->fence;
 265                 }
 266
 267                 i = cs.in.num_chunks++;
 268
 269                 /* dependencies chunk */
 270                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 271                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
 272                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4
 273                         * ibs_request->number_of_dependencies;
 274                 chunks[i].chunk_data = (uint64_t)(uintptr_t)dependencies;
 275         }
 276
 277         sem_list = &context->sem_list[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring];
 278         LIST_FOR_EACH_ENTRY(sem, sem_list, list)
 279                 sem_count++;
 280         if (sem_count) {
 281                 sem_dependencies = malloc(sizeof(struct drm_amdgpu_cs_chunk_dep) * sem_count);
 282                 if (!sem_dependencies) {
 283                         r = -ENOMEM;
 284                         goto error_unlock;
 285                 }
 286                 sem_count = 0;
 287                 LIST_FOR_EACH_ENTRY_SAFE(sem, tmp, sem_list, list) {
 288                         struct amdgpu_cs_fence *info = &sem->signal_fence;
 289                         struct drm_amdgpu_cs_chunk_dep *dep = &sem_dependencies[sem_count++];
 290                         dep->ip_type = info->ip_type;
 291                         dep->ip_instance = info->ip_instance;
 292                         dep->ring = info->ring;
 293                         dep->ctx_id = info->context->id;
 294                         dep->handle = info->fence;
 295
 296                         list_del(&sem->list);
 297                         amdgpu_cs_reset_sem(sem);
 298                         amdgpu_cs_unreference_sem(sem);
 299                 }
 300                 i = cs.in.num_chunks++;
 301
 302                 /* dependencies chunk */
 303                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 304                 chunks[i].chunk_id = AMDGPU_CHUNK_ID_DEPENDENCIES;
 305                 chunks[i].length_dw = sizeof(struct drm_amdgpu_cs_chunk_dep) / 4 * sem_count;
 306                 chunks[i].chunk_data = (uint64_t)(uintptr_t)sem_dependencies;
 307         }
 308
 309         r = drmCommandWriteRead(context->dev->fd, DRM_AMDGPU_CS,
 310                                 &cs, sizeof(cs));
 311         if (r)
 312                 goto error_unlock;
 313
 314         ibs_request->seq_no = cs.out.handle;
 315         context->last_seq[ibs_request->ip_type][ibs_request->ip_instance][ibs_request->ring] = ibs_request->seq_no;
 316 error_unlock:
 317         pthread_mutex_unlock(&context->sequence_mutex);
 318         free(dependencies);
 319         free(sem_dependencies);
 320         return r;
 321 }
 322
 323 int amdgpu_cs_submit(amdgpu_context_handle context,
 324                      uint64_t flags,
 325                      struct amdgpu_cs_request *ibs_request,
 326                      uint32_t number_of_requests)
 327 {
 328         uint32_t i;
 329         int r;
 330
 331         if (!context || !ibs_request)
 332                 return -EINVAL;
 333
 334         r = 0;
 335         for (i = 0; i < number_of_requests; i++) {
 336                 r = amdgpu_cs_submit_one(context, ibs_request);
 337                 if (r)
 338                         break;
 339                 ibs_request++;
 340         }
 341
 342         return r;
 343 }
 344
 345 /**
 346  * Calculate absolute timeout.
 347  *
 348  * \param   timeout - \c [in] timeout in nanoseconds.
 349  *
 350  * \return  absolute timeout in nanoseconds
 351 */
 352 drm_private uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout)
 353 {
 354         int r;
 355
 356         if (timeout != AMDGPU_TIMEOUT_INFINITE) {
 357                 struct timespec current;
 358                 uint64_t current_ns;
 359                 r = clock_gettime(CLOCK_MONOTONIC, &current);
 360                 if (r) {
 361                         fprintf(stderr, "clock_gettime() returned error (%d)!", errno);
 362                         return AMDGPU_TIMEOUT_INFINITE;
 363                 }
 364
 365                 current_ns = ((uint64_t)current.tv_sec) * 1000000000ull;
 366                 current_ns += current.tv_nsec;
 367                 timeout += current_ns;
 368                 if (timeout < current_ns)
 369                         timeout = AMDGPU_TIMEOUT_INFINITE;
 370         }
 371         return timeout;
 372 }
 373
 374 static int amdgpu_ioctl_wait_cs(amdgpu_context_handle context,
 375                                 unsigned ip,
 376                                 unsigned ip_instance,
 377                                 uint32_t ring,
 378                                 uint64_t handle,
 379                                 uint64_t timeout_ns,
 380                                 uint64_t flags,
 381                                 bool *busy)
 382 {
 383         amdgpu_device_handle dev = context->dev;
 384         union drm_amdgpu_wait_cs args;
 385         int r;
 386
 387         memset(&args, 0, sizeof(args));
 388         args.in.handle = handle;
 389         args.in.ip_type = ip;
 390         args.in.ip_instance = ip_instance;
 391         args.in.ring = ring;
 392         args.in.ctx_id = context->id;
 393
 394         if (flags & AMDGPU_QUERY_FENCE_TIMEOUT_IS_ABSOLUTE)
 395                 args.in.timeout = timeout_ns;
 396         else
 397                 args.in.timeout = amdgpu_cs_calculate_timeout(timeout_ns);
 398
 399         r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_CS, &args);
 400         if (r)
 401                 return -errno;
 402
 403         *busy = args.out.status;
 404         return 0;
 405 }
 406
 407 int amdgpu_cs_query_fence_status(struct amdgpu_cs_fence *fence,
 408                                  uint64_t timeout_ns,
 409                                  uint64_t flags,
 410                                  uint32_t *expired)
 411 {
 412         bool busy = true;
 413         int r;
 414
 415         if (!fence || !expired || !fence->context)
 416                 return -EINVAL;
 417         if (fence->ip_type >= AMDGPU_HW_IP_NUM)
 418                 return -EINVAL;
 419         if (fence->ring >= AMDGPU_CS_MAX_RINGS)
 420                 return -EINVAL;
 421         if (fence->fence == AMDGPU_NULL_SUBMIT_SEQ) {
 422                 *expired = true;
 423                 return 0;
 424         }
 425
 426         *expired = false;
 427
 428         r = amdgpu_ioctl_wait_cs(fence->context, fence->ip_type,
 429                                 fence->ip_instance, fence->ring,
 430                                 fence->fence, timeout_ns, flags, &busy);
 431
 432         if (!r && !busy)
 433                 *expired = true;
 434
 435         return r;
 436 }
 437
 438 static int amdgpu_ioctl_wait_fences(struct amdgpu_cs_fence *fences,
 439                                     uint32_t fence_count,
 440                                     bool wait_all,
 441                                     uint64_t timeout_ns,
 442                                     uint32_t *status,
 443                                     uint32_t *first)
 444 {
 445         struct drm_amdgpu_fence *drm_fences;
 446         amdgpu_device_handle dev = fences[0].context->dev;
 447         union drm_amdgpu_wait_fences args;
 448         int r;
 449         uint32_t i;
 450
 451         drm_fences = alloca(sizeof(struct drm_amdgpu_fence) * fence_count);
 452         for (i = 0; i < fence_count; i++) {
 453                 drm_fences[i].ctx_id = fences[i].context->id;
 454                 drm_fences[i].ip_type = fences[i].ip_type;
 455                 drm_fences[i].ip_instance = fences[i].ip_instance;
 456                 drm_fences[i].ring = fences[i].ring;
 457                 drm_fences[i].seq_no = fences[i].fence;
 458         }
 459
 460         memset(&args, 0, sizeof(args));
 461         args.in.fences = (uint64_t)(uintptr_t)drm_fences;
 462         args.in.fence_count = fence_count;
 463         args.in.wait_all = wait_all;
 464         args.in.timeout_ns = amdgpu_cs_calculate_timeout(timeout_ns);
 465
 466         r = drmIoctl(dev->fd, DRM_IOCTL_AMDGPU_WAIT_FENCES, &args);
 467         if (r)
 468                 return -errno;
 469
 470         *status = args.out.status;
 471
 472         if (first)
 473                 *first = args.out.first_signaled;
 474
 475         return 0;
 476 }
 477
 478 int amdgpu_cs_wait_fences(struct amdgpu_cs_fence *fences,
 479                           uint32_t fence_count,
 480                           bool wait_all,
 481                           uint64_t timeout_ns,
 482                           uint32_t *status,
 483                           uint32_t *first)
 484 {
 485         uint32_t i;
 486
 487         /* Sanity check */
 488         if (!fences || !status || !fence_count)
 489                 return -EINVAL;
 490
 491         for (i = 0; i < fence_count; i++) {
 492                 if (NULL == fences[i].context)
 493                         return -EINVAL;
 494                 if (fences[i].ip_type >= AMDGPU_HW_IP_NUM)
 495                         return -EINVAL;
 496                 if (fences[i].ring >= AMDGPU_CS_MAX_RINGS)
 497                         return -EINVAL;
 498         }
 499
 500         *status = 0;
 501
 502         return amdgpu_ioctl_wait_fences(fences, fence_count, wait_all,
 503                                         timeout_ns, status, first);
 504 }
 505
 506 int amdgpu_cs_create_semaphore(amdgpu_semaphore_handle *sem)
 507 {
 508         struct amdgpu_semaphore *gpu_semaphore;
 509
 510         if (!sem)
 511                 return -EINVAL;
 512
 513         gpu_semaphore = calloc(1, sizeof(struct amdgpu_semaphore));
 514         if (!gpu_semaphore)
 515                 return -ENOMEM;
 516
 517         atomic_set(&gpu_semaphore->refcount, 1);
 518         *sem = gpu_semaphore;
 519
 520         return 0;
 521 }
 522
 523 int amdgpu_cs_signal_semaphore(amdgpu_context_handle ctx,
 524                                uint32_t ip_type,
 525                                uint32_t ip_instance,
 526                                uint32_t ring,
 527                                amdgpu_semaphore_handle sem)
 528 {
 529         if (!ctx || !sem)
 530                 return -EINVAL;
 531         if (ip_type >= AMDGPU_HW_IP_NUM)
 532                 return -EINVAL;
 533         if (ring >= AMDGPU_CS_MAX_RINGS)
 534                 return -EINVAL;
 535         /* sem has been signaled */
 536         if (sem->signal_fence.context)
 537                 return -EINVAL;
 538         pthread_mutex_lock(&ctx->sequence_mutex);
 539         sem->signal_fence.context = ctx;
 540         sem->signal_fence.ip_type = ip_type;
 541         sem->signal_fence.ip_instance = ip_instance;
 542         sem->signal_fence.ring = ring;
 543         sem->signal_fence.fence = ctx->last_seq[ip_type][ip_instance][ring];
 544         update_references(NULL, &sem->refcount);
 545         pthread_mutex_unlock(&ctx->sequence_mutex);
 546         return 0;
 547 }
 548
 549 int amdgpu_cs_wait_semaphore(amdgpu_context_handle ctx,
 550                              uint32_t ip_type,
 551                              uint32_t ip_instance,
 552                              uint32_t ring,
 553                              amdgpu_semaphore_handle sem)
 554 {
 555         if (!ctx || !sem)
 556                 return -EINVAL;
 557         if (ip_type >= AMDGPU_HW_IP_NUM)
 558                 return -EINVAL;
 559         if (ring >= AMDGPU_CS_MAX_RINGS)
 560                 return -EINVAL;
 561         /* must signal first */
 562         if (!sem->signal_fence.context)
 563                 return -EINVAL;
 564
 565         pthread_mutex_lock(&ctx->sequence_mutex);
 566         list_add(&sem->list, &ctx->sem_list[ip_type][ip_instance][ring]);
 567         pthread_mutex_unlock(&ctx->sequence_mutex);
 568         return 0;
 569 }
 570
 571 static int amdgpu_cs_reset_sem(amdgpu_semaphore_handle sem)
 572 {
 573         if (!sem || !sem->signal_fence.context)
 574                 return -EINVAL;
 575
 576         sem->signal_fence.context = NULL;;
 577         sem->signal_fence.ip_type = 0;
 578         sem->signal_fence.ip_instance = 0;
 579         sem->signal_fence.ring = 0;
 580         sem->signal_fence.fence = 0;
 581
 582         return 0;
 583 }
 584
 585 static int amdgpu_cs_unreference_sem(amdgpu_semaphore_handle sem)
 586 {
 587         if (!sem)
 588                 return -EINVAL;
 589
 590         if (update_references(&sem->refcount, NULL))
 591                 free(sem);
 592         return 0;
 593 }
 594
 595 int amdgpu_cs_destroy_semaphore(amdgpu_semaphore_handle sem)
 596 {
 597         return amdgpu_cs_unreference_sem(sem);
 598 }
 599
 600 int amdgpu_cs_create_syncobj(amdgpu_device_handle dev,
 601                              uint32_t *handle)
 602 {
 603         if (NULL == dev)
 604                 return -EINVAL;
 605
 606         return drmSyncobjCreate(dev->fd, 0, handle);
 607 }
 608
 609 int amdgpu_cs_destroy_syncobj(amdgpu_device_handle dev,
 610                               uint32_t handle)
 611 {
 612         if (NULL == dev)
 613                 return -EINVAL;
 614
 615         return drmSyncobjDestroy(dev->fd, handle);
 616 }
 617
 618 int amdgpu_cs_export_syncobj(amdgpu_device_handle dev,
 619                              uint32_t handle,
 620                              int *shared_fd)
 621 {
 622         if (NULL == dev)
 623                 return -EINVAL;
 624
 625         return drmSyncobjHandleToFD(dev->fd, handle, shared_fd);
 626 }
 627
 628 int amdgpu_cs_import_syncobj(amdgpu_device_handle dev,
 629                              int shared_fd,
 630                              uint32_t *handle)
 631 {
 632         if (NULL == dev)
 633                 return -EINVAL;
 634
 635         return drmSyncobjFDToHandle(dev->fd, shared_fd, handle);
 636 }
 637
 638 int amdgpu_cs_submit_raw(amdgpu_device_handle dev,
 639                          amdgpu_context_handle context,
 640                          amdgpu_bo_list_handle bo_list_handle,
 641                          int num_chunks,
 642                          struct drm_amdgpu_cs_chunk *chunks,
 643                          uint64_t *seq_no)
 644 {
 645         union drm_amdgpu_cs cs = {0};
 646         uint64_t *chunk_array;
 647         int i, r;
 648         if (num_chunks == 0)
 649                 return -EINVAL;
 650
 651         chunk_array = alloca(sizeof(uint64_t) * num_chunks);
 652         for (i = 0; i < num_chunks; i++)
 653                 chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i];
 654         cs.in.chunks = (uint64_t)(uintptr_t)chunk_array;
 655         cs.in.ctx_id = context->id;
 656         cs.in.bo_list_handle = bo_list_handle ? bo_list_handle->handle : 0;
 657         cs.in.num_chunks = num_chunks;
 658         r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS,
 659                                 &cs, sizeof(cs));
 660         if (r)
 661                 return r;
 662
 663         if (seq_no)
 664                 *seq_no = cs.out.handle;
 665         return 0;
 666 }
 667
 668 void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info,
 669                                         struct drm_amdgpu_cs_chunk_data *data)
 670 {
 671         data->fence_data.handle = fence_info->handle->handle;
 672         data->fence_data.offset = fence_info->offset * sizeof(uint64_t);
 673 }
 674
 675 void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence,
 676                                   struct drm_amdgpu_cs_chunk_dep *dep)
 677 {
 678         dep->ip_type = fence->ip_type;
 679         dep->ip_instance = fence->ip_instance;
 680         dep->ring = fence->ring;
 681         dep->ctx_id = fence->context->id;
 682         dep->handle = fence->fence;
 683 }