amdgpu/amdgpu_device.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 /**
  25  * \file amdgpu_device.c
  26  *
  27  *  Implementation of functions for AMD GPU device
  28  *
  29  */
  30
  31 #ifdef HAVE_CONFIG_H
  32 #include "config.h"
  33 #endif
  34
  35 #include <sys/stat.h>
  36 #include <errno.h>
  37 #include <string.h>
  38 #include <stdio.h>
  39 #include <stdlib.h>
  40 #include <unistd.h>
  41
  42 #include "xf86drm.h"
  43 #include "amdgpu_drm.h"
  44 #include "amdgpu_internal.h"
  45 #include "util_hash_table.h"
  46 #include "util_math.h"
  47 #include "amdgpu_asic_id.h"
  48
  49 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
  50 #define UINT_TO_PTR(x) ((void *)((intptr_t)(x)))
  51
  52 static pthread_mutex_t fd_mutex = PTHREAD_MUTEX_INITIALIZER;
  53 static struct util_hash_table *fd_tab;
  54
  55 static unsigned handle_hash(void *key)
  56 {
  57         return PTR_TO_UINT(key);
  58 }
  59
  60 static int handle_compare(void *key1, void *key2)
  61 {
  62         return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
  63 }
  64
  65 static unsigned fd_hash(void *key)
  66 {
  67         int fd = PTR_TO_UINT(key);
  68         char *name = drmGetPrimaryDeviceNameFromFd(fd);
  69         unsigned result = 0;
  70         char *c;
  71
  72         if (name == NULL)
  73                 return 0;
  74
  75         for (c = name; *c; ++c)
  76                 result += *c;
  77
  78         free(name);
  79
  80         return result;
  81 }
  82
  83 static int fd_compare(void *key1, void *key2)
  84 {
  85         int fd1 = PTR_TO_UINT(key1);
  86         int fd2 = PTR_TO_UINT(key2);
  87         char *name1 = drmGetPrimaryDeviceNameFromFd(fd1);
  88         char *name2 = drmGetPrimaryDeviceNameFromFd(fd2);
  89         int result;
  90
  91         if (name1 == NULL || name2 == NULL) {
  92                 free(name1);
  93                 free(name2);
  94                 return 0;
  95         }
  96
  97         result = strcmp(name1, name2);
  98         free(name1);
  99         free(name2);
 100
 101         return result;
 102 }
 103
 104 /**
 105 * Get the authenticated form fd,
 106 *
 107 * \param   fd   - \c [in]  File descriptor for AMD GPU device
 108 * \param   auth - \c [out] Pointer to output the fd is authenticated or not
 109 *                          A render node fd, output auth = 0
 110 *                          A legacy fd, get the authenticated for compatibility root
 111 *
 112 * \return   0 on success\n
 113 *          >0 - AMD specific error code\n
 114 *          <0 - Negative POSIX Error code
 115 */
 116 static int amdgpu_get_auth(int fd, int *auth)
 117 {
 118         int r = 0;
 119         drm_client_t client = {};
 120
 121         if (drmGetNodeTypeFromFd(fd) == DRM_NODE_RENDER)
 122                 *auth = 0;
 123         else {
 124                 client.idx = 0;
 125                 r = drmIoctl(fd, DRM_IOCTL_GET_CLIENT, &client);
 126                 if (!r)
 127                         *auth = client.auth;
 128         }
 129         return r;
 130 }
 131
 132 static void amdgpu_device_free_internal(amdgpu_device_handle dev)
 133 {
 134         amdgpu_vamgr_deinit(&dev->vamgr_32);
 135         amdgpu_vamgr_deinit(&dev->vamgr);
 136         util_hash_table_destroy(dev->bo_flink_names);
 137         util_hash_table_destroy(dev->bo_handles);
 138         pthread_mutex_destroy(&dev->bo_table_mutex);
 139         util_hash_table_remove(fd_tab, UINT_TO_PTR(dev->fd));
 140         close(dev->fd);
 141         if ((dev->flink_fd >= 0) && (dev->fd != dev->flink_fd))
 142                 close(dev->flink_fd);
 143         free(dev);
 144 }
 145
 146 /**
 147  * Assignment between two amdgpu_device pointers with reference counting.
 148  *
 149  * Usage:
 150  *    struct amdgpu_device *dst = ... , *src = ...;
 151  *
 152  *    dst = src;
 153  *    // No reference counting. Only use this when you need to move
 154  *    // a reference from one pointer to another.
 155  *
 156  *    amdgpu_device_reference(&dst, src);
 157  *    // Reference counters are updated. dst is decremented and src is
 158  *    // incremented. dst is freed if its reference counter is 0.
 159  */
 160 static void amdgpu_device_reference(struct amdgpu_device **dst,
 161                              struct amdgpu_device *src)
 162 {
 163         if (update_references(&(*dst)->refcount, &src->refcount))
 164                 amdgpu_device_free_internal(*dst);
 165         *dst = src;
 166 }
 167
 168 int amdgpu_device_initialize(int fd,
 169                              uint32_t *major_version,
 170                              uint32_t *minor_version,
 171                              amdgpu_device_handle *device_handle)
 172 {
 173         struct amdgpu_device *dev;
 174         drmVersionPtr version;
 175         int r;
 176         int flag_auth = 0;
 177         int flag_authexist=0;
 178         uint32_t accel_working = 0;
 179         uint64_t start, max;
 180
 181         *device_handle = NULL;
 182
 183         pthread_mutex_lock(&fd_mutex);
 184         if (!fd_tab)
 185                 fd_tab = util_hash_table_create(fd_hash, fd_compare);
 186         r = amdgpu_get_auth(fd, &flag_auth);
 187         if (r) {
 188                 pthread_mutex_unlock(&fd_mutex);
 189                 return r;
 190         }
 191         dev = util_hash_table_get(fd_tab, UINT_TO_PTR(fd));
 192         if (dev) {
 193                 r = amdgpu_get_auth(dev->fd, &flag_authexist);
 194                 if (r) {
 195                         pthread_mutex_unlock(&fd_mutex);
 196                         return r;
 197                 }
 198                 if ((flag_auth) && (!flag_authexist)) {
 199                         dev->flink_fd = dup(fd);
 200                 }
 201                 *major_version = dev->major_version;
 202                 *minor_version = dev->minor_version;
 203                 amdgpu_device_reference(device_handle, dev);
 204                 pthread_mutex_unlock(&fd_mutex);
 205                 return 0;
 206         }
 207
 208         dev = calloc(1, sizeof(struct amdgpu_device));
 209         if (!dev) {
 210                 pthread_mutex_unlock(&fd_mutex);
 211                 return -ENOMEM;
 212         }
 213
 214         dev->fd = -1;
 215         dev->flink_fd = -1;
 216
 217         atomic_set(&dev->refcount, 1);
 218
 219         version = drmGetVersion(fd);
 220         if (version->version_major != 3) {
 221                 fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
 222                         "only compatible with 3.x.x.\n",
 223                         __func__,
 224                         version->version_major,
 225                         version->version_minor,
 226                         version->version_patchlevel);
 227                 drmFreeVersion(version);
 228                 r = -EBADF;
 229                 goto cleanup;
 230         }
 231
 232         dev->fd = dup(fd);
 233         dev->flink_fd = dev->fd;
 234         dev->major_version = version->version_major;
 235         dev->minor_version = version->version_minor;
 236         drmFreeVersion(version);
 237
 238         dev->bo_flink_names = util_hash_table_create(handle_hash,
 239                                                      handle_compare);
 240         dev->bo_handles = util_hash_table_create(handle_hash, handle_compare);
 241         pthread_mutex_init(&dev->bo_table_mutex, NULL);
 242
 243         /* Check if acceleration is working. */
 244         r = amdgpu_query_info(dev, AMDGPU_INFO_ACCEL_WORKING, 4, &accel_working);
 245         if (r)
 246                 goto cleanup;
 247         if (!accel_working) {
 248                 r = -EBADF;
 249                 goto cleanup;
 250         }
 251
 252         r = amdgpu_query_gpu_info_init(dev);
 253         if (r)
 254                 goto cleanup;
 255
 256         amdgpu_vamgr_init(&dev->vamgr, dev->dev_info.virtual_address_offset,
 257                           dev->dev_info.virtual_address_max,
 258                           dev->dev_info.virtual_address_alignment);
 259
 260         max = MIN2(dev->dev_info.virtual_address_max, 0xffffffff);
 261         start = amdgpu_vamgr_find_va(&dev->vamgr,
 262                                      max - dev->dev_info.virtual_address_offset,
 263                                      dev->dev_info.virtual_address_alignment, 0);
 264         if (start > 0xffffffff)
 265                 goto free_va; /* shouldn't get here */
 266
 267         amdgpu_vamgr_init(&dev->vamgr_32, start, max,
 268                           dev->dev_info.virtual_address_alignment);
 269
 270         *major_version = dev->major_version;
 271         *minor_version = dev->minor_version;
 272         *device_handle = dev;
 273         util_hash_table_set(fd_tab, UINT_TO_PTR(dev->fd), dev);
 274         pthread_mutex_unlock(&fd_mutex);
 275
 276         return 0;
 277
 278 free_va:
 279         r = -ENOMEM;
 280         amdgpu_vamgr_free_va(&dev->vamgr, start,
 281                              max - dev->dev_info.virtual_address_offset);
 282         amdgpu_vamgr_deinit(&dev->vamgr);
 283
 284 cleanup:
 285         if (dev->fd >= 0)
 286                 close(dev->fd);
 287         free(dev);
 288         pthread_mutex_unlock(&fd_mutex);
 289         return r;
 290 }
 291
 292 int amdgpu_device_deinitialize(amdgpu_device_handle dev)
 293 {
 294         amdgpu_device_reference(&dev, NULL);
 295         return 0;
 296 }
 297
 298 const char *amdgpu_get_marketing_name(amdgpu_device_handle dev)
 299 {
 300         const struct amdgpu_asic_id_table_t *t = amdgpu_asic_id_table;
 301
 302         while (t->did) {
 303                 if ((t->did == dev->info.asic_id) &&
 304                     (t->rid == dev->info.pci_rev_id))
 305                         return t->marketing_name;
 306                 t++;
 307         }
 308
 309         return NULL;
 310 }