2 * Copyright © 2014 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef _AMDGPU_INTERNAL_H_
25 #define _AMDGPU_INTERNAL_H_
33 #include "xf86atomic.h"
35 #include "util_double_list.h"
37 #define AMDGPU_CS_MAX_RINGS 8
38 /* do not use below macro if b is not power of 2 aligned value */
39 #define __round_mask(x, y) ((__typeof__(x))((y)-1))
40 #define ROUND_UP(x, y) ((((x)-1) | __round_mask(x, y))+1)
41 #define ROUND_DOWN(x, y) ((x) & ~__round_mask(x, y))
43 #define AMDGPU_INVALID_VA_ADDRESS 0xffffffffffffffff
45 struct amdgpu_bo_va_hole {
46 struct list_head list;
51 struct amdgpu_bo_va_mgr {
53 /* the start virtual address */
56 struct list_head va_holes;
57 pthread_mutex_t bo_va_mutex;
58 uint32_t va_alignment;
61 struct amdgpu_device {
65 unsigned major_version;
66 unsigned minor_version;
68 /** List of buffer handles. Protected by bo_table_mutex. */
69 struct util_hash_table *bo_handles;
70 /** List of buffer GEM flink names. Protected by bo_table_mutex. */
71 struct util_hash_table *bo_flink_names;
72 /** This protects all hash tables. */
73 pthread_mutex_t bo_table_mutex;
74 struct drm_amdgpu_info_device dev_info;
75 struct amdgpu_gpu_info info;
76 struct amdgpu_bo_va_mgr *vamgr;
81 struct amdgpu_device *dev;
84 uint64_t virtual_mc_base_address;
89 pthread_mutex_t cpu_access_mutex;
94 struct amdgpu_bo_list {
95 struct amdgpu_device *dev;
101 * There are three mutexes.
102 * To avoid deadlock, only hold the mutexes in this order:
103 * sequence_mutex -> pendings_mutex -> pool_mutex.
105 struct amdgpu_context {
106 struct amdgpu_device *dev;
107 /** Mutex for accessing fences and to maintain command submissions
108 and pending lists in good sequence. */
109 pthread_mutex_t sequence_mutex;
110 /** Buffer for user fences */
111 struct amdgpu_ib *fence_ib;
112 /** The newest expired fence for the ring of the ip blocks. */
113 uint64_t expired_fences[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
114 /** Mutex for accessing pendings list. */
115 pthread_mutex_t pendings_mutex;
117 struct list_head pendings[AMDGPU_HW_IP_NUM][AMDGPU_HW_IP_INSTANCE_MAX_COUNT][AMDGPU_CS_MAX_RINGS];
118 /** Freed IBs not yet in pool */
119 struct list_head freed;
120 /** Mutex for accessing free ib pool. */
121 pthread_mutex_t pool_mutex;
122 /** Internal free IB pools. */
123 struct list_head ib_pools[AMDGPU_CS_IB_SIZE_NUM];
129 amdgpu_context_handle context;
130 struct list_head list_node;
131 amdgpu_bo_handle buf_handle;
133 uint64_t virtual_mc_base_address;
134 enum amdgpu_cs_ib_size ib_size;
142 void amdgpu_device_free_internal(amdgpu_device_handle dev);
144 void amdgpu_bo_free_internal(amdgpu_bo_handle bo);
146 struct amdgpu_bo_va_mgr* amdgpu_vamgr_get_global(struct amdgpu_device *dev);
148 void amdgpu_vamgr_reference(struct amdgpu_bo_va_mgr **dst, struct amdgpu_bo_va_mgr *src);
150 uint64_t amdgpu_vamgr_find_va(struct amdgpu_bo_va_mgr *mgr,
151 uint64_t size, uint64_t alignment);
153 void amdgpu_vamgr_free_va(struct amdgpu_bo_va_mgr *mgr, uint64_t va,
156 int amdgpu_query_gpu_info_init(amdgpu_device_handle dev);
158 uint64_t amdgpu_cs_calculate_timeout(uint64_t timeout);
165 * Increment src and decrement dst as if we were updating references
166 * for an assignment between 2 pointers of some objects.
168 * \return true if dst is 0
170 static inline bool update_references(atomic_t *dst, atomic_t *src)
175 assert(atomic_read(src) > 0);
179 assert(atomic_read(dst) > 0);
180 return atomic_dec_and_test(dst);
187 * Assignment between two amdgpu_bo pointers with reference counting.
190 * struct amdgpu_bo *dst = ... , *src = ...;
193 * // No reference counting. Only use this when you need to move
194 * // a reference from one pointer to another.
196 * amdgpu_bo_reference(&dst, src);
197 * // Reference counters are updated. dst is decremented and src is
198 * // incremented. dst is freed if its reference counter is 0.
200 static inline void amdgpu_bo_reference(struct amdgpu_bo **dst,
201 struct amdgpu_bo *src)
203 if (update_references(&(*dst)->refcount, &src->refcount))
204 amdgpu_bo_free_internal(*dst);
209 * Assignment between two amdgpu_device pointers with reference counting.
212 * struct amdgpu_device *dst = ... , *src = ...;
215 * // No reference counting. Only use this when you need to move
216 * // a reference from one pointer to another.
218 * amdgpu_device_reference(&dst, src);
219 * // Reference counters are updated. dst is decremented and src is
220 * // incremented. dst is freed if its reference counter is 0.
222 void amdgpu_device_reference(struct amdgpu_device **dst,
223 struct amdgpu_device *src);