amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 // clang-format off
  22 #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so)
  23 // clang-format on
  24
  25 #define TILE_TYPE_LINEAR 0
  26 /* DRI backend decides tiling in this case. */
  27 #define TILE_TYPE_DRI 1
  28
  29 struct amdgpu_priv {
  30         struct dri_driver dri;
  31         int drm_version;
  32 };
  33
  34 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  35                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  36                                                   DRM_FORMAT_XRGB8888 };
  37
  38 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88,           DRM_FORMAT_R8,
  39                                                    DRM_FORMAT_NV21,           DRM_FORMAT_NV12,
  40                                                    DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 };
  41
  42 static int amdgpu_init(struct driver *drv)
  43 {
  44         struct amdgpu_priv *priv;
  45         drmVersionPtr drm_version;
  46         struct format_metadata metadata;
  47         uint64_t use_flags = BO_USE_RENDER_MASK;
  48
  49         priv = calloc(1, sizeof(struct amdgpu_priv));
  50         if (!priv)
  51                 return -ENOMEM;
  52
  53         drm_version = drmGetVersion(drv_get_fd(drv));
  54         if (!drm_version) {
  55                 free(priv);
  56                 return -ENODEV;
  57         }
  58
  59         priv->drm_version = drm_version->version_minor;
  60         drmFreeVersion(drm_version);
  61
  62         drv->priv = priv;
  63
  64         if (dri_init(drv, DRI_PATH, "radeonsi")) {
  65                 free(priv);
  66                 drv->priv = NULL;
  67                 return -ENODEV;
  68         }
  69
  70         metadata.tiling = TILE_TYPE_LINEAR;
  71         metadata.priority = 1;
  72         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  73
  74         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  75                              &metadata, use_flags);
  76
  77         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
  78                              &metadata, BO_USE_TEXTURE_MASK);
  79
  80         /* NV12 format for camera, display, decoding and encoding. */
  81         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  82                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
  83                                    BO_USE_HW_VIDEO_DECODER | BO_USE_HW_VIDEO_ENCODER);
  84
  85         /* Android CTS tests require this. */
  86         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
  87
  88         /* Linear formats supported by display. */
  89         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  90         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  91         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
  92         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
  93
  94         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
  95
  96         /*
  97          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
  98          * from camera and input/output from hardware decoder/encoder.
  99          */
 100         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 101                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_HW_VIDEO_DECODER |
 102                                    BO_USE_HW_VIDEO_ENCODER);
 103
 104         /*
 105          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 106          * Since format modifier support hasn't been implemented fully yet, it's not
 107          * possible to enumerate the different types of buffers (like i915 can).
 108          */
 109         use_flags &= ~BO_USE_RENDERSCRIPT;
 110         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 111         use_flags &= ~BO_USE_SW_READ_OFTEN;
 112         use_flags &= ~BO_USE_LINEAR;
 113
 114         metadata.tiling = TILE_TYPE_DRI;
 115         metadata.priority = 2;
 116
 117         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 118                              &metadata, use_flags);
 119
 120         /* Potentially tiled formats supported by display. */
 121         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 122         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 123         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 124         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 125         return 0;
 126 }
 127
 128 static void amdgpu_close(struct driver *drv)
 129 {
 130         dri_close(drv);
 131         free(drv->priv);
 132         drv->priv = NULL;
 133 }
 134
 135 static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 136                                    uint64_t use_flags)
 137 {
 138         int ret;
 139         uint32_t plane, stride;
 140         union drm_amdgpu_gem_create gem_create;
 141
 142         stride = drv_stride_from_format(format, width, 0);
 143         stride = ALIGN(stride, 256);
 144
 145         drv_bo_from_format(bo, stride, height, format);
 146
 147         memset(&gem_create, 0, sizeof(gem_create));
 148         gem_create.in.bo_size = bo->meta.total_size;
 149         gem_create.in.alignment = 256;
 150         gem_create.in.domain_flags = 0;
 151
 152         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 153                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 154
 155         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 156         if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
 157                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 158
 159         /* Allocate the buffer with the preferred heap. */
 160         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 161                                   sizeof(gem_create));
 162         if (ret < 0)
 163                 return ret;
 164
 165         for (plane = 0; plane < bo->meta.num_planes; plane++)
 166                 bo->handles[plane].u32 = gem_create.out.handle;
 167
 168         bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR;
 169
 170         return 0;
 171 }
 172
 173 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 174                             uint64_t use_flags)
 175 {
 176         struct combination *combo;
 177
 178         combo = drv_get_combination(bo->drv, format, use_flags);
 179         if (!combo)
 180                 return -EINVAL;
 181
 182         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 183                 bool needs_alignment = false;
 184 #ifdef __ANDROID__
 185                 /*
 186                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 187                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 188                  * allocation time.
 189                  *
 190                  * See b/115946221,b/117942643
 191                  */
 192                 if (use_flags & (BO_USE_SW_MASK))
 193                         needs_alignment = true;
 194 #endif
 195                 // See b/122049612
 196                 if (use_flags & (BO_USE_SCANOUT))
 197                         needs_alignment = true;
 198
 199                 if (needs_alignment) {
 200                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 201                         width = ALIGN(width, 256 / bytes_per_pixel);
 202                 }
 203
 204                 return dri_bo_create(bo, width, height, format, use_flags);
 205         }
 206
 207         return amdgpu_create_bo_linear(bo, width, height, format, use_flags);
 208 }
 209
 210 static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 211                                            uint32_t format, const uint64_t *modifiers,
 212                                            uint32_t count)
 213 {
 214         bool only_use_linear = true;
 215
 216         for (uint32_t i = 0; i < count; ++i)
 217                 if (modifiers[i] != DRM_FORMAT_MOD_LINEAR)
 218                         only_use_linear = false;
 219
 220         if (only_use_linear)
 221                 return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT);
 222
 223         return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count);
 224 }
 225
 226 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 227 {
 228         bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR;
 229         if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) {
 230                 struct combination *combo;
 231                 combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 232                 if (!combo)
 233                         return -EINVAL;
 234
 235                 dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI;
 236         }
 237
 238         if (dri_tiling)
 239                 return dri_bo_import(bo, data);
 240         else
 241                 return drv_prime_bo_import(bo, data);
 242 }
 243
 244 static int amdgpu_destroy_bo(struct bo *bo)
 245 {
 246         if (bo->priv)
 247                 return dri_bo_destroy(bo);
 248         else
 249                 return drv_gem_bo_destroy(bo);
 250 }
 251
 252 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 253 {
 254         int ret;
 255         union drm_amdgpu_gem_mmap gem_map;
 256
 257         if (bo->priv)
 258                 return dri_bo_map(bo, vma, plane, map_flags);
 259
 260         memset(&gem_map, 0, sizeof(gem_map));
 261         gem_map.in.handle = bo->handles[plane].u32;
 262
 263         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 264         if (ret) {
 265                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 266                 return MAP_FAILED;
 267         }
 268
 269         vma->length = bo->meta.total_size;
 270
 271         return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 272                     gem_map.out.addr_ptr);
 273 }
 274
 275 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 276 {
 277         if (bo->priv)
 278                 return dri_bo_unmap(bo, vma);
 279         else
 280                 return munmap(vma->addr, vma->length);
 281 }
 282
 283 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 284 {
 285         int ret;
 286         union drm_amdgpu_gem_wait_idle wait_idle;
 287
 288         if (bo->priv)
 289                 return 0;
 290
 291         memset(&wait_idle, 0, sizeof(wait_idle));
 292         wait_idle.in.handle = bo->handles[0].u32;
 293         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 294
 295         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 296                                   sizeof(wait_idle));
 297
 298         if (ret < 0) {
 299                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 300                 return ret;
 301         }
 302
 303         if (ret == 0 && wait_idle.out.status)
 304                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 305
 306         return 0;
 307 }
 308
 309 static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 310 {
 311         switch (format) {
 312         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 313                 /* Camera subsystem requires NV12. */
 314                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 315                         return DRM_FORMAT_NV12;
 316                 /*HACK: See b/28671744 */
 317                 return DRM_FORMAT_XBGR8888;
 318         case DRM_FORMAT_FLEX_YCbCr_420_888:
 319                 return DRM_FORMAT_NV12;
 320         default:
 321                 return format;
 322         }
 323 }
 324
 325 const struct backend backend_amdgpu = {
 326         .name = "amdgpu",
 327         .init = amdgpu_init,
 328         .close = amdgpu_close,
 329         .bo_create = amdgpu_create_bo,
 330         .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers,
 331         .bo_destroy = amdgpu_destroy_bo,
 332         .bo_import = amdgpu_import_bo,
 333         .bo_map = amdgpu_map_bo,
 334         .bo_unmap = amdgpu_unmap_bo,
 335         .bo_invalidate = amdgpu_bo_invalidate,
 336         .resolve_format = amdgpu_resolve_format,
 337         .num_planes_from_modifier = dri_num_planes_from_modifier,
 338 };
 339
 340 #endif