2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
8 #include <amdgpu_drm.h>
16 #include "addrinterface.h"
21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
26 #define mmCC_RB_BACKEND_DISABLE 0x263d
27 #define mmGB_TILE_MODE0 0x2644
28 #define mmGB_MACROTILE_MODE0 0x2664
29 #define mmGB_ADDR_CONFIG 0x263e
30 #define mmMC_ARB_RAMCFG 0x9d8
44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
45 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
46 DRM_FORMAT_XRGB8888 };
48 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
51 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
53 struct drm_amdgpu_gem_metadata args = { 0 };
59 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
60 args.data.flags = info->flags;
61 args.data.tiling_info = info->tiling_info;
63 if (info->size_metadata > sizeof(args.data.data))
66 if (info->size_metadata) {
67 args.data.data_size_bytes = info->size_metadata;
68 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
71 return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
74 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
75 uint32_t flags, uint32_t *values)
77 struct drm_amdgpu_info request;
79 memset(&request, 0, sizeof(request));
80 request.return_pointer = (uintptr_t)values;
81 request.return_size = count * sizeof(uint32_t);
82 request.query = AMDGPU_INFO_READ_MMR_REG;
83 request.read_mmr_reg.dword_offset = dword_offset;
84 request.read_mmr_reg.count = count;
85 request.read_mmr_reg.instance = instance;
86 request.read_mmr_reg.flags = flags;
88 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
91 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
99 instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
101 ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
102 &gpu_info->backend_disable[0]);
105 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
106 gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
108 ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
112 ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
113 gpu_info->gb_macro_tile_mode);
117 ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
121 ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
128 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
130 return malloc(in->sizeInBytes);
133 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
139 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
140 uint64_t use_flags, uint32_t *tiling_flags,
141 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
143 ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
144 ADDR_TILEINFO addr_tile_info = { 0 };
145 ADDR_TILEINFO addr_tile_info_out = { 0 };
146 uint32_t bits_per_pixel;
148 addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
150 /* Set the requested tiling mode. */
151 addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
153 (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
154 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
155 else if (width <= 16 || height <= 16)
156 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
158 bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
159 /* Bits per pixel should be calculated from format*/
160 addr_surf_info_in.bpp = bits_per_pixel;
161 addr_surf_info_in.numSamples = 1;
162 addr_surf_info_in.width = width;
163 addr_surf_info_in.height = height;
164 addr_surf_info_in.numSlices = 1;
165 addr_surf_info_in.pTileInfo = &addr_tile_info;
166 addr_surf_info_in.tileIndex = -1;
168 /* This disables incorrect calculations (hacks) in addrlib. */
169 addr_surf_info_in.flags.noStencil = 1;
171 /* Set the micro tile type. */
172 if (use_flags & BO_USE_SCANOUT)
173 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
175 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
177 addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
178 addr_out->pTileInfo = &addr_tile_info_out;
180 if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
183 ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
184 ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
185 ADDR_TILEINFO s_tile_hw_info_out = { 0 };
187 s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
188 /* Convert from real value to HW value */
190 s_in.pTileInfo = &addr_tile_info_out;
193 s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
194 s_out.pTileInfo = &s_tile_hw_info_out;
196 if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
199 if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
201 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
202 else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
204 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
207 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
209 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
211 AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
212 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
213 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
214 drv_log_base2(addr_tile_info_out.macroAspectRatio));
215 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
216 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
221 static void *amdgpu_addrlib_init(int fd)
224 ADDR_CREATE_INPUT addr_create_input = { 0 };
225 ADDR_CREATE_OUTPUT addr_create_output = { 0 };
226 ADDR_REGISTER_VALUE reg_value = { 0 };
227 ADDR_CREATE_FLAGS create_flags = { { 0 } };
228 ADDR_E_RETURNCODE addr_ret;
230 addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
231 addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
233 struct amdgpu_gpu_info gpu_info = { 0 };
235 ret = amdgpu_query_gpu(fd, &gpu_info);
238 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
242 reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
243 reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
244 reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
246 reg_value.backendDisables = gpu_info.backend_disable[0];
247 reg_value.pTileConfig = gpu_info.gb_tile_mode;
248 reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
249 reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
250 reg_value.noOfMacroEntries =
251 sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
252 create_flags.value = 0;
253 create_flags.useTileIndex = 1;
255 addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
257 addr_create_input.chipFamily = FAMILY_CZ;
258 addr_create_input.createFlags = create_flags;
259 addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
260 addr_create_input.callbacks.freeSysMem = free_sys_mem;
261 addr_create_input.callbacks.debugPrint = 0;
262 addr_create_input.regValue = reg_value;
264 addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
266 if (addr_ret != ADDR_OK) {
267 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
271 return addr_create_output.hLib;
274 static int amdgpu_init(struct driver *drv)
278 struct format_metadata metadata;
279 uint64_t use_flags = BO_USE_RENDER_MASK;
281 addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
287 ret = drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
288 &LINEAR_METADATA, BO_USE_TEXTURE_MASK);
292 drv_modify_combination(drv, DRM_FORMAT_NV21, &LINEAR_METADATA, BO_USE_SCANOUT);
293 drv_modify_combination(drv, DRM_FORMAT_NV12, &LINEAR_METADATA, BO_USE_SCANOUT);
295 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
296 metadata.priority = 2;
297 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
299 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
300 &metadata, use_flags);
304 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
305 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
306 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
308 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
309 metadata.priority = 3;
310 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
312 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
313 &metadata, use_flags);
317 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
318 use_flags &= ~BO_USE_SW_READ_OFTEN;
319 use_flags &= ~BO_USE_LINEAR;
321 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
322 metadata.priority = 4;
324 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
325 &metadata, use_flags);
329 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
330 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
331 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
333 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
334 metadata.priority = 5;
336 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
337 &metadata, use_flags);
344 static void amdgpu_close(struct driver *drv)
346 AddrDestroy(drv->priv);
350 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
353 void *addrlib = bo->drv->priv;
354 union drm_amdgpu_gem_create gem_create;
355 struct amdgpu_bo_metadata metadata = { 0 };
356 ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
357 uint32_t tiling_flags = 0;
361 if (format == DRM_FORMAT_NV12 || format == DRM_FORMAT_NV21) {
362 drv_bo_from_format(bo, ALIGN(width, 64), height, format);
364 if (amdgpu_addrlib_compute(addrlib, width, height, format, use_flags, &tiling_flags,
368 bo->tiling = tiling_flags;
369 /* RGB has 1 plane only */
371 bo->total_size = bo->sizes[0] = addr_out.surfSize;
372 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
375 memset(&gem_create, 0, sizeof(gem_create));
377 gem_create.in.bo_size = bo->total_size;
378 gem_create.in.alignment = addr_out.baseAlign;
379 /* Set the placement. */
380 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
381 gem_create.in.domain_flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
382 /* Allocate the buffer with the preferred heap. */
383 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
389 metadata.tiling_info = tiling_flags;
391 for (plane = 0; plane < bo->num_planes; plane++)
392 bo->handles[plane].u32 = gem_create.out.handle;
394 ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
399 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane, uint32_t map_flags)
402 union drm_amdgpu_gem_mmap gem_map;
404 memset(&gem_map, 0, sizeof(gem_map));
405 gem_map.in.handle = bo->handles[plane].u32;
407 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
409 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
413 data->length = bo->total_size;
415 return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
416 gem_map.out.addr_ptr);
419 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
422 case DRM_FORMAT_FLEX_YCbCr_420_888:
423 return DRM_FORMAT_NV12;
429 const struct backend backend_amdgpu = {
432 .close = amdgpu_close,
433 .bo_create = amdgpu_bo_create,
434 .bo_destroy = drv_gem_bo_destroy,
435 .bo_import = drv_prime_bo_import,
436 .bo_map = amdgpu_bo_map,
437 .bo_unmap = drv_bo_munmap,
438 .resolve_format = amdgpu_resolve_format,