amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 // clang-format off
  22 #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so)
  23 // clang-format on
  24
  25 #define TILE_TYPE_LINEAR 0
  26 /* DRI backend decides tiling in this case. */
  27 #define TILE_TYPE_DRI 1
  28
  29 struct amdgpu_priv {
  30         struct dri_driver dri;
  31         int drm_version;
  32 };
  33
  34 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  35                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  36                                                   DRM_FORMAT_XRGB8888 };
  37
  38 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88,           DRM_FORMAT_R8,
  39                                                    DRM_FORMAT_NV21,           DRM_FORMAT_NV12,
  40                                                    DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 };
  41
  42 static int amdgpu_init(struct driver *drv)
  43 {
  44         struct amdgpu_priv *priv;
  45         drmVersionPtr drm_version;
  46         struct format_metadata metadata;
  47         uint64_t use_flags = BO_USE_RENDER_MASK;
  48
  49         priv = calloc(1, sizeof(struct amdgpu_priv));
  50         if (!priv)
  51                 return -ENOMEM;
  52
  53         drm_version = drmGetVersion(drv_get_fd(drv));
  54         if (!drm_version) {
  55                 free(priv);
  56                 return -ENODEV;
  57         }
  58
  59         priv->drm_version = drm_version->version_minor;
  60         drmFreeVersion(drm_version);
  61
  62         drv->priv = priv;
  63
  64         if (dri_init(drv, DRI_PATH, "radeonsi")) {
  65                 free(priv);
  66                 drv->priv = NULL;
  67                 return -ENODEV;
  68         }
  69
  70         metadata.tiling = TILE_TYPE_LINEAR;
  71         metadata.priority = 1;
  72         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  73
  74         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  75                              &metadata, use_flags);
  76
  77         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
  78                              &metadata, BO_USE_TEXTURE_MASK);
  79
  80         /*
  81          * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
  82          * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
  83          */
  84         drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
  85         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER);
  86
  87         /* Android CTS tests require this. */
  88         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
  89
  90         /* Linear formats supported by display. */
  91         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  92         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  93         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
  94         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
  95
  96         /* YUV formats for camera and display. */
  97         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  98                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
  99                                    BO_USE_HW_VIDEO_DECODER);
 100
 101         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
 102
 103         /*
 104          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
 105          * from camera.
 106          */
 107         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 108                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 109
 110         /*
 111          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 112          * Since format modifier support hasn't been implemented fully yet, it's not
 113          * possible to enumerate the different types of buffers (like i915 can).
 114          */
 115         use_flags &= ~BO_USE_RENDERSCRIPT;
 116         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 117         use_flags &= ~BO_USE_SW_READ_OFTEN;
 118         use_flags &= ~BO_USE_LINEAR;
 119
 120         metadata.tiling = TILE_TYPE_DRI;
 121         metadata.priority = 2;
 122
 123         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 124                              &metadata, use_flags);
 125
 126         /* Potentially tiled formats supported by display. */
 127         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 128         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 129         drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
 130         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 131         return 0;
 132 }
 133
 134 static void amdgpu_close(struct driver *drv)
 135 {
 136         dri_close(drv);
 137         free(drv->priv);
 138         drv->priv = NULL;
 139 }
 140
 141 static int amdgpu_create_bo_linear(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 142                                    uint64_t use_flags)
 143 {
 144         int ret;
 145         uint32_t plane, stride;
 146         union drm_amdgpu_gem_create gem_create;
 147
 148         stride = drv_stride_from_format(format, width, 0);
 149         stride = ALIGN(stride, 256);
 150
 151         drv_bo_from_format(bo, stride, height, format);
 152
 153         memset(&gem_create, 0, sizeof(gem_create));
 154         gem_create.in.bo_size = bo->meta.total_size;
 155         gem_create.in.alignment = 256;
 156         gem_create.in.domain_flags = 0;
 157
 158         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 159                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 160
 161         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 162         gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 163
 164         /* Allocate the buffer with the preferred heap. */
 165         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 166                                   sizeof(gem_create));
 167         if (ret < 0)
 168                 return ret;
 169
 170         for (plane = 0; plane < bo->meta.num_planes; plane++)
 171                 bo->handles[plane].u32 = gem_create.out.handle;
 172
 173         bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR;
 174
 175         return 0;
 176 }
 177
 178 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 179                             uint64_t use_flags)
 180 {
 181         struct combination *combo;
 182
 183         combo = drv_get_combination(bo->drv, format, use_flags);
 184         if (!combo)
 185                 return -EINVAL;
 186
 187         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 188                 bool needs_alignment = false;
 189 #ifdef __ANDROID__
 190                 /*
 191                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 192                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 193                  * allocation time.
 194                  *
 195                  * See b/115946221,b/117942643
 196                  */
 197                 if (use_flags & (BO_USE_SW_MASK))
 198                         needs_alignment = true;
 199 #endif
 200                 // See b/122049612
 201                 if (use_flags & (BO_USE_SCANOUT))
 202                         needs_alignment = true;
 203
 204                 if (needs_alignment) {
 205                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 206                         width = ALIGN(width, 256 / bytes_per_pixel);
 207                 }
 208
 209                 return dri_bo_create(bo, width, height, format, use_flags);
 210         }
 211
 212         return amdgpu_create_bo_linear(bo, width, height, format, use_flags);
 213 }
 214
 215 static int amdgpu_create_bo_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
 216                                            uint32_t format, const uint64_t *modifiers,
 217                                            uint32_t count)
 218 {
 219         bool only_use_linear = true;
 220
 221         for (uint32_t i = 0; i < count; ++i)
 222                 if (modifiers[i] != DRM_FORMAT_MOD_LINEAR)
 223                         only_use_linear = false;
 224
 225         if (only_use_linear)
 226                 return amdgpu_create_bo_linear(bo, width, height, format, BO_USE_SCANOUT);
 227
 228         return dri_bo_create_with_modifiers(bo, width, height, format, modifiers, count);
 229 }
 230
 231 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 232 {
 233         bool dri_tiling = data->format_modifiers[0] != DRM_FORMAT_MOD_LINEAR;
 234         if (data->format_modifiers[0] == DRM_FORMAT_MOD_INVALID) {
 235                 struct combination *combo;
 236                 combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 237                 if (!combo)
 238                         return -EINVAL;
 239
 240                 dri_tiling = combo->metadata.tiling == TILE_TYPE_DRI;
 241         }
 242
 243         if (dri_tiling)
 244                 return dri_bo_import(bo, data);
 245         else
 246                 return drv_prime_bo_import(bo, data);
 247 }
 248
 249 static int amdgpu_destroy_bo(struct bo *bo)
 250 {
 251         if (bo->priv)
 252                 return dri_bo_destroy(bo);
 253         else
 254                 return drv_gem_bo_destroy(bo);
 255 }
 256
 257 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 258 {
 259         int ret;
 260         union drm_amdgpu_gem_mmap gem_map;
 261
 262         if (bo->priv)
 263                 return dri_bo_map(bo, vma, plane, map_flags);
 264
 265         memset(&gem_map, 0, sizeof(gem_map));
 266         gem_map.in.handle = bo->handles[plane].u32;
 267
 268         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 269         if (ret) {
 270                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 271                 return MAP_FAILED;
 272         }
 273
 274         vma->length = bo->meta.total_size;
 275
 276         return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 277                     gem_map.out.addr_ptr);
 278 }
 279
 280 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 281 {
 282         if (bo->priv)
 283                 return dri_bo_unmap(bo, vma);
 284         else
 285                 return munmap(vma->addr, vma->length);
 286 }
 287
 288 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 289 {
 290         int ret;
 291         union drm_amdgpu_gem_wait_idle wait_idle;
 292
 293         if (bo->priv)
 294                 return 0;
 295
 296         memset(&wait_idle, 0, sizeof(wait_idle));
 297         wait_idle.in.handle = bo->handles[0].u32;
 298         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 299
 300         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 301                                   sizeof(wait_idle));
 302
 303         if (ret < 0) {
 304                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 305                 return ret;
 306         }
 307
 308         if (ret == 0 && wait_idle.out.status)
 309                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 310
 311         return 0;
 312 }
 313
 314 static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
 315 {
 316         switch (format) {
 317         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 318                 /* Camera subsystem requires NV12. */
 319                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 320                         return DRM_FORMAT_NV12;
 321                 /*HACK: See b/28671744 */
 322                 return DRM_FORMAT_XBGR8888;
 323         case DRM_FORMAT_FLEX_YCbCr_420_888:
 324                 return DRM_FORMAT_NV12;
 325         default:
 326                 return format;
 327         }
 328 }
 329
 330 const struct backend backend_amdgpu = {
 331         .name = "amdgpu",
 332         .init = amdgpu_init,
 333         .close = amdgpu_close,
 334         .bo_create = amdgpu_create_bo,
 335         .bo_create_with_modifiers = amdgpu_create_bo_with_modifiers,
 336         .bo_destroy = amdgpu_destroy_bo,
 337         .bo_import = amdgpu_import_bo,
 338         .bo_map = amdgpu_map_bo,
 339         .bo_unmap = amdgpu_unmap_bo,
 340         .bo_invalidate = amdgpu_bo_invalidate,
 341         .resolve_format = amdgpu_resolve_format,
 342         .num_planes_from_modifier = dri_num_planes_from_modifier,
 343 };
 344
 345 #endif