2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
8 #include <amdgpu_drm.h>
16 #include "addrinterface.h"
21 #ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
22 #define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
26 #define mmCC_RB_BACKEND_DISABLE 0x263d
27 #define mmGB_TILE_MODE0 0x2644
28 #define mmGB_MACROTILE_MODE0 0x2664
29 #define mmGB_ADDR_CONFIG 0x263e
30 #define mmMC_ARB_RAMCFG 0x9d8
44 const static uint32_t render_target_formats[] = { DRM_FORMAT_ARGB8888, DRM_FORMAT_XBGR8888,
45 DRM_FORMAT_XRGB8888 };
47 static int amdgpu_set_metadata(int fd, uint32_t handle, struct amdgpu_bo_metadata *info)
49 struct drm_amdgpu_gem_metadata args = { 0 };
55 args.op = AMDGPU_GEM_METADATA_OP_SET_METADATA;
56 args.data.flags = info->flags;
57 args.data.tiling_info = info->tiling_info;
59 if (info->size_metadata > sizeof(args.data.data))
62 if (info->size_metadata) {
63 args.data.data_size_bytes = info->size_metadata;
64 memcpy(args.data.data, info->umd_metadata, info->size_metadata);
67 return drmCommandWriteRead(fd, DRM_AMDGPU_GEM_METADATA, &args, sizeof(args));
70 static int amdgpu_read_mm_regs(int fd, unsigned dword_offset, unsigned count, uint32_t instance,
71 uint32_t flags, uint32_t *values)
73 struct drm_amdgpu_info request;
75 memset(&request, 0, sizeof(request));
76 request.return_pointer = (uintptr_t)values;
77 request.return_size = count * sizeof(uint32_t);
78 request.query = AMDGPU_INFO_READ_MMR_REG;
79 request.read_mmr_reg.dword_offset = dword_offset;
80 request.read_mmr_reg.count = count;
81 request.read_mmr_reg.instance = instance;
82 request.read_mmr_reg.flags = flags;
84 return drmCommandWrite(fd, DRM_AMDGPU_INFO, &request, sizeof(struct drm_amdgpu_info));
87 static int amdgpu_query_gpu(int fd, struct amdgpu_gpu_info *gpu_info)
95 instance = AMDGPU_INFO_MMR_SH_INDEX_MASK << AMDGPU_INFO_MMR_SH_INDEX_SHIFT;
97 ret = amdgpu_read_mm_regs(fd, mmCC_RB_BACKEND_DISABLE, 1, instance, 0,
98 &gpu_info->backend_disable[0]);
101 /* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
102 gpu_info->backend_disable[0] = (gpu_info->backend_disable[0] >> 16) & 0xff;
104 ret = amdgpu_read_mm_regs(fd, mmGB_TILE_MODE0, 32, 0xffffffff, 0, gpu_info->gb_tile_mode);
108 ret = amdgpu_read_mm_regs(fd, mmGB_MACROTILE_MODE0, 16, 0xffffffff, 0,
109 gpu_info->gb_macro_tile_mode);
113 ret = amdgpu_read_mm_regs(fd, mmGB_ADDR_CONFIG, 1, 0xffffffff, 0, &gpu_info->gb_addr_cfg);
117 ret = amdgpu_read_mm_regs(fd, mmMC_ARB_RAMCFG, 1, 0xffffffff, 0, &gpu_info->mc_arb_ramcfg);
124 static void *ADDR_API alloc_sys_mem(const ADDR_ALLOCSYSMEM_INPUT *in)
126 return malloc(in->sizeInBytes);
129 static ADDR_E_RETURNCODE ADDR_API free_sys_mem(const ADDR_FREESYSMEM_INPUT *in)
135 static int amdgpu_addrlib_compute(void *addrlib, uint32_t width, uint32_t height, uint32_t format,
136 uint32_t usage, uint32_t *tiling_flags,
137 ADDR_COMPUTE_SURFACE_INFO_OUTPUT *addr_out)
139 ADDR_COMPUTE_SURFACE_INFO_INPUT addr_surf_info_in = { 0 };
140 ADDR_TILEINFO addr_tile_info = { 0 };
141 ADDR_TILEINFO addr_tile_info_out = { 0 };
142 uint32_t bits_per_pixel;
144 addr_surf_info_in.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
146 /* Set the requested tiling mode. */
147 addr_surf_info_in.tileMode = ADDR_TM_2D_TILED_THIN1;
148 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN))
149 addr_surf_info_in.tileMode = ADDR_TM_LINEAR_ALIGNED;
150 else if (width <= 16 || height <= 16)
151 addr_surf_info_in.tileMode = ADDR_TM_1D_TILED_THIN1;
153 bits_per_pixel = drv_stride_from_format(format, 1, 0) * 8;
154 /* Bits per pixel should be calculated from format*/
155 addr_surf_info_in.bpp = bits_per_pixel;
156 addr_surf_info_in.numSamples = 1;
157 addr_surf_info_in.width = width;
158 addr_surf_info_in.height = height;
159 addr_surf_info_in.numSlices = 1;
160 addr_surf_info_in.pTileInfo = &addr_tile_info;
161 addr_surf_info_in.tileIndex = -1;
163 /* This disables incorrect calculations (hacks) in addrlib. */
164 addr_surf_info_in.flags.noStencil = 1;
166 /* Set the micro tile type. */
167 if (usage & BO_USE_SCANOUT)
168 addr_surf_info_in.tileType = ADDR_DISPLAYABLE;
170 addr_surf_info_in.tileType = ADDR_NON_DISPLAYABLE;
172 addr_out->size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
173 addr_out->pTileInfo = &addr_tile_info_out;
175 if (AddrComputeSurfaceInfo(addrlib, &addr_surf_info_in, addr_out) != ADDR_OK)
178 ADDR_CONVERT_TILEINFOTOHW_INPUT s_in = { 0 };
179 ADDR_CONVERT_TILEINFOTOHW_OUTPUT s_out = { 0 };
180 ADDR_TILEINFO s_tile_hw_info_out = { 0 };
182 s_in.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_INPUT);
183 /* Convert from real value to HW value */
185 s_in.pTileInfo = &addr_tile_info_out;
188 s_out.size = sizeof(ADDR_CONVERT_TILEINFOTOHW_OUTPUT);
189 s_out.pTileInfo = &s_tile_hw_info_out;
191 if (AddrConvertTileInfoToHW(addrlib, &s_in, &s_out) != ADDR_OK)
194 if (addr_out->tileMode >= ADDR_TM_2D_TILED_THIN1)
196 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4);
197 else if (addr_out->tileMode >= ADDR_TM_1D_TILED_THIN1)
199 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2);
202 *tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1);
204 *tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, drv_log_base2(addr_tile_info_out.bankWidth));
206 AMDGPU_TILING_SET(BANK_HEIGHT, drv_log_base2(addr_tile_info_out.bankHeight));
207 *tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT, s_tile_hw_info_out.tileSplitBytes);
208 *tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT,
209 drv_log_base2(addr_tile_info_out.macroAspectRatio));
210 *tiling_flags |= AMDGPU_TILING_SET(PIPE_CONFIG, s_tile_hw_info_out.pipeConfig);
211 *tiling_flags |= AMDGPU_TILING_SET(NUM_BANKS, s_tile_hw_info_out.banks);
216 static void *amdgpu_addrlib_init(int fd)
219 ADDR_CREATE_INPUT addr_create_input = { 0 };
220 ADDR_CREATE_OUTPUT addr_create_output = { 0 };
221 ADDR_REGISTER_VALUE reg_value = { 0 };
222 ADDR_CREATE_FLAGS create_flags = { { 0 } };
223 ADDR_E_RETURNCODE addr_ret;
225 addr_create_input.size = sizeof(ADDR_CREATE_INPUT);
226 addr_create_output.size = sizeof(ADDR_CREATE_OUTPUT);
228 struct amdgpu_gpu_info gpu_info = { 0 };
230 ret = amdgpu_query_gpu(fd, &gpu_info);
233 fprintf(stderr, "[%s]failed with error =%d\n", __func__, ret);
237 reg_value.noOfBanks = gpu_info.mc_arb_ramcfg & 0x3;
238 reg_value.gbAddrConfig = gpu_info.gb_addr_cfg;
239 reg_value.noOfRanks = (gpu_info.mc_arb_ramcfg & 0x4) >> 2;
241 reg_value.backendDisables = gpu_info.backend_disable[0];
242 reg_value.pTileConfig = gpu_info.gb_tile_mode;
243 reg_value.noOfEntries = sizeof(gpu_info.gb_tile_mode) / sizeof(gpu_info.gb_tile_mode[0]);
244 reg_value.pMacroTileConfig = gpu_info.gb_macro_tile_mode;
245 reg_value.noOfMacroEntries =
246 sizeof(gpu_info.gb_macro_tile_mode) / sizeof(gpu_info.gb_macro_tile_mode[0]);
247 create_flags.value = 0;
248 create_flags.useTileIndex = 1;
250 addr_create_input.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
252 addr_create_input.chipFamily = FAMILY_CZ;
253 addr_create_input.createFlags = create_flags;
254 addr_create_input.callbacks.allocSysMem = alloc_sys_mem;
255 addr_create_input.callbacks.freeSysMem = free_sys_mem;
256 addr_create_input.callbacks.debugPrint = 0;
257 addr_create_input.regValue = reg_value;
259 addr_ret = AddrCreate(&addr_create_input, &addr_create_output);
261 if (addr_ret != ADDR_OK) {
262 fprintf(stderr, "[%s]failed error =%d\n", __func__, addr_ret);
266 return addr_create_output.hLib;
269 static int amdgpu_init(struct driver *drv)
273 struct format_metadata metadata;
274 uint32_t flags = BO_USE_RENDER_MASK;
276 addrlib = amdgpu_addrlib_init(drv_get_fd(drv));
282 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
283 metadata.priority = 1;
284 metadata.modifier = DRM_FORMAT_MOD_NONE;
286 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
291 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
292 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
293 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
295 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_LINEAR_ALIGNED;
296 metadata.priority = 2;
297 metadata.modifier = DRM_FORMAT_MOD_NONE;
299 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
304 flags &= ~BO_USE_SW_WRITE_OFTEN;
305 flags &= ~BO_USE_SW_READ_OFTEN;
306 flags &= ~BO_USE_LINEAR;
308 metadata.tiling = ADDR_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
309 metadata.priority = 3;
311 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
316 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_SCANOUT);
317 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_SCANOUT);
318 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
320 metadata.tiling = ADDR_NON_DISPLAYABLE << 16 | ADDR_TM_2D_TILED_THIN1;
321 metadata.priority = 4;
323 ret = drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
331 static void amdgpu_close(struct driver *drv)
333 AddrDestroy(drv->priv);
337 static int amdgpu_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
340 void *addrlib = bo->drv->priv;
341 union drm_amdgpu_gem_create gem_create;
342 struct amdgpu_bo_metadata metadata = { 0 };
343 ADDR_COMPUTE_SURFACE_INFO_OUTPUT addr_out = { 0 };
344 uint32_t tiling_flags = 0;
345 uint32_t gem_create_flags = 0;
348 if (amdgpu_addrlib_compute(addrlib, width, height, format, usage, &tiling_flags,
352 bo->tiling = tiling_flags;
354 bo->sizes[0] = addr_out.surfSize;
355 bo->strides[0] = addr_out.pixelPitch * DIV_ROUND_UP(addr_out.pixelBits, 8);
356 if (usage & (BO_USE_CURSOR | BO_USE_LINEAR | BO_USE_SW_READ_OFTEN | BO_USE_SW_WRITE_OFTEN |
357 BO_USE_SW_WRITE_RARELY | BO_USE_SW_READ_RARELY))
358 gem_create_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
360 gem_create_flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
362 memset(&gem_create, 0, sizeof(gem_create));
363 gem_create.in.bo_size = bo->sizes[0];
364 gem_create.in.alignment = addr_out.baseAlign;
365 /* Set the placement. */
366 gem_create.in.domains = AMDGPU_GEM_DOMAIN_VRAM;
367 gem_create.in.domain_flags = gem_create_flags;
369 /* Allocate the buffer with the preferred heap. */
370 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
376 bo->handles[0].u32 = gem_create.out.handle;
378 metadata.tiling_info = tiling_flags;
380 ret = amdgpu_set_metadata(drv_get_fd(bo->drv), bo->handles[0].u32, &metadata);
385 static void *amdgpu_bo_map(struct bo *bo, struct map_info *data, size_t plane)
388 union drm_amdgpu_gem_mmap gem_map;
390 memset(&gem_map, 0, sizeof(gem_map));
391 gem_map.in.handle = bo->handles[0].u32;
393 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
395 fprintf(stderr, "drv: DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
398 data->length = bo->sizes[0];
400 return mmap(0, bo->sizes[0], PROT_READ | PROT_WRITE, MAP_SHARED, bo->drv->fd,
401 gem_map.out.addr_ptr);
404 struct backend backend_amdgpu = {
407 .close = amdgpu_close,
408 .bo_create = amdgpu_bo_create,
409 .bo_destroy = drv_gem_bo_destroy,
410 .bo_import = drv_prime_bo_import,
411 .bo_map = amdgpu_bo_map,