2 * Copyright 2016 The Chromium OS Authors. All rights reserved.
3 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
8 #include <amdgpu_drm.h>
22 #define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so"
25 #define DRI_PATH STRINGIZE(DRI_DRIVER_DIR/radeonsi_dri.so)
29 #define TILE_TYPE_LINEAR 0
30 /* DRI backend decides tiling in this case. */
31 #define TILE_TYPE_DRI 1
34 struct dri_driver dri;
38 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
39 DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
40 DRM_FORMAT_XRGB8888 };
42 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8,
43 DRM_FORMAT_NV21, DRM_FORMAT_NV12,
44 DRM_FORMAT_YVU420_ANDROID, DRM_FORMAT_YVU420 };
46 static int amdgpu_init(struct driver *drv)
48 struct amdgpu_priv *priv;
49 drmVersionPtr drm_version;
50 struct format_metadata metadata;
51 uint64_t use_flags = BO_USE_RENDER_MASK;
53 priv = calloc(1, sizeof(struct amdgpu_priv));
57 drm_version = drmGetVersion(drv_get_fd(drv));
63 priv->drm_version = drm_version->version_minor;
64 drmFreeVersion(drm_version);
68 if (dri_init(drv, DRI_PATH, "radeonsi")) {
74 metadata.tiling = TILE_TYPE_LINEAR;
75 metadata.priority = 1;
76 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
78 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
79 &metadata, use_flags);
81 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
82 &metadata, BO_USE_TEXTURE_MASK);
85 * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
86 * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
88 drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
89 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata, BO_USE_HW_VIDEO_ENCODER);
91 /* Android CTS tests require this. */
92 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
94 /* Linear formats supported by display. */
95 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
96 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
97 drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
98 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
100 /* YUV formats for camera and display. */
101 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
102 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
103 BO_USE_HW_VIDEO_DECODER);
105 drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
108 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
111 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
112 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
115 * The following formats will be allocated by the DRI backend and may be potentially tiled.
116 * Since format modifier support hasn't been implemented fully yet, it's not
117 * possible to enumerate the different types of buffers (like i915 can).
119 use_flags &= ~BO_USE_RENDERSCRIPT;
120 use_flags &= ~BO_USE_SW_WRITE_OFTEN;
121 use_flags &= ~BO_USE_SW_READ_OFTEN;
122 use_flags &= ~BO_USE_LINEAR;
124 metadata.tiling = TILE_TYPE_DRI;
125 metadata.priority = 2;
127 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
128 &metadata, use_flags);
130 /* Potentially tiled formats supported by display. */
131 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
132 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
133 drv_modify_combination(drv, DRM_FORMAT_ABGR8888, &metadata, BO_USE_SCANOUT);
134 drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
138 static void amdgpu_close(struct driver *drv)
145 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
149 uint32_t plane, stride;
150 struct combination *combo;
151 union drm_amdgpu_gem_create gem_create;
153 combo = drv_get_combination(bo->drv, format, use_flags);
157 if (combo->metadata.tiling == TILE_TYPE_DRI) {
158 bool needs_alignment = false;
161 * Currently, the gralloc API doesn't differentiate between allocation time and map
162 * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
165 * See b/115946221,b/117942643
167 if (use_flags & (BO_USE_SW_MASK))
168 needs_alignment = true;
171 if (use_flags & (BO_USE_SCANOUT))
172 needs_alignment = true;
174 if (needs_alignment) {
175 uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
176 width = ALIGN(width, 256 / bytes_per_pixel);
179 return dri_bo_create(bo, width, height, format, use_flags);
182 stride = drv_stride_from_format(format, width, 0);
183 stride = ALIGN(stride, 256);
185 drv_bo_from_format(bo, stride, height, format);
187 memset(&gem_create, 0, sizeof(gem_create));
188 gem_create.in.bo_size = bo->meta.total_size;
189 gem_create.in.alignment = 256;
190 gem_create.in.domain_flags = 0;
192 if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
193 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
195 gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
196 if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
197 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
199 /* Allocate the buffer with the preferred heap. */
200 ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
205 for (plane = 0; plane < bo->meta.num_planes; plane++)
206 bo->handles[plane].u32 = gem_create.out.handle;
208 bo->meta.format_modifiers[0] = DRM_FORMAT_MOD_LINEAR;
213 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
215 struct combination *combo;
216 combo = drv_get_combination(bo->drv, data->format, data->use_flags);
220 if (combo->metadata.tiling == TILE_TYPE_DRI)
221 return dri_bo_import(bo, data);
223 return drv_prime_bo_import(bo, data);
226 static int amdgpu_destroy_bo(struct bo *bo)
229 return dri_bo_destroy(bo);
231 return drv_gem_bo_destroy(bo);
234 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
237 union drm_amdgpu_gem_mmap gem_map;
240 return dri_bo_map(bo, vma, plane, map_flags);
242 memset(&gem_map, 0, sizeof(gem_map));
243 gem_map.in.handle = bo->handles[plane].u32;
245 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
247 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
251 vma->length = bo->meta.total_size;
253 return mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
254 gem_map.out.addr_ptr);
257 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
260 return dri_bo_unmap(bo, vma);
262 return munmap(vma->addr, vma->length);
265 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
268 union drm_amdgpu_gem_wait_idle wait_idle;
273 memset(&wait_idle, 0, sizeof(wait_idle));
274 wait_idle.in.handle = bo->handles[0].u32;
275 wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
277 ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
281 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
285 if (ret == 0 && wait_idle.out.status)
286 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
291 static uint32_t amdgpu_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
294 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
295 /* Camera subsystem requires NV12. */
296 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
297 return DRM_FORMAT_NV12;
298 /*HACK: See b/28671744 */
299 return DRM_FORMAT_XBGR8888;
300 case DRM_FORMAT_FLEX_YCbCr_420_888:
301 return DRM_FORMAT_NV12;
307 const struct backend backend_amdgpu = {
310 .close = amdgpu_close,
311 .bo_create = amdgpu_create_bo,
312 .bo_destroy = amdgpu_destroy_bo,
313 .bo_import = amdgpu_import_bo,
314 .bo_map = amdgpu_map_bo,
315 .bo_unmap = amdgpu_unmap_bo,
316 .bo_invalidate = amdgpu_bo_invalidate,
317 .resolve_format = amdgpu_resolve_format,