amdgpu.c

   1 /*
   2  * Copyright 2016 The Chromium OS Authors. All rights reserved.
   3  * Use of this source code is governed by a BSD-style license that can be
   4  * found in the LICENSE file.
   5  */
   6 #ifdef DRV_AMDGPU
   7 #include <amdgpu.h>
   8 #include <amdgpu_drm.h>
   9 #include <errno.h>
  10 #include <stdio.h>
  11 #include <stdlib.h>
  12 #include <string.h>
  13 #include <sys/mman.h>
  14 #include <xf86drm.h>
  15
  16 #include "dri.h"
  17 #include "drv_priv.h"
  18 #include "helpers.h"
  19 #include "util.h"
  20
  21 #ifdef __ANDROID__
  22 #define DRI_PATH "/vendor/lib/dri/radeonsi_dri.so"
  23 #else
  24 #define DRI_PATH "/usr/lib64/dri/radeonsi_dri.so"
  25 #endif
  26
  27 #define TILE_TYPE_LINEAR 0
  28 /* DRI backend decides tiling in this case. */
  29 #define TILE_TYPE_DRI 1
  30
  31 struct amdgpu_priv {
  32         struct dri_driver dri;
  33         int drm_version;
  34 };
  35
  36 const static uint32_t render_target_formats[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB8888,
  37                                                   DRM_FORMAT_RGB565, DRM_FORMAT_XBGR8888,
  38                                                   DRM_FORMAT_XRGB8888 };
  39
  40 const static uint32_t texture_source_formats[] = { DRM_FORMAT_GR88, DRM_FORMAT_R8, DRM_FORMAT_NV21,
  41                                                    DRM_FORMAT_NV12, DRM_FORMAT_YVU420_ANDROID };
  42
  43 static int amdgpu_init(struct driver *drv)
  44 {
  45         struct amdgpu_priv *priv;
  46         drmVersionPtr drm_version;
  47         struct format_metadata metadata;
  48         uint64_t use_flags = BO_USE_RENDER_MASK;
  49
  50         priv = calloc(1, sizeof(struct amdgpu_priv));
  51         if (!priv)
  52                 return -ENOMEM;
  53
  54         drm_version = drmGetVersion(drv_get_fd(drv));
  55         if (!drm_version) {
  56                 free(priv);
  57                 return -ENODEV;
  58         }
  59
  60         priv->drm_version = drm_version->version_minor;
  61         drmFreeVersion(drm_version);
  62
  63         drv->priv = priv;
  64
  65         if (dri_init(drv, DRI_PATH, "radeonsi")) {
  66                 free(priv);
  67                 drv->priv = NULL;
  68                 return -ENODEV;
  69         }
  70
  71         metadata.tiling = TILE_TYPE_LINEAR;
  72         metadata.priority = 1;
  73         metadata.modifier = DRM_FORMAT_MOD_LINEAR;
  74
  75         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
  76                              &metadata, use_flags);
  77
  78         drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
  79                              &metadata, BO_USE_TEXTURE_MASK);
  80
  81         /* Android CTS tests require this. */
  82         drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
  83
  84         /* Linear formats supported by display. */
  85         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  86         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
  87         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
  88
  89         /* YUV formats for camera and display. */
  90         drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
  91                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE | BO_USE_SCANOUT |
  92                                    BO_USE_HW_VIDEO_DECODER);
  93
  94         drv_modify_combination(drv, DRM_FORMAT_NV21, &metadata, BO_USE_SCANOUT);
  95
  96         /*
  97          * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
  98          * from camera.
  99          */
 100         drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
 101                                BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
 102
 103         /*
 104          * The following formats will be allocated by the DRI backend and may be potentially tiled.
 105          * Since format modifier support hasn't been implemented fully yet, it's not
 106          * possible to enumerate the different types of buffers (like i915 can).
 107          */
 108         use_flags &= ~BO_USE_RENDERSCRIPT;
 109         use_flags &= ~BO_USE_SW_WRITE_OFTEN;
 110         use_flags &= ~BO_USE_SW_READ_OFTEN;
 111         use_flags &= ~BO_USE_LINEAR;
 112
 113         metadata.tiling = TILE_TYPE_DRI;
 114         metadata.priority = 2;
 115
 116         drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
 117                              &metadata, use_flags);
 118
 119         /* Potentially tiled formats supported by display. */
 120         drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 121         drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
 122         drv_modify_combination(drv, DRM_FORMAT_XBGR8888, &metadata, BO_USE_SCANOUT);
 123         return 0;
 124 }
 125
 126 static void amdgpu_close(struct driver *drv)
 127 {
 128         dri_close(drv);
 129         free(drv->priv);
 130         drv->priv = NULL;
 131 }
 132
 133 static int amdgpu_create_bo(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
 134                             uint64_t use_flags)
 135 {
 136         int ret;
 137         uint32_t plane, stride;
 138         struct combination *combo;
 139         union drm_amdgpu_gem_create gem_create;
 140
 141         combo = drv_get_combination(bo->drv, format, use_flags);
 142         if (!combo)
 143                 return -EINVAL;
 144
 145         if (combo->metadata.tiling == TILE_TYPE_DRI) {
 146                 bool needs_alignment = false;
 147 #ifdef __ANDROID__
 148                 /*
 149                  * Currently, the gralloc API doesn't differentiate between allocation time and map
 150                  * time strides. A workaround for amdgpu DRI buffers is to always to align to 256 at
 151                  * allocation time.
 152                  *
 153                  * See b/115946221,b/117942643
 154                  */
 155                 if (use_flags & (BO_USE_SW_MASK))
 156                         needs_alignment = true;
 157 #endif
 158                 // See b/122049612
 159                 if (use_flags & (BO_USE_SCANOUT))
 160                         needs_alignment = true;
 161
 162                 if (needs_alignment) {
 163                         uint32_t bytes_per_pixel = drv_bytes_per_pixel_from_format(format, 0);
 164                         width = ALIGN(width, 256 / bytes_per_pixel);
 165                 }
 166
 167                 return dri_bo_create(bo, width, height, format, use_flags);
 168         }
 169
 170         stride = drv_stride_from_format(format, width, 0);
 171         stride = ALIGN(stride, 256);
 172
 173         drv_bo_from_format(bo, stride, height, format);
 174
 175         memset(&gem_create, 0, sizeof(gem_create));
 176         gem_create.in.bo_size = bo->total_size;
 177         gem_create.in.alignment = 256;
 178         gem_create.in.domain_flags = 0;
 179
 180         if (use_flags & (BO_USE_LINEAR | BO_USE_SW_MASK))
 181                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 182
 183         gem_create.in.domains = AMDGPU_GEM_DOMAIN_GTT;
 184         if (!(use_flags & (BO_USE_SW_READ_OFTEN | BO_USE_SCANOUT)))
 185                 gem_create.in.domain_flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 186
 187         /* Allocate the buffer with the preferred heap. */
 188         ret = drmCommandWriteRead(drv_get_fd(bo->drv), DRM_AMDGPU_GEM_CREATE, &gem_create,
 189                                   sizeof(gem_create));
 190         if (ret < 0)
 191                 return ret;
 192
 193         for (plane = 0; plane < bo->num_planes; plane++)
 194                 bo->handles[plane].u32 = gem_create.out.handle;
 195
 196         return 0;
 197 }
 198
 199 static int amdgpu_import_bo(struct bo *bo, struct drv_import_fd_data *data)
 200 {
 201         struct combination *combo;
 202         combo = drv_get_combination(bo->drv, data->format, data->use_flags);
 203         if (!combo)
 204                 return -EINVAL;
 205
 206         if (combo->metadata.tiling == TILE_TYPE_DRI)
 207                 return dri_bo_import(bo, data);
 208         else
 209                 return drv_prime_bo_import(bo, data);
 210 }
 211
 212 static int amdgpu_destroy_bo(struct bo *bo)
 213 {
 214         if (bo->priv)
 215                 return dri_bo_destroy(bo);
 216         else
 217                 return drv_gem_bo_destroy(bo);
 218 }
 219
 220 static void *amdgpu_map_bo(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
 221 {
 222         int ret;
 223         union drm_amdgpu_gem_mmap gem_map;
 224
 225         if (bo->priv)
 226                 return dri_bo_map(bo, vma, plane, map_flags);
 227
 228         memset(&gem_map, 0, sizeof(gem_map));
 229         gem_map.in.handle = bo->handles[plane].u32;
 230
 231         ret = drmIoctl(bo->drv->fd, DRM_IOCTL_AMDGPU_GEM_MMAP, &gem_map);
 232         if (ret) {
 233                 drv_log("DRM_IOCTL_AMDGPU_GEM_MMAP failed\n");
 234                 return MAP_FAILED;
 235         }
 236
 237         vma->length = bo->total_size;
 238
 239         return mmap(0, bo->total_size, drv_get_prot(map_flags), MAP_SHARED, bo->drv->fd,
 240                     gem_map.out.addr_ptr);
 241 }
 242
 243 static int amdgpu_unmap_bo(struct bo *bo, struct vma *vma)
 244 {
 245         if (bo->priv)
 246                 return dri_bo_unmap(bo, vma);
 247         else
 248                 return munmap(vma->addr, vma->length);
 249 }
 250
 251 static int amdgpu_bo_invalidate(struct bo *bo, struct mapping *mapping)
 252 {
 253         int ret;
 254         union drm_amdgpu_gem_wait_idle wait_idle;
 255
 256         if (bo->priv)
 257                 return 0;
 258
 259         memset(&wait_idle, 0, sizeof(wait_idle));
 260         wait_idle.in.handle = bo->handles[0].u32;
 261         wait_idle.in.timeout = AMDGPU_TIMEOUT_INFINITE;
 262
 263         ret = drmCommandWriteRead(bo->drv->fd, DRM_AMDGPU_GEM_WAIT_IDLE, &wait_idle,
 264                                   sizeof(wait_idle));
 265
 266         if (ret < 0) {
 267                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE failed with %d\n", ret);
 268                 return ret;
 269         }
 270
 271         if (ret == 0 && wait_idle.out.status)
 272                 drv_log("DRM_AMDGPU_GEM_WAIT_IDLE BO is busy\n");
 273
 274         return 0;
 275 }
 276
 277 static uint32_t amdgpu_resolve_format(uint32_t format, uint64_t use_flags)
 278 {
 279         switch (format) {
 280         case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
 281                 /* Camera subsystem requires NV12. */
 282                 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
 283                         return DRM_FORMAT_NV12;
 284                 /*HACK: See b/28671744 */
 285                 return DRM_FORMAT_XBGR8888;
 286         case DRM_FORMAT_FLEX_YCbCr_420_888:
 287                 return DRM_FORMAT_NV12;
 288         default:
 289                 return format;
 290         }
 291 }
 292
 293 const struct backend backend_amdgpu = {
 294         .name = "amdgpu",
 295         .init = amdgpu_init,
 296         .close = amdgpu_close,
 297         .bo_create = amdgpu_create_bo,
 298         .bo_destroy = amdgpu_destroy_bo,
 299         .bo_import = amdgpu_import_bo,
 300         .bo_map = amdgpu_map_bo,
 301         .bo_unmap = amdgpu_unmap_bo,
 302         .bo_invalidate = amdgpu_bo_invalidate,
 303         .resolve_format = amdgpu_resolve_format,
 304 };
 305
 306 #endif