2 * linux/arch/alpha/kernel/sys_sable.c
4 * Copyright (C) 1995 David A Rusling
5 * Copyright (C) 1996 Jay A Estabrook
6 * Copyright (C) 1998, 1999 Richard Henderson
8 * Code supporting the Sable, Sable-Gamma, and Lynx systems.
11 #include <linux/kernel.h>
12 #include <linux/types.h>
14 #include <linux/sched.h>
15 #include <linux/pci.h>
16 #include <linux/init.h>
18 #include <asm/ptrace.h>
19 #include <asm/system.h>
22 #include <asm/mmu_context.h>
24 #include <asm/pgtable.h>
25 #include <asm/core_t2.h>
26 #include <asm/tlbflush.h>
31 #include "machvec_impl.h"
33 DEFINE_SPINLOCK(sable_lynx_irq_lock);
35 typedef struct irq_swizzle_struct
40 /* Note mask bit is true for DISABLED irqs. */
41 unsigned long shadow_mask;
43 void (*update_irq_hw)(unsigned long bit, unsigned long mask);
44 void (*ack_irq_hw)(unsigned long bit);
48 static irq_swizzle_t *sable_lynx_irq_swizzle;
50 static void sable_lynx_init_irq(int nr_of_irqs);
52 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE)
54 /***********************************************************************/
56 * For SABLE, which is really baroque, we manage 40 IRQ's, but the
57 * hardware really only supports 24, not via normal ISA PIC,
58 * but cascaded custom 8259's, etc.
63 * Summary Registers (536/53a/53c):
65 * Bit Meaning Kernel IRQ
66 *------------------------------------------
68 * 1 NCR810 (builtin) 33
69 * 2 TULIP (builtin) 32
94 sable_update_irq_hw(unsigned long bit, unsigned long mask)
101 } else if (bit >= 8) {
110 sable_ack_irq_hw(unsigned long bit)
112 int port, val1, val2;
116 val1 = 0xE0 | (bit - 16);
118 } else if (bit >= 8) {
120 val1 = 0xE0 | (bit - 8);
124 val1 = 0xE0 | (bit - 0);
128 outb(val1, port); /* ack the slave */
129 outb(val2, 0x534); /* ack the master */
132 static irq_swizzle_t sable_irq_swizzle = {
134 -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
135 -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
136 -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 0-7 */
137 -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo EISA 8-15 */
138 2, 1, 0, 4, 5, -1, -1, -1, /* pseudo PCI */
139 -1, -1, -1, -1, -1, -1, -1, -1, /* */
140 -1, -1, -1, -1, -1, -1, -1, -1, /* */
141 -1, -1, -1, -1, -1, -1, -1, -1 /* */
144 34, 33, 32, 12, 35, 36, 1, 6, /* mask 0-7 */
145 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
146 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
147 -1, -1, -1, -1, -1, -1, -1, -1, /* */
148 -1, -1, -1, -1, -1, -1, -1, -1, /* */
149 -1, -1, -1, -1, -1, -1, -1, -1, /* */
150 -1, -1, -1, -1, -1, -1, -1, -1, /* */
151 -1, -1, -1, -1, -1, -1, -1, -1 /* */
161 outb(-1, 0x537); /* slave 0 */
162 outb(-1, 0x53b); /* slave 1 */
163 outb(-1, 0x53d); /* slave 2 */
164 outb(0x44, 0x535); /* enable cascades in master */
166 sable_lynx_irq_swizzle = &sable_irq_swizzle;
167 sable_lynx_init_irq(40);
171 * PCI Fixup configuration for ALPHA SABLE (2100).
173 * The device to slot mapping looks like:
182 * 6 PCI on board slot 0
183 * 7 PCI on board slot 1
184 * 8 PCI on board slot 2
187 * This two layered interrupt approach means that we allocate IRQ 16 and
188 * above for PCI interrupts. The IRQ relates to which bit the interrupt
189 * comes in on. This makes interrupt processing much easier.
192 * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
193 * with the values in the irq swizzling tables above.
197 sable_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
199 static char irq_tab[9][5] __initdata = {
200 /*INT INTA INTB INTC INTD */
201 { 32+0, 32+0, 32+0, 32+0, 32+0}, /* IdSel 0, TULIP */
202 { 32+1, 32+1, 32+1, 32+1, 32+1}, /* IdSel 1, SCSI */
203 { -1, -1, -1, -1, -1}, /* IdSel 2, SIO */
204 { -1, -1, -1, -1, -1}, /* IdSel 3, none */
205 { -1, -1, -1, -1, -1}, /* IdSel 4, none */
206 { -1, -1, -1, -1, -1}, /* IdSel 5, none */
207 { 32+2, 32+2, 32+2, 32+2, 32+2}, /* IdSel 6, slot 0 */
208 { 32+3, 32+3, 32+3, 32+3, 32+3}, /* IdSel 7, slot 1 */
209 { 32+4, 32+4, 32+4, 32+4, 32+4} /* IdSel 8, slot 2 */
211 long min_idsel = 0, max_idsel = 8, irqs_per_slot = 5;
212 return COMMON_TABLE_LOOKUP;
214 #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_SABLE) */
216 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
218 /***********************************************************************/
219 /* LYNX hardware specifics
222 * For LYNX, which is also baroque, we manage 64 IRQs, via a custom IC.
224 * Bit Meaning Kernel IRQ
225 *------------------------------------------
254 *28 NCR810 (builtin) 28
258 *32 PCI 0 slot 4 A primary bus 32
259 *33 PCI 0 slot 4 B primary bus 33
260 *34 PCI 0 slot 4 C primary bus 34
261 *35 PCI 0 slot 4 D primary bus
262 *36 PCI 0 slot 5 A primary bus
263 *37 PCI 0 slot 5 B primary bus
264 *38 PCI 0 slot 5 C primary bus
265 *39 PCI 0 slot 5 D primary bus
266 *40 PCI 0 slot 6 A primary bus
267 *41 PCI 0 slot 6 B primary bus
268 *42 PCI 0 slot 6 C primary bus
269 *43 PCI 0 slot 6 D primary bus
270 *44 PCI 0 slot 7 A primary bus
271 *45 PCI 0 slot 7 B primary bus
272 *46 PCI 0 slot 7 C primary bus
273 *47 PCI 0 slot 7 D primary bus
274 *48 PCI 0 slot 0 A secondary bus
275 *49 PCI 0 slot 0 B secondary bus
276 *50 PCI 0 slot 0 C secondary bus
277 *51 PCI 0 slot 0 D secondary bus
278 *52 PCI 0 slot 1 A secondary bus
279 *53 PCI 0 slot 1 B secondary bus
280 *54 PCI 0 slot 1 C secondary bus
281 *55 PCI 0 slot 1 D secondary bus
282 *56 PCI 0 slot 2 A secondary bus
283 *57 PCI 0 slot 2 B secondary bus
284 *58 PCI 0 slot 2 C secondary bus
285 *59 PCI 0 slot 2 D secondary bus
286 *60 PCI 0 slot 3 A secondary bus
287 *61 PCI 0 slot 3 B secondary bus
288 *62 PCI 0 slot 3 C secondary bus
289 *63 PCI 0 slot 3 D secondary bus
293 lynx_update_irq_hw(unsigned long bit, unsigned long mask)
296 * Write the AIR register on the T3/T4 with the
297 * address of the IC mask register (offset 0x40)
299 *(vulp)T2_AIR = 0x40;
301 *(vulp)T2_AIR; /* re-read to force write */
303 *(vulp)T2_DIR = mask;
309 lynx_ack_irq_hw(unsigned long bit)
311 *(vulp)T2_VAR = (u_long) bit;
316 static irq_swizzle_t lynx_irq_swizzle = {
318 -1, 6, -1, 8, 15, 12, 7, 9, /* pseudo PIC 0-7 */
319 -1, 16, 17, 18, 3, -1, 21, 22, /* pseudo PIC 8-15 */
320 -1, -1, -1, -1, -1, -1, -1, -1, /* pseudo */
321 -1, -1, -1, -1, 28, -1, -1, -1, /* pseudo */
322 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
323 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
324 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
325 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
328 -1, -1, -1, 12, -1, -1, 1, 6, /* mask 0-7 */
329 3, 7, -1, -1, 5, -1, -1, 4, /* mask 8-15 */
330 9, 10, 11, -1, -1, 14, 15, -1, /* mask 16-23 */
331 -1, -1, -1, -1, 28, -1, -1, -1, /* mask 24-31 */
332 32, 33, 34, 35, 36, 37, 38, 39, /* mask 32-39 */
333 40, 41, 42, 43, 44, 45, 46, 47, /* mask 40-47 */
334 48, 49, 50, 51, 52, 53, 54, 55, /* mask 48-55 */
335 56, 57, 58, 59, 60, 61, 62, 63 /* mask 56-63 */
345 sable_lynx_irq_swizzle = &lynx_irq_swizzle;
346 sable_lynx_init_irq(64);
350 * PCI Fixup configuration for ALPHA LYNX (2100A)
352 * The device to slot mapping looks like:
359 * 4 NCR 810 (Demi-Lynx only)
361 * 6 PCI on board slot 4
362 * 7 PCI on board slot 5
363 * 8 PCI on board slot 6
364 * 9 PCI on board slot 7
366 * And behind the PPB we have:
368 * 11 PCI on board slot 0
369 * 12 PCI on board slot 1
370 * 13 PCI on board slot 2
371 * 14 PCI on board slot 3
374 * NOTE: the IRQ assignments below are arbitrary, but need to be consistent
375 * with the values in the irq swizzling tables above.
379 lynx_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
381 static char irq_tab[19][5] __initdata = {
382 /*INT INTA INTB INTC INTD */
383 { -1, -1, -1, -1, -1}, /* IdSel 13, PCEB */
384 { -1, -1, -1, -1, -1}, /* IdSel 14, PPB */
385 { 28, 28, 28, 28, 28}, /* IdSel 15, NCR demi */
386 { -1, -1, -1, -1, -1}, /* IdSel 16, none */
387 { 32, 32, 33, 34, 35}, /* IdSel 17, slot 4 */
388 { 36, 36, 37, 38, 39}, /* IdSel 18, slot 5 */
389 { 40, 40, 41, 42, 43}, /* IdSel 19, slot 6 */
390 { 44, 44, 45, 46, 47}, /* IdSel 20, slot 7 */
391 { -1, -1, -1, -1, -1}, /* IdSel 22, none */
392 /* The following are actually behind the PPB. */
393 { -1, -1, -1, -1, -1}, /* IdSel 16 none */
394 { 28, 28, 28, 28, 28}, /* IdSel 17 NCR lynx */
395 { -1, -1, -1, -1, -1}, /* IdSel 18 none */
396 { -1, -1, -1, -1, -1}, /* IdSel 19 none */
397 { -1, -1, -1, -1, -1}, /* IdSel 20 none */
398 { -1, -1, -1, -1, -1}, /* IdSel 21 none */
399 { 48, 48, 49, 50, 51}, /* IdSel 22 slot 0 */
400 { 52, 52, 53, 54, 55}, /* IdSel 23 slot 1 */
401 { 56, 56, 57, 58, 59}, /* IdSel 24 slot 2 */
402 { 60, 60, 61, 62, 63} /* IdSel 25 slot 3 */
404 const long min_idsel = 2, max_idsel = 20, irqs_per_slot = 5;
405 return COMMON_TABLE_LOOKUP;
409 lynx_swizzle(struct pci_dev *dev, u8 *pinp)
411 int slot, pin = *pinp;
413 if (dev->bus->number == 0) {
414 slot = PCI_SLOT(dev->devfn);
416 /* Check for the built-in bridge */
417 else if (PCI_SLOT(dev->bus->self->devfn) == 3) {
418 slot = PCI_SLOT(dev->devfn) + 11;
422 /* Must be a card-based bridge. */
424 if (PCI_SLOT(dev->bus->self->devfn) == 3) {
425 slot = PCI_SLOT(dev->devfn) + 11;
428 pin = pci_swizzle_interrupt_pin(dev, pin);
430 /* Move up the chain of bridges. */
431 dev = dev->bus->self;
432 /* Slot of the next bridge. */
433 slot = PCI_SLOT(dev->devfn);
434 } while (dev->bus->self);
440 #endif /* defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX) */
442 /***********************************************************************/
443 /* GENERIC irq routines */
446 sable_lynx_enable_irq(struct irq_data *d)
448 unsigned long bit, mask;
450 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
451 spin_lock(&sable_lynx_irq_lock);
452 mask = sable_lynx_irq_swizzle->shadow_mask &= ~(1UL << bit);
453 sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
454 spin_unlock(&sable_lynx_irq_lock);
456 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
457 __func__, mask, bit, irq);
462 sable_lynx_disable_irq(struct irq_data *d)
464 unsigned long bit, mask;
466 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
467 spin_lock(&sable_lynx_irq_lock);
468 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
469 sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
470 spin_unlock(&sable_lynx_irq_lock);
472 printk("%s: mask 0x%lx bit 0x%lx irq 0x%x\n",
473 __func__, mask, bit, irq);
478 sable_lynx_mask_and_ack_irq(struct irq_data *d)
480 unsigned long bit, mask;
482 bit = sable_lynx_irq_swizzle->irq_to_mask[d->irq];
483 spin_lock(&sable_lynx_irq_lock);
484 mask = sable_lynx_irq_swizzle->shadow_mask |= 1UL << bit;
485 sable_lynx_irq_swizzle->update_irq_hw(bit, mask);
486 sable_lynx_irq_swizzle->ack_irq_hw(bit);
487 spin_unlock(&sable_lynx_irq_lock);
490 static struct irq_chip sable_lynx_irq_type = {
491 .name = "SABLE/LYNX",
492 .irq_unmask = sable_lynx_enable_irq,
493 .irq_mask = sable_lynx_disable_irq,
494 .irq_mask_ack = sable_lynx_mask_and_ack_irq,
498 sable_lynx_srm_device_interrupt(unsigned long vector)
500 /* Note that the vector reported by the SRM PALcode corresponds
501 to the interrupt mask bits, but we have to manage via the
502 so-called legacy IRQs for many common devices. */
506 bit = (vector - 0x800) >> 4;
507 irq = sable_lynx_irq_swizzle->mask_to_irq[bit];
509 printk("%s: vector 0x%lx bit 0x%x irq 0x%x\n",
510 __func__, vector, bit, irq);
516 sable_lynx_init_irq(int nr_of_irqs)
520 for (i = 0; i < nr_of_irqs; ++i) {
521 set_irq_chip_and_handler(i, &sable_lynx_irq_type,
523 irq_set_status_flags(i, IRQ_LEVEL);
526 common_init_isa_dma();
530 sable_lynx_init_pci(void)
535 /*****************************************************************/
539 * In order that T2_HAE_ADDRESS should be a constant, we play
540 * these games with GAMMA_BIAS.
543 #if defined(CONFIG_ALPHA_GENERIC) || \
544 (defined(CONFIG_ALPHA_SABLE) && !defined(CONFIG_ALPHA_GAMMA))
547 struct alpha_machine_vector sable_mv __initmv = {
548 .vector_name = "Sable",
552 .machine_check = t2_machine_check,
553 .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
554 .min_io_address = EISA_DEFAULT_IO_BASE,
555 .min_mem_address = T2_DEFAULT_MEM_BASE,
558 .device_interrupt = sable_lynx_srm_device_interrupt,
560 .init_arch = t2_init_arch,
561 .init_irq = sable_init_irq,
562 .init_rtc = common_init_rtc,
563 .init_pci = sable_lynx_init_pci,
564 .kill_arch = t2_kill_arch,
565 .pci_map_irq = sable_map_irq,
566 .pci_swizzle = common_swizzle,
573 #endif /* GENERIC || (SABLE && !GAMMA) */
575 #if defined(CONFIG_ALPHA_GENERIC) || \
576 (defined(CONFIG_ALPHA_SABLE) && defined(CONFIG_ALPHA_GAMMA))
578 #define GAMMA_BIAS _GAMMA_BIAS
579 struct alpha_machine_vector sable_gamma_mv __initmv = {
580 .vector_name = "Sable-Gamma",
584 .machine_check = t2_machine_check,
585 .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
586 .min_io_address = EISA_DEFAULT_IO_BASE,
587 .min_mem_address = T2_DEFAULT_MEM_BASE,
590 .device_interrupt = sable_lynx_srm_device_interrupt,
592 .init_arch = t2_init_arch,
593 .init_irq = sable_init_irq,
594 .init_rtc = common_init_rtc,
595 .init_pci = sable_lynx_init_pci,
596 .kill_arch = t2_kill_arch,
597 .pci_map_irq = sable_map_irq,
598 .pci_swizzle = common_swizzle,
601 .gamma_bias = _GAMMA_BIAS
604 ALIAS_MV(sable_gamma)
605 #endif /* GENERIC || (SABLE && GAMMA) */
607 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_LYNX)
609 #define GAMMA_BIAS _GAMMA_BIAS
610 struct alpha_machine_vector lynx_mv __initmv = {
611 .vector_name = "Lynx",
615 .machine_check = t2_machine_check,
616 .max_isa_dma_address = ALPHA_SABLE_MAX_ISA_DMA_ADDRESS,
617 .min_io_address = EISA_DEFAULT_IO_BASE,
618 .min_mem_address = T2_DEFAULT_MEM_BASE,
621 .device_interrupt = sable_lynx_srm_device_interrupt,
623 .init_arch = t2_init_arch,
624 .init_irq = lynx_init_irq,
625 .init_rtc = common_init_rtc,
626 .init_pci = sable_lynx_init_pci,
627 .kill_arch = t2_kill_arch,
628 .pci_map_irq = lynx_map_irq,
629 .pci_swizzle = lynx_swizzle,
632 .gamma_bias = _GAMMA_BIAS
636 #endif /* GENERIC || LYNX */