arch/arc/kernel/setup.c

   1 /*
   2  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/seq_file.h>
  10 #include <linux/fs.h>
  11 #include <linux/delay.h>
  12 #include <linux/root_dev.h>
  13 #include <linux/clk.h>
  14 #include <linux/clk-provider.h>
  15 #include <linux/clocksource.h>
  16 #include <linux/console.h>
  17 #include <linux/module.h>
  18 #include <linux/cpu.h>
  19 #include <linux/of_fdt.h>
  20 #include <linux/of.h>
  21 #include <linux/cache.h>
  22 #include <uapi/linux/mount.h>
  23 #include <asm/sections.h>
  24 #include <asm/arcregs.h>
  25 #include <asm/tlb.h>
  26 #include <asm/setup.h>
  27 #include <asm/page.h>
  28 #include <asm/irq.h>
  29 #include <asm/unwind.h>
  30 #include <asm/mach_desc.h>
  31 #include <asm/smp.h>
  32
  33 #define FIX_PTR(x)  __asm__ __volatile__(";" : "+r"(x))
  34
  35 unsigned int intr_to_DE_cnt;
  36
  37 /* Part of U-boot ABI: see head.S */
  38 int __initdata uboot_tag;
  39 char __initdata *uboot_arg;
  40
  41 const struct machine_desc *machine_desc;
  42
  43 struct task_struct *_current_task[NR_CPUS];     /* For stack switching */
  44
  45 struct cpuinfo_arc cpuinfo_arc700[NR_CPUS];
  46
  47 static const struct id_to_str arc_cpu_rel[] = {
  48 #ifdef CONFIG_ISA_ARCOMPACT
  49         { 0x34, "R4.10"},
  50         { 0x35, "R4.11"},
  51 #else
  52         { 0x51, "R2.0" },
  53         { 0x52, "R2.1" },
  54         { 0x53, "R3.0" },
  55         { 0x54, "R3.10a" },
  56 #endif
  57         { 0x00, NULL   }
  58 };
  59
  60 static const struct id_to_str arc_cpu_nm[] = {
  61 #ifdef CONFIG_ISA_ARCOMPACT
  62         { 0x20, "ARC 600"   },
  63         { 0x30, "ARC 770"   },  /* 750 identified seperately */
  64 #else
  65         { 0x40, "ARC EM"  },
  66         { 0x50, "ARC HS38"  },
  67         { 0x54, "ARC HS48"  },
  68 #endif
  69         { 0x00, "Unknown"   }
  70 };
  71
  72 static void read_decode_ccm_bcr(struct cpuinfo_arc *cpu)
  73 {
  74         if (is_isa_arcompact()) {
  75                 struct bcr_iccm_arcompact iccm;
  76                 struct bcr_dccm_arcompact dccm;
  77
  78                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  79                 if (iccm.ver) {
  80                         cpu->iccm.sz = 4096 << iccm.sz; /* 8K to 512K */
  81                         cpu->iccm.base_addr = iccm.base << 16;
  82                 }
  83
  84                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
  85                 if (dccm.ver) {
  86                         unsigned long base;
  87                         cpu->dccm.sz = 2048 << dccm.sz; /* 2K to 256K */
  88
  89                         base = read_aux_reg(ARC_REG_DCCM_BASE_BUILD);
  90                         cpu->dccm.base_addr = base & ~0xF;
  91                 }
  92         } else {
  93                 struct bcr_iccm_arcv2 iccm;
  94                 struct bcr_dccm_arcv2 dccm;
  95                 unsigned long region;
  96
  97                 READ_BCR(ARC_REG_ICCM_BUILD, iccm);
  98                 if (iccm.ver) {
  99                         cpu->iccm.sz = 256 << iccm.sz00;        /* 512B to 16M */
 100                         if (iccm.sz00 == 0xF && iccm.sz01 > 0)
 101                                 cpu->iccm.sz <<= iccm.sz01;
 102
 103                         region = read_aux_reg(ARC_REG_AUX_ICCM);
 104                         cpu->iccm.base_addr = region & 0xF0000000;
 105                 }
 106
 107                 READ_BCR(ARC_REG_DCCM_BUILD, dccm);
 108                 if (dccm.ver) {
 109                         cpu->dccm.sz = 256 << dccm.sz0;
 110                         if (dccm.sz0 == 0xF && dccm.sz1 > 0)
 111                                 cpu->dccm.sz <<= dccm.sz1;
 112
 113                         region = read_aux_reg(ARC_REG_AUX_DCCM);
 114                         cpu->dccm.base_addr = region & 0xF0000000;
 115                 }
 116         }
 117 }
 118
 119 static void read_arc_build_cfg_regs(void)
 120 {
 121         struct bcr_timer timer;
 122         struct bcr_generic bcr;
 123         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 124         const struct id_to_str *tbl;
 125         struct bcr_isa_arcv2 isa;
 126         struct bcr_actionpoint ap;
 127
 128         FIX_PTR(cpu);
 129
 130         READ_BCR(AUX_IDENTITY, cpu->core);
 131
 132         for (tbl = &arc_cpu_rel[0]; tbl->id != 0; tbl++) {
 133                 if (cpu->core.family == tbl->id) {
 134                         cpu->details = tbl->str;
 135                         break;
 136                 }
 137         }
 138
 139         for (tbl = &arc_cpu_nm[0]; tbl->id != 0; tbl++) {
 140                 if ((cpu->core.family & 0xF4) == tbl->id)
 141                         break;
 142         }
 143         cpu->name = tbl->str;
 144
 145         READ_BCR(ARC_REG_TIMERS_BCR, timer);
 146         cpu->extn.timer0 = timer.t0;
 147         cpu->extn.timer1 = timer.t1;
 148         cpu->extn.rtc = timer.rtc;
 149
 150         cpu->vec_base = read_aux_reg(AUX_INTR_VEC_BASE);
 151
 152         READ_BCR(ARC_REG_MUL_BCR, cpu->extn_mpy);
 153
 154         cpu->extn.norm = read_aux_reg(ARC_REG_NORM_BCR) > 1 ? 1 : 0; /* 2,3 */
 155         cpu->extn.barrel = read_aux_reg(ARC_REG_BARREL_BCR) > 1 ? 1 : 0; /* 2,3 */
 156         cpu->extn.swap = read_aux_reg(ARC_REG_SWAP_BCR) ? 1 : 0;        /* 1,3 */
 157         cpu->extn.crc = read_aux_reg(ARC_REG_CRC_BCR) ? 1 : 0;
 158         cpu->extn.minmax = read_aux_reg(ARC_REG_MIXMAX_BCR) > 1 ? 1 : 0; /* 2 */
 159         cpu->extn.swape = (cpu->core.family >= 0x34) ? 1 :
 160                                 IS_ENABLED(CONFIG_ARC_HAS_SWAPE);
 161
 162         READ_BCR(ARC_REG_XY_MEM_BCR, cpu->extn_xymem);
 163
 164         /* Read CCM BCRs for boot reporting even if not enabled in Kconfig */
 165         read_decode_ccm_bcr(cpu);
 166
 167         read_decode_mmu_bcr();
 168         read_decode_cache_bcr();
 169
 170         if (is_isa_arcompact()) {
 171                 struct bcr_fp_arcompact sp, dp;
 172                 struct bcr_bpu_arcompact bpu;
 173
 174                 READ_BCR(ARC_REG_FP_BCR, sp);
 175                 READ_BCR(ARC_REG_DPFP_BCR, dp);
 176                 cpu->extn.fpu_sp = sp.ver ? 1 : 0;
 177                 cpu->extn.fpu_dp = dp.ver ? 1 : 0;
 178
 179                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 180                 cpu->bpu.ver = bpu.ver;
 181                 cpu->bpu.full = bpu.fam ? 1 : 0;
 182                 if (bpu.ent) {
 183                         cpu->bpu.num_cache = 256 << (bpu.ent - 1);
 184                         cpu->bpu.num_pred = 256 << (bpu.ent - 1);
 185                 }
 186         } else {
 187                 struct bcr_fp_arcv2 spdp;
 188                 struct bcr_bpu_arcv2 bpu;
 189
 190                 READ_BCR(ARC_REG_FP_V2_BCR, spdp);
 191                 cpu->extn.fpu_sp = spdp.sp ? 1 : 0;
 192                 cpu->extn.fpu_dp = spdp.dp ? 1 : 0;
 193
 194                 READ_BCR(ARC_REG_BPU_BCR, bpu);
 195                 cpu->bpu.ver = bpu.ver;
 196                 cpu->bpu.full = bpu.ft;
 197                 cpu->bpu.num_cache = 256 << bpu.bce;
 198                 cpu->bpu.num_pred = 2048 << bpu.pte;
 199                 cpu->bpu.ret_stk = 4 << bpu.rse;
 200
 201                 if (cpu->core.family >= 0x54) {
 202                         unsigned int exec_ctrl;
 203
 204                         READ_BCR(AUX_EXEC_CTRL, exec_ctrl);
 205                         cpu->extn.dual_enb = !(exec_ctrl & 1);
 206
 207                         /* dual issue always present for this core */
 208                         cpu->extn.dual = 1;
 209                 }
 210         }
 211
 212         READ_BCR(ARC_REG_AP_BCR, ap);
 213         if (ap.ver) {
 214                 cpu->extn.ap_num = 2 << ap.num;
 215                 cpu->extn.ap_full = !ap.min;
 216         }
 217
 218         READ_BCR(ARC_REG_SMART_BCR, bcr);
 219         cpu->extn.smart = bcr.ver ? 1 : 0;
 220
 221         READ_BCR(ARC_REG_RTT_BCR, bcr);
 222         cpu->extn.rtt = bcr.ver ? 1 : 0;
 223
 224         READ_BCR(ARC_REG_ISA_CFG_BCR, isa);
 225
 226         /* some hacks for lack of feature BCR info in old ARC700 cores */
 227         if (is_isa_arcompact()) {
 228                 if (!isa.ver)   /* ISA BCR absent, use Kconfig info */
 229                         cpu->isa.atomic = IS_ENABLED(CONFIG_ARC_HAS_LLSC);
 230                 else {
 231                         /* ARC700_BUILD only has 2 bits of isa info */
 232                         struct bcr_generic bcr = *(struct bcr_generic *)&isa;
 233                         cpu->isa.atomic = bcr.info & 1;
 234                 }
 235
 236                 cpu->isa.be = IS_ENABLED(CONFIG_CPU_BIG_ENDIAN);
 237
 238                  /* there's no direct way to distinguish 750 vs. 770 */
 239                 if (unlikely(cpu->core.family < 0x34 || cpu->mmu.ver < 3))
 240                         cpu->name = "ARC750";
 241         } else {
 242                 cpu->isa = isa;
 243         }
 244 }
 245
 246 static char *arc_cpu_mumbojumbo(int cpu_id, char *buf, int len)
 247 {
 248         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 249         struct bcr_identity *core = &cpu->core;
 250         int i, n = 0, ua = 0;
 251
 252         FIX_PTR(cpu);
 253
 254         n += scnprintf(buf + n, len - n,
 255                        "\nIDENTITY\t: ARCVER [%#02x] ARCNUM [%#02x] CHIPID [%#4x]\n",
 256                        core->family, core->cpu_id, core->chip_id);
 257
 258         n += scnprintf(buf + n, len - n, "processor [%d]\t: %s %s (%s ISA) %s%s%s\n",
 259                        cpu_id, cpu->name, cpu->details,
 260                        is_isa_arcompact() ? "ARCompact" : "ARCv2",
 261                        IS_AVAIL1(cpu->isa.be, "[Big-Endian]"),
 262                        IS_AVAIL3(cpu->extn.dual, cpu->extn.dual_enb, " Dual-Issue "));
 263
 264         n += scnprintf(buf + n, len - n, "Timers\t\t: %s%s%s%s%s%s\nISA Extn\t: ",
 265                        IS_AVAIL1(cpu->extn.timer0, "Timer0 "),
 266                        IS_AVAIL1(cpu->extn.timer1, "Timer1 "),
 267                        IS_AVAIL2(cpu->extn.rtc, "RTC [UP 64-bit] ", CONFIG_ARC_TIMERS_64BIT),
 268                        IS_AVAIL2(cpu->extn.gfrc, "GFRC [SMP 64-bit] ", CONFIG_ARC_TIMERS_64BIT));
 269
 270 #ifdef __ARC_UNALIGNED__
 271         ua = 1;
 272 #endif
 273         n += i = scnprintf(buf + n, len - n, "%s%s%s%s%s%s",
 274                            IS_AVAIL2(cpu->isa.atomic, "atomic ", CONFIG_ARC_HAS_LLSC),
 275                            IS_AVAIL2(cpu->isa.ldd, "ll64 ", CONFIG_ARC_HAS_LL64),
 276                            IS_AVAIL1(cpu->isa.unalign, "unalign "), IS_USED_RUN(ua));
 277
 278         if (i)
 279                 n += scnprintf(buf + n, len - n, "\n\t\t: ");
 280
 281         if (cpu->extn_mpy.ver) {
 282                 if (cpu->extn_mpy.ver <= 0x2) { /* ARCompact */
 283                         n += scnprintf(buf + n, len - n, "mpy ");
 284                 } else {
 285                         int opt = 2;    /* stock MPY/MPYH */
 286
 287                         if (cpu->extn_mpy.dsp)  /* OPT 7-9 */
 288                                 opt = cpu->extn_mpy.dsp + 6;
 289
 290                         n += scnprintf(buf + n, len - n, "mpy[opt %d] ", opt);
 291                 }
 292         }
 293
 294         n += scnprintf(buf + n, len - n, "%s%s%s%s%s%s%s%s\n",
 295                        IS_AVAIL1(cpu->isa.div_rem, "div_rem "),
 296                        IS_AVAIL1(cpu->extn.norm, "norm "),
 297                        IS_AVAIL1(cpu->extn.barrel, "barrel-shift "),
 298                        IS_AVAIL1(cpu->extn.swap, "swap "),
 299                        IS_AVAIL1(cpu->extn.minmax, "minmax "),
 300                        IS_AVAIL1(cpu->extn.crc, "crc "),
 301                        IS_AVAIL2(cpu->extn.swape, "swape", CONFIG_ARC_HAS_SWAPE));
 302
 303         if (cpu->bpu.ver)
 304                 n += scnprintf(buf + n, len - n,
 305                               "BPU\t\t: %s%s match, cache:%d, Predict Table:%d Return stk: %d",
 306                               IS_AVAIL1(cpu->bpu.full, "full"),
 307                               IS_AVAIL1(!cpu->bpu.full, "partial"),
 308                               cpu->bpu.num_cache, cpu->bpu.num_pred, cpu->bpu.ret_stk);
 309
 310         if (is_isa_arcv2()) {
 311                 struct bcr_lpb lpb;
 312
 313                 READ_BCR(ARC_REG_LPB_BUILD, lpb);
 314                 if (lpb.ver) {
 315                         unsigned int ctl;
 316                         ctl = read_aux_reg(ARC_REG_LPB_CTRL);
 317
 318                         n += scnprintf(buf + n, len - n, " Loop Buffer:%d %s",
 319                                 lpb.entries,
 320                                 IS_DISABLED_RUN(!ctl));
 321                 }
 322         }
 323
 324         n += scnprintf(buf + n, len - n, "\n");
 325         return buf;
 326 }
 327
 328 static char *arc_extn_mumbojumbo(int cpu_id, char *buf, int len)
 329 {
 330         int n = 0;
 331         struct cpuinfo_arc *cpu = &cpuinfo_arc700[cpu_id];
 332
 333         FIX_PTR(cpu);
 334
 335         n += scnprintf(buf + n, len - n, "Vector Table\t: %#x\n", cpu->vec_base);
 336
 337         if (cpu->extn.fpu_sp || cpu->extn.fpu_dp)
 338                 n += scnprintf(buf + n, len - n, "FPU\t\t: %s%s\n",
 339                                IS_AVAIL1(cpu->extn.fpu_sp, "SP "),
 340                                IS_AVAIL1(cpu->extn.fpu_dp, "DP "));
 341
 342         if (cpu->extn.ap_num | cpu->extn.smart | cpu->extn.rtt) {
 343                 n += scnprintf(buf + n, len - n, "DEBUG\t\t: %s%s",
 344                                IS_AVAIL1(cpu->extn.smart, "smaRT "),
 345                                IS_AVAIL1(cpu->extn.rtt, "RTT "));
 346                 if (cpu->extn.ap_num) {
 347                         n += scnprintf(buf + n, len - n, "ActionPoint %d/%s",
 348                                        cpu->extn.ap_num,
 349                                        cpu->extn.ap_full ? "full":"min");
 350                 }
 351                 n += scnprintf(buf + n, len - n, "\n");
 352         }
 353
 354         if (cpu->dccm.sz || cpu->iccm.sz)
 355                 n += scnprintf(buf + n, len - n, "Extn [CCM]\t: DCCM @ %x, %d KB / ICCM: @ %x, %d KB\n",
 356                                cpu->dccm.base_addr, TO_KB(cpu->dccm.sz),
 357                                cpu->iccm.base_addr, TO_KB(cpu->iccm.sz));
 358
 359         if (is_isa_arcv2()) {
 360
 361                 /* Error Protection: ECC/Parity */
 362                 struct bcr_erp erp;
 363                 READ_BCR(ARC_REG_ERP_BUILD, erp);
 364
 365                 if (erp.ver) {
 366                         struct  ctl_erp ctl;
 367                         READ_BCR(ARC_REG_ERP_CTRL, ctl);
 368
 369                         /* inverted bits: 0 means enabled */
 370                         n += scnprintf(buf + n, len - n, "Extn [ECC]\t: %s%s%s%s%s%s\n",
 371                                 IS_AVAIL3(erp.ic,  !ctl.dpi, "IC "),
 372                                 IS_AVAIL3(erp.dc,  !ctl.dpd, "DC "),
 373                                 IS_AVAIL3(erp.mmu, !ctl.mpd, "MMU "));
 374                 }
 375         }
 376
 377         n += scnprintf(buf + n, len - n, "OS ABI [v%d]\t: %s\n",
 378                         EF_ARC_OSABI_CURRENT >> 8,
 379                         EF_ARC_OSABI_CURRENT == EF_ARC_OSABI_V3 ?
 380                         "no-legacy-syscalls" : "64-bit data any register aligned");
 381
 382         return buf;
 383 }
 384
 385 static void arc_chk_core_config(void)
 386 {
 387         struct cpuinfo_arc *cpu = &cpuinfo_arc700[smp_processor_id()];
 388         int saved = 0, present = 0;
 389         char *opt_nm = NULL;
 390
 391         if (!cpu->extn.timer0)
 392                 panic("Timer0 is not present!\n");
 393
 394         if (!cpu->extn.timer1)
 395                 panic("Timer1 is not present!\n");
 396
 397 #ifdef CONFIG_ARC_HAS_DCCM
 398         /*
 399          * DCCM can be arbit placed in hardware.
 400          * Make sure it's placement/sz matches what Linux is built with
 401          */
 402         if ((unsigned int)__arc_dccm_base != cpu->dccm.base_addr)
 403                 panic("Linux built with incorrect DCCM Base address\n");
 404
 405         if (CONFIG_ARC_DCCM_SZ != cpu->dccm.sz)
 406                 panic("Linux built with incorrect DCCM Size\n");
 407 #endif
 408
 409 #ifdef CONFIG_ARC_HAS_ICCM
 410         if (CONFIG_ARC_ICCM_SZ != cpu->iccm.sz)
 411                 panic("Linux built with incorrect ICCM Size\n");
 412 #endif
 413
 414         /*
 415          * FP hardware/software config sanity
 416          * -If hardware present, kernel needs to save/restore FPU state
 417          * -If not, it will crash trying to save/restore the non-existant regs
 418          */
 419
 420         if (is_isa_arcompact()) {
 421                 opt_nm = "CONFIG_ARC_FPU_SAVE_RESTORE";
 422                 saved = IS_ENABLED(CONFIG_ARC_FPU_SAVE_RESTORE);
 423
 424                 /* only DPDP checked since SP has no arch visible regs */
 425                 present = cpu->extn.fpu_dp;
 426         } else {
 427                 opt_nm = "CONFIG_ARC_HAS_ACCL_REGS";
 428                 saved = IS_ENABLED(CONFIG_ARC_HAS_ACCL_REGS);
 429
 430                 /* Accumulator Low:High pair (r58:59) present if DSP MPY or FPU */
 431                 present = cpu->extn_mpy.dsp | cpu->extn.fpu_sp | cpu->extn.fpu_dp;
 432         }
 433
 434         if (present && !saved)
 435                 pr_warn("Enable %s for working apps\n", opt_nm);
 436         else if (!present && saved)
 437                 panic("Disable %s, hardware NOT present\n", opt_nm);
 438 }
 439
 440 /*
 441  * Initialize and setup the processor core
 442  * This is called by all the CPUs thus should not do special case stuff
 443  *    such as only for boot CPU etc
 444  */
 445
 446 void setup_processor(void)
 447 {
 448         char str[512];
 449         int cpu_id = smp_processor_id();
 450
 451         read_arc_build_cfg_regs();
 452         arc_init_IRQ();
 453
 454         pr_info("%s", arc_cpu_mumbojumbo(cpu_id, str, sizeof(str)));
 455
 456         arc_mmu_init();
 457         arc_cache_init();
 458
 459         pr_info("%s", arc_extn_mumbojumbo(cpu_id, str, sizeof(str)));
 460         pr_info("%s", arc_platform_smp_cpuinfo());
 461
 462         arc_chk_core_config();
 463 }
 464
 465 static inline bool uboot_arg_invalid(unsigned long addr)
 466 {
 467         /*
 468          * Check that it is a untranslated address (although MMU is not enabled
 469          * yet, it being a high address ensures this is not by fluke)
 470          */
 471         if (addr < PAGE_OFFSET)
 472                 return true;
 473
 474         /* Check that address doesn't clobber resident kernel image */
 475         return addr >= (unsigned long)_stext && addr <= (unsigned long)_end;
 476 }
 477
 478 #define IGNORE_ARGS             "Ignore U-boot args: "
 479
 480 /* uboot_tag values for U-boot - kernel ABI revision 0; see head.S */
 481 #define UBOOT_TAG_NONE          0
 482 #define UBOOT_TAG_CMDLINE       1
 483 #define UBOOT_TAG_DTB           2
 484
 485 void __init handle_uboot_args(void)
 486 {
 487         bool use_embedded_dtb = true;
 488         bool append_cmdline = false;
 489
 490 #ifdef CONFIG_ARC_UBOOT_SUPPORT
 491         /* check that we know this tag */
 492         if (uboot_tag != UBOOT_TAG_NONE &&
 493             uboot_tag != UBOOT_TAG_CMDLINE &&
 494             uboot_tag != UBOOT_TAG_DTB) {
 495                 pr_warn(IGNORE_ARGS "invalid uboot tag: '%08x'\n", uboot_tag);
 496                 goto ignore_uboot_args;
 497         }
 498
 499         if (uboot_tag != UBOOT_TAG_NONE &&
 500             uboot_arg_invalid((unsigned long)uboot_arg)) {
 501                 pr_warn(IGNORE_ARGS "invalid uboot arg: '%px'\n", uboot_arg);
 502                 goto ignore_uboot_args;
 503         }
 504
 505         /* see if U-boot passed an external Device Tree blob */
 506         if (uboot_tag == UBOOT_TAG_DTB) {
 507                 machine_desc = setup_machine_fdt((void *)uboot_arg);
 508
 509                 /* external Device Tree blob is invalid - use embedded one */
 510                 use_embedded_dtb = !machine_desc;
 511         }
 512
 513         if (uboot_tag == UBOOT_TAG_CMDLINE)
 514                 append_cmdline = true;
 515
 516 ignore_uboot_args:
 517 #endif
 518
 519         if (use_embedded_dtb) {
 520                 machine_desc = setup_machine_fdt(__dtb_start);
 521                 if (!machine_desc)
 522                         panic("Embedded DT invalid\n");
 523         }
 524
 525         /*
 526          * NOTE: @boot_command_line is populated by setup_machine_fdt() so this
 527          * append processing can only happen after.
 528          */
 529         if (append_cmdline) {
 530                 /* Ensure a whitespace between the 2 cmdlines */
 531                 strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
 532                 strlcat(boot_command_line, uboot_arg, COMMAND_LINE_SIZE);
 533         }
 534 }
 535
 536 void __init setup_arch(char **cmdline_p)
 537 {
 538         handle_uboot_args();
 539
 540         /* Save unparsed command line copy for /proc/cmdline */
 541         *cmdline_p = boot_command_line;
 542
 543         /* To force early parsing of things like mem=xxx */
 544         parse_early_param();
 545
 546         /* Platform/board specific: e.g. early console registration */
 547         if (machine_desc->init_early)
 548                 machine_desc->init_early();
 549
 550         smp_init_cpus();
 551
 552         setup_processor();
 553         setup_arch_memory();
 554
 555         /* copy flat DT out of .init and then unflatten it */
 556         unflatten_and_copy_device_tree();
 557
 558         /* Can be issue if someone passes cmd line arg "ro"
 559          * But that is unlikely so keeping it as it is
 560          */
 561         root_mountflags &= ~MS_RDONLY;
 562
 563 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 564         conswitchp = &dummy_con;
 565 #endif
 566
 567         arc_unwind_init();
 568 }
 569
 570 /*
 571  * Called from start_kernel() - boot CPU only
 572  */
 573 void __init time_init(void)
 574 {
 575         of_clk_init(NULL);
 576         timer_probe();
 577 }
 578
 579 static int __init customize_machine(void)
 580 {
 581         if (machine_desc->init_machine)
 582                 machine_desc->init_machine();
 583
 584         return 0;
 585 }
 586 arch_initcall(customize_machine);
 587
 588 static int __init init_late_machine(void)
 589 {
 590         if (machine_desc->init_late)
 591                 machine_desc->init_late();
 592
 593         return 0;
 594 }
 595 late_initcall(init_late_machine);
 596 /*
 597  *  Get CPU information for use by the procfs.
 598  */
 599
 600 #define cpu_to_ptr(c)   ((void *)(0xFFFF0000 | (unsigned int)(c)))
 601 #define ptr_to_cpu(p)   (~0xFFFF0000UL & (unsigned int)(p))
 602
 603 static int show_cpuinfo(struct seq_file *m, void *v)
 604 {
 605         char *str;
 606         int cpu_id = ptr_to_cpu(v);
 607         struct device *cpu_dev = get_cpu_device(cpu_id);
 608         struct clk *cpu_clk;
 609         unsigned long freq = 0;
 610
 611         if (!cpu_online(cpu_id)) {
 612                 seq_printf(m, "processor [%d]\t: Offline\n", cpu_id);
 613                 goto done;
 614         }
 615
 616         str = (char *)__get_free_page(GFP_KERNEL);
 617         if (!str)
 618                 goto done;
 619
 620         seq_printf(m, arc_cpu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 621
 622         cpu_clk = clk_get(cpu_dev, NULL);
 623         if (IS_ERR(cpu_clk)) {
 624                 seq_printf(m, "CPU speed \t: Cannot get clock for processor [%d]\n",
 625                            cpu_id);
 626         } else {
 627                 freq = clk_get_rate(cpu_clk);
 628         }
 629         if (freq)
 630                 seq_printf(m, "CPU speed\t: %lu.%02lu Mhz\n",
 631                            freq / 1000000, (freq / 10000) % 100);
 632
 633         seq_printf(m, "Bogo MIPS\t: %lu.%02lu\n",
 634                    loops_per_jiffy / (500000 / HZ),
 635                    (loops_per_jiffy / (5000 / HZ)) % 100);
 636
 637         seq_printf(m, arc_mmu_mumbojumbo(cpu_id, str, PAGE_SIZE));
 638         seq_printf(m, arc_cache_mumbojumbo(cpu_id, str, PAGE_SIZE));
 639         seq_printf(m, arc_extn_mumbojumbo(cpu_id, str, PAGE_SIZE));
 640         seq_printf(m, arc_platform_smp_cpuinfo());
 641
 642         free_page((unsigned long)str);
 643 done:
 644         seq_printf(m, "\n");
 645
 646         return 0;
 647 }
 648
 649 static void *c_start(struct seq_file *m, loff_t *pos)
 650 {
 651         /*
 652          * Callback returns cpu-id to iterator for show routine, NULL to stop.
 653          * However since NULL is also a valid cpu-id (0), we use a round-about
 654          * way to pass it w/o having to kmalloc/free a 2 byte string.
 655          * Encode cpu-id as 0xFFcccc, which is decoded by show routine.
 656          */
 657         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 658 }
 659
 660 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 661 {
 662         ++*pos;
 663         return c_start(m, pos);
 664 }
 665
 666 static void c_stop(struct seq_file *m, void *v)
 667 {
 668 }
 669
 670 const struct seq_operations cpuinfo_op = {
 671         .start  = c_start,
 672         .next   = c_next,
 673         .stop   = c_stop,
 674         .show   = show_cpuinfo
 675 };
 676
 677 static DEFINE_PER_CPU(struct cpu, cpu_topology);
 678
 679 static int __init topology_init(void)
 680 {
 681         int cpu;
 682
 683         for_each_present_cpu(cpu)
 684             register_cpu(&per_cpu(cpu_topology, cpu), cpu);
 685
 686         return 0;
 687 }
 688
 689 subsys_initcall(topology_init);