4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
61 select HAVE_CONTEXT_TRACKING
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
416 Support for the Cortina Systems Gemini family SoCs
420 select ARCH_REQUIRE_GPIOLIB
423 select GENERIC_CLOCKEVENTS
424 select GENERIC_IRQ_CHIP
425 select MIGHT_HAVE_CACHE_L2X0
431 Support for CSR SiRFprimaII/Marco/Polo platforms
435 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
442 This is an evaluation board for the StrongARM processor available
443 from Digital. It has limited hardware on-board, including an
444 Ethernet interface, two PCMCIA sockets, two serial ports and a
449 select ARCH_HAS_HOLES_MEMORYMODEL
450 select ARCH_REQUIRE_GPIOLIB
451 select ARCH_USES_GETTIMEOFFSET
456 select NEED_MACH_MEMORY_H
458 This enables support for the Cirrus EP93xx series of CPUs.
460 config ARCH_FOOTBRIDGE
464 select GENERIC_CLOCKEVENTS
466 select NEED_MACH_IO_H if !MMU
467 select NEED_MACH_MEMORY_H
469 Support for systems based on the DC21285 companion chip
470 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
473 bool "Freescale MXS-based"
474 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
479 select HAVE_CLK_PREPARE
480 select MULTI_IRQ_HANDLER
485 Support for Freescale MXS-based family of processors
488 bool "Hilscher NetX based"
492 select GENERIC_CLOCKEVENTS
494 This enables support for systems based on the Hilscher NetX Soc
497 bool "Hynix HMS720x-based"
498 select ARCH_USES_GETTIMEOFFSET
502 This enables support for systems based on the Hynix HMS720x
507 select ARCH_SUPPORTS_MSI
509 select NEED_MACH_MEMORY_H
510 select NEED_RET_TO_USER
515 Support for Intel's IOP13XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
522 select NEED_MACH_GPIO_H
523 select NEED_RET_TO_USER
527 Support for Intel's 80219 and IOP32X (XScale) family of
533 select ARCH_REQUIRE_GPIOLIB
535 select NEED_MACH_GPIO_H
536 select NEED_RET_TO_USER
540 Support for Intel's IOP33X (XScale) family of processors.
545 select ARCH_HAS_DMA_SET_COHERENT_MASK
546 select ARCH_REQUIRE_GPIOLIB
549 select DMABOUNCE if PCI
550 select GENERIC_CLOCKEVENTS
551 select MIGHT_HAVE_PCI
552 select NEED_MACH_IO_H
554 Support for Intel's IXP4XX (XScale) family of processors.
558 select ARCH_REQUIRE_GPIOLIB
560 select GENERIC_CLOCKEVENTS
561 select MIGHT_HAVE_PCI
564 select PLAT_ORION_LEGACY
565 select USB_ARCH_HAS_EHCI
567 Support for the Marvell Dove SoC 88AP510
570 bool "Marvell Kirkwood"
571 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
577 select PINCTRL_KIRKWOOD
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Kirkwood series SoCs:
581 88F6180, 88F6192 and 88F6281.
584 bool "Marvell MV78xx0"
585 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
589 select PLAT_ORION_LEGACY
591 Support for the following Marvell MV78xx0 series SoCs:
597 select ARCH_REQUIRE_GPIOLIB
599 select GENERIC_CLOCKEVENTS
601 select PLAT_ORION_LEGACY
603 Support for the following Marvell Orion 5x series SoCs:
604 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
605 Orion-2 (5281), Orion-1-90 (6183).
608 bool "Marvell PXA168/910/MMP2"
610 select ARCH_REQUIRE_GPIOLIB
612 select GENERIC_ALLOCATOR
613 select GENERIC_CLOCKEVENTS
616 select NEED_MACH_GPIO_H
621 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
624 bool "Micrel/Kendin KS8695"
625 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select NEED_MACH_MEMORY_H
631 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
632 System-on-Chip devices.
635 bool "Nuvoton W90X900 CPU"
636 select ARCH_REQUIRE_GPIOLIB
640 select GENERIC_CLOCKEVENTS
642 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
643 At present, the w90x900 has been renamed nuc900, regarding
644 the ARM series product line, you can login the following
645 link address to know more.
647 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
648 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
652 select ARCH_REQUIRE_GPIOLIB
657 select GENERIC_CLOCKEVENTS
660 select USB_ARCH_HAS_OHCI
663 Support for the NXP LPC32XX family of processors
667 select ARCH_HAS_CPUFREQ
668 select ARCH_REQUIRE_GPIOLIB
673 select GENERIC_CLOCKEVENTS
676 select MIGHT_HAVE_CACHE_L2X0
680 This enables support for NVIDIA Tegra based systems (Tegra APX,
681 Tegra 6xx and Tegra 2 series).
684 bool "PXA2xx/PXA3xx-based"
686 select ARCH_HAS_CPUFREQ
688 select ARCH_REQUIRE_GPIOLIB
689 select ARM_CPU_SUSPEND if PM
693 select GENERIC_CLOCKEVENTS
696 select MULTI_IRQ_HANDLER
697 select NEED_MACH_GPIO_H
701 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
705 select ARCH_REQUIRE_GPIOLIB
707 select GENERIC_CLOCKEVENTS
710 Support for Qualcomm MSM/QSD based systems. This runs on the
711 apps processor of the MSM/QSD and depends on a shared memory
712 interface to the modem processor which runs the baseband
713 stack and controls some vital subsystems
714 (clock and power control, etc).
717 bool "Renesas SH-Mobile / R-Mobile"
719 select GENERIC_CLOCKEVENTS
721 select HAVE_MACH_CLKDEV
723 select MIGHT_HAVE_CACHE_L2X0
724 select MULTI_IRQ_HANDLER
725 select NEED_MACH_MEMORY_H
728 select PM_GENERIC_DOMAINS if PM
731 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
736 select ARCH_MAY_HAVE_PC_FDC
737 select ARCH_SPARSEMEM_ENABLE
738 select ARCH_USES_GETTIMEOFFSET
741 select HAVE_PATA_PLATFORM
743 select NEED_MACH_IO_H
744 select NEED_MACH_MEMORY_H
748 On the Acorn Risc-PC, Linux can support the internal IDE disk and
749 CD-ROM interface, serial and parallel port, and the floppy drive.
753 select ARCH_HAS_CPUFREQ
755 select ARCH_REQUIRE_GPIOLIB
756 select ARCH_SPARSEMEM_ENABLE
761 select GENERIC_CLOCKEVENTS
764 select NEED_MACH_GPIO_H
765 select NEED_MACH_MEMORY_H
768 Support for StrongARM 11x0 based boards.
771 bool "Samsung S3C24XX SoCs"
772 select ARCH_HAS_CPUFREQ
773 select ARCH_USES_GETTIMEOFFSET
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 select HAVE_S3C_RTC if RTC_CLASS
779 select NEED_MACH_GPIO_H
780 select NEED_MACH_IO_H
782 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
783 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
784 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
785 Samsung SMDK2410 development board (and derivatives).
788 bool "Samsung S3C64XX"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_REQUIRE_GPIOLIB
791 select ARCH_USES_GETTIMEOFFSET
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select NEED_MACH_GPIO_H
803 select S3C_GPIO_TRACK
804 select SAMSUNG_CLKSRC
805 select SAMSUNG_GPIOLIB_4BIT
806 select SAMSUNG_IRQ_VIC_TIMER
807 select USB_ARCH_HAS_OHCI
809 Samsung S3C64XX series based systems
812 bool "Samsung S5P6440 S5P6450"
816 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_GPIO_H
823 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
827 bool "Samsung S5PC100"
828 select ARCH_USES_GETTIMEOFFSET
832 select HAVE_S3C2410_I2C if I2C
833 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 select HAVE_S3C_RTC if RTC_CLASS
835 select NEED_MACH_GPIO_H
837 Samsung S5PC100 series based systems
840 bool "Samsung S5PV210/S5PC110"
841 select ARCH_HAS_CPUFREQ
842 select ARCH_HAS_HOLES_MEMORYMODEL
843 select ARCH_SPARSEMEM_ENABLE
847 select GENERIC_CLOCKEVENTS
849 select HAVE_S3C2410_I2C if I2C
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
851 select HAVE_S3C_RTC if RTC_CLASS
852 select NEED_MACH_GPIO_H
853 select NEED_MACH_MEMORY_H
855 Samsung S5PV210/S5PC110 series based systems
858 bool "Samsung EXYNOS"
859 select ARCH_HAS_CPUFREQ
860 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_SPARSEMEM_ENABLE
864 select GENERIC_CLOCKEVENTS
866 select HAVE_S3C2410_I2C if I2C
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select HAVE_S3C_RTC if RTC_CLASS
869 select NEED_MACH_GPIO_H
870 select NEED_MACH_MEMORY_H
872 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
876 select ARCH_USES_GETTIMEOFFSET
880 select NEED_MACH_MEMORY_H
885 Support for the StrongARM based Digital DNARD machine, also known
886 as "Shark" (<http://www.shark-linux.de/shark.html>).
889 bool "ST-Ericsson U300 Series"
891 select ARCH_REQUIRE_GPIOLIB
893 select ARM_PATCH_PHYS_VIRT
899 select GENERIC_CLOCKEVENTS
903 Support for ST-Ericsson U300 series mobile platforms.
906 bool "ST-Ericsson U8500 Series"
908 select ARCH_HAS_CPUFREQ
909 select ARCH_REQUIRE_GPIOLIB
913 select GENERIC_CLOCKEVENTS
915 select MIGHT_HAVE_CACHE_L2X0
918 Support for ST-Ericsson's Ux500 architecture
921 bool "STMicroelectronics Nomadik"
922 select ARCH_REQUIRE_GPIOLIB
925 select CLKSRC_NOMADIK_MTU
928 select GENERIC_CLOCKEVENTS
929 select MIGHT_HAVE_CACHE_L2X0
932 select PINCTRL_STN8815
935 Support for the Nomadik platform by ST-Ericsson
939 select ARCH_HAS_CPUFREQ
940 select ARCH_REQUIRE_GPIOLIB
945 select GENERIC_CLOCKEVENTS
948 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
952 select ARCH_HAS_HOLES_MEMORYMODEL
953 select ARCH_REQUIRE_GPIOLIB
955 select GENERIC_ALLOCATOR
956 select GENERIC_CLOCKEVENTS
957 select GENERIC_IRQ_CHIP
959 select NEED_MACH_GPIO_H
963 Support for TI's DaVinci platform.
968 select ARCH_HAS_CPUFREQ
969 select ARCH_HAS_HOLES_MEMORYMODEL
971 select ARCH_REQUIRE_GPIOLIB
974 select GENERIC_CLOCKEVENTS
975 select GENERIC_IRQ_CHIP
979 select NEED_MACH_IO_H if PCCARD
980 select NEED_MACH_MEMORY_H
982 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
986 menu "Multiple platform selection"
987 depends on ARCH_MULTIPLATFORM
989 comment "CPU Core family selection"
992 bool "ARMv4 based platforms (FA526, StrongARM)"
993 depends on !ARCH_MULTI_V6_V7
994 select ARCH_MULTI_V4_V5
996 config ARCH_MULTI_V4T
997 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
998 depends on !ARCH_MULTI_V6_V7
999 select ARCH_MULTI_V4_V5
1001 config ARCH_MULTI_V5
1002 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1003 depends on !ARCH_MULTI_V6_V7
1004 select ARCH_MULTI_V4_V5
1006 config ARCH_MULTI_V4_V5
1009 config ARCH_MULTI_V6
1010 bool "ARMv6 based platforms (ARM11)"
1011 select ARCH_MULTI_V6_V7
1014 config ARCH_MULTI_V7
1015 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1017 select ARCH_MULTI_V6_V7
1018 select ARCH_VEXPRESS
1021 config ARCH_MULTI_V6_V7
1024 config ARCH_MULTI_CPU_AUTO
1025 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1026 select ARCH_MULTI_V5
1031 # This is sorted alphabetically by mach-* pathname. However, plat-*
1032 # Kconfigs may be included either alphabetically (according to the
1033 # plat- suffix) or along side the corresponding mach-* source.
1035 source "arch/arm/mach-mvebu/Kconfig"
1037 source "arch/arm/mach-at91/Kconfig"
1039 source "arch/arm/mach-bcm/Kconfig"
1041 source "arch/arm/mach-clps711x/Kconfig"
1043 source "arch/arm/mach-cns3xxx/Kconfig"
1045 source "arch/arm/mach-davinci/Kconfig"
1047 source "arch/arm/mach-dove/Kconfig"
1049 source "arch/arm/mach-ep93xx/Kconfig"
1051 source "arch/arm/mach-footbridge/Kconfig"
1053 source "arch/arm/mach-gemini/Kconfig"
1055 source "arch/arm/mach-h720x/Kconfig"
1057 source "arch/arm/mach-highbank/Kconfig"
1059 source "arch/arm/mach-integrator/Kconfig"
1061 source "arch/arm/mach-iop32x/Kconfig"
1063 source "arch/arm/mach-iop33x/Kconfig"
1065 source "arch/arm/mach-iop13xx/Kconfig"
1067 source "arch/arm/mach-ixp4xx/Kconfig"
1069 source "arch/arm/mach-kirkwood/Kconfig"
1071 source "arch/arm/mach-ks8695/Kconfig"
1073 source "arch/arm/mach-msm/Kconfig"
1075 source "arch/arm/mach-mv78xx0/Kconfig"
1077 source "arch/arm/mach-imx/Kconfig"
1079 source "arch/arm/mach-mxs/Kconfig"
1081 source "arch/arm/mach-netx/Kconfig"
1083 source "arch/arm/mach-nomadik/Kconfig"
1085 source "arch/arm/plat-omap/Kconfig"
1087 source "arch/arm/mach-omap1/Kconfig"
1089 source "arch/arm/mach-omap2/Kconfig"
1091 source "arch/arm/mach-orion5x/Kconfig"
1093 source "arch/arm/mach-picoxcell/Kconfig"
1095 source "arch/arm/mach-pxa/Kconfig"
1096 source "arch/arm/plat-pxa/Kconfig"
1098 source "arch/arm/mach-mmp/Kconfig"
1100 source "arch/arm/mach-realview/Kconfig"
1102 source "arch/arm/mach-sa1100/Kconfig"
1104 source "arch/arm/plat-samsung/Kconfig"
1106 source "arch/arm/mach-socfpga/Kconfig"
1108 source "arch/arm/plat-spear/Kconfig"
1110 source "arch/arm/mach-s3c24xx/Kconfig"
1113 source "arch/arm/mach-s3c64xx/Kconfig"
1116 source "arch/arm/mach-s5p64x0/Kconfig"
1118 source "arch/arm/mach-s5pc100/Kconfig"
1120 source "arch/arm/mach-s5pv210/Kconfig"
1122 source "arch/arm/mach-exynos/Kconfig"
1124 source "arch/arm/mach-shmobile/Kconfig"
1126 source "arch/arm/mach-sunxi/Kconfig"
1128 source "arch/arm/mach-prima2/Kconfig"
1130 source "arch/arm/mach-tegra/Kconfig"
1132 source "arch/arm/mach-u300/Kconfig"
1134 source "arch/arm/mach-ux500/Kconfig"
1136 source "arch/arm/mach-versatile/Kconfig"
1138 source "arch/arm/mach-vexpress/Kconfig"
1139 source "arch/arm/plat-versatile/Kconfig"
1141 source "arch/arm/mach-virt/Kconfig"
1143 source "arch/arm/mach-vt8500/Kconfig"
1145 source "arch/arm/mach-w90x900/Kconfig"
1147 source "arch/arm/mach-zynq/Kconfig"
1149 # Definitions to make life easier
1155 select GENERIC_CLOCKEVENTS
1161 select GENERIC_IRQ_CHIP
1164 config PLAT_ORION_LEGACY
1171 config PLAT_VERSATILE
1174 config ARM_TIMER_SP804
1177 select HAVE_SCHED_CLOCK
1179 source arch/arm/mm/Kconfig
1183 default 16 if ARCH_EP93XX
1187 bool "Enable iWMMXt support" if !CPU_PJ4
1188 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1189 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1191 Enable support for iWMMXt context switching at run time if
1192 running on a CPU that supports it.
1196 depends on CPU_XSCALE
1199 config MULTI_IRQ_HANDLER
1202 Allow each machine to specify it's own IRQ handler at run time.
1205 source "arch/arm/Kconfig-nommu"
1208 config ARM_ERRATA_326103
1209 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1212 Executing a SWP instruction to read-only memory does not set bit 11
1213 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1214 treat the access as a read, preventing a COW from occurring and
1215 causing the faulting task to livelock.
1217 config ARM_ERRATA_411920
1218 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1219 depends on CPU_V6 || CPU_V6K
1221 Invalidation of the Instruction Cache operation can
1222 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1223 It does not affect the MPCore. This option enables the ARM Ltd.
1224 recommended workaround.
1226 config ARM_ERRATA_430973
1227 bool "ARM errata: Stale prediction on replaced interworking branch"
1230 This option enables the workaround for the 430973 Cortex-A8
1231 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1232 interworking branch is replaced with another code sequence at the
1233 same virtual address, whether due to self-modifying code or virtual
1234 to physical address re-mapping, Cortex-A8 does not recover from the
1235 stale interworking branch prediction. This results in Cortex-A8
1236 executing the new code sequence in the incorrect ARM or Thumb state.
1237 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1238 and also flushes the branch target cache at every context switch.
1239 Note that setting specific bits in the ACTLR register may not be
1240 available in non-secure mode.
1242 config ARM_ERRATA_458693
1243 bool "ARM errata: Processor deadlock when a false hazard is created"
1245 depends on !ARCH_MULTIPLATFORM
1247 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1248 erratum. For very specific sequences of memory operations, it is
1249 possible for a hazard condition intended for a cache line to instead
1250 be incorrectly associated with a different cache line. This false
1251 hazard might then cause a processor deadlock. The workaround enables
1252 the L1 caching of the NEON accesses and disables the PLD instruction
1253 in the ACTLR register. Note that setting specific bits in the ACTLR
1254 register may not be available in non-secure mode.
1256 config ARM_ERRATA_460075
1257 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1259 depends on !ARCH_MULTIPLATFORM
1261 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1262 erratum. Any asynchronous access to the L2 cache may encounter a
1263 situation in which recent store transactions to the L2 cache are lost
1264 and overwritten with stale memory contents from external memory. The
1265 workaround disables the write-allocate mode for the L2 cache via the
1266 ACTLR register. Note that setting specific bits in the ACTLR register
1267 may not be available in non-secure mode.
1269 config ARM_ERRATA_742230
1270 bool "ARM errata: DMB operation may be faulty"
1271 depends on CPU_V7 && SMP
1272 depends on !ARCH_MULTIPLATFORM
1274 This option enables the workaround for the 742230 Cortex-A9
1275 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1276 between two write operations may not ensure the correct visibility
1277 ordering of the two writes. This workaround sets a specific bit in
1278 the diagnostic register of the Cortex-A9 which causes the DMB
1279 instruction to behave as a DSB, ensuring the correct behaviour of
1282 config ARM_ERRATA_742231
1283 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1284 depends on CPU_V7 && SMP
1285 depends on !ARCH_MULTIPLATFORM
1287 This option enables the workaround for the 742231 Cortex-A9
1288 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1289 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1290 accessing some data located in the same cache line, may get corrupted
1291 data due to bad handling of the address hazard when the line gets
1292 replaced from one of the CPUs at the same time as another CPU is
1293 accessing it. This workaround sets specific bits in the diagnostic
1294 register of the Cortex-A9 which reduces the linefill issuing
1295 capabilities of the processor.
1297 config PL310_ERRATA_588369
1298 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1299 depends on CACHE_L2X0
1301 The PL310 L2 cache controller implements three types of Clean &
1302 Invalidate maintenance operations: by Physical Address
1303 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1304 They are architecturally defined to behave as the execution of a
1305 clean operation followed immediately by an invalidate operation,
1306 both performing to the same memory location. This functionality
1307 is not correctly implemented in PL310 as clean lines are not
1308 invalidated as a result of these operations.
1310 config ARM_ERRATA_720789
1311 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1314 This option enables the workaround for the 720789 Cortex-A9 (prior to
1315 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1316 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1317 As a consequence of this erratum, some TLB entries which should be
1318 invalidated are not, resulting in an incoherency in the system page
1319 tables. The workaround changes the TLB flushing routines to invalidate
1320 entries regardless of the ASID.
1322 config PL310_ERRATA_727915
1323 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1324 depends on CACHE_L2X0
1326 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1327 operation (offset 0x7FC). This operation runs in background so that
1328 PL310 can handle normal accesses while it is in progress. Under very
1329 rare circumstances, due to this erratum, write data can be lost when
1330 PL310 treats a cacheable write transaction during a Clean &
1331 Invalidate by Way operation.
1333 config ARM_ERRATA_743622
1334 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1336 depends on !ARCH_MULTIPLATFORM
1338 This option enables the workaround for the 743622 Cortex-A9
1339 (r2p*) erratum. Under very rare conditions, a faulty
1340 optimisation in the Cortex-A9 Store Buffer may lead to data
1341 corruption. This workaround sets a specific bit in the diagnostic
1342 register of the Cortex-A9 which disables the Store Buffer
1343 optimisation, preventing the defect from occurring. This has no
1344 visible impact on the overall performance or power consumption of the
1347 config ARM_ERRATA_751472
1348 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1350 depends on !ARCH_MULTIPLATFORM
1352 This option enables the workaround for the 751472 Cortex-A9 (prior
1353 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1354 completion of a following broadcasted operation if the second
1355 operation is received by a CPU before the ICIALLUIS has completed,
1356 potentially leading to corrupted entries in the cache or TLB.
1358 config PL310_ERRATA_753970
1359 bool "PL310 errata: cache sync operation may be faulty"
1360 depends on CACHE_PL310
1362 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1364 Under some condition the effect of cache sync operation on
1365 the store buffer still remains when the operation completes.
1366 This means that the store buffer is always asked to drain and
1367 this prevents it from merging any further writes. The workaround
1368 is to replace the normal offset of cache sync operation (0x730)
1369 by another offset targeting an unmapped PL310 register 0x740.
1370 This has the same effect as the cache sync operation: store buffer
1371 drain and waiting for all buffers empty.
1373 config ARM_ERRATA_754322
1374 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1377 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1378 r3p*) erratum. A speculative memory access may cause a page table walk
1379 which starts prior to an ASID switch but completes afterwards. This
1380 can populate the micro-TLB with a stale entry which may be hit with
1381 the new ASID. This workaround places two dsb instructions in the mm
1382 switching code so that no page table walks can cross the ASID switch.
1384 config ARM_ERRATA_754327
1385 bool "ARM errata: no automatic Store Buffer drain"
1386 depends on CPU_V7 && SMP
1388 This option enables the workaround for the 754327 Cortex-A9 (prior to
1389 r2p0) erratum. The Store Buffer does not have any automatic draining
1390 mechanism and therefore a livelock may occur if an external agent
1391 continuously polls a memory location waiting to observe an update.
1392 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1393 written polling loops from denying visibility of updates to memory.
1395 config ARM_ERRATA_364296
1396 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1397 depends on CPU_V6 && !SMP
1399 This options enables the workaround for the 364296 ARM1136
1400 r0p2 erratum (possible cache data corruption with
1401 hit-under-miss enabled). It sets the undocumented bit 31 in
1402 the auxiliary control register and the FI bit in the control
1403 register, thus disabling hit-under-miss without putting the
1404 processor into full low interrupt latency mode. ARM11MPCore
1407 config ARM_ERRATA_764369
1408 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1409 depends on CPU_V7 && SMP
1411 This option enables the workaround for erratum 764369
1412 affecting Cortex-A9 MPCore with two or more processors (all
1413 current revisions). Under certain timing circumstances, a data
1414 cache line maintenance operation by MVA targeting an Inner
1415 Shareable memory region may fail to proceed up to either the
1416 Point of Coherency or to the Point of Unification of the
1417 system. This workaround adds a DSB instruction before the
1418 relevant cache maintenance functions and sets a specific bit
1419 in the diagnostic control register of the SCU.
1421 config PL310_ERRATA_769419
1422 bool "PL310 errata: no automatic Store Buffer drain"
1423 depends on CACHE_L2X0
1425 On revisions of the PL310 prior to r3p2, the Store Buffer does
1426 not automatically drain. This can cause normal, non-cacheable
1427 writes to be retained when the memory system is idle, leading
1428 to suboptimal I/O performance for drivers using coherent DMA.
1429 This option adds a write barrier to the cpu_idle loop so that,
1430 on systems with an outer cache, the store buffer is drained
1433 config ARM_ERRATA_775420
1434 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1437 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1438 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1439 operation aborts with MMU exception, it might cause the processor
1440 to deadlock. This workaround puts DSB before executing ISB if
1441 an abort may occur on cache maintenance.
1443 config ARM_ERRATA_798181
1444 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1445 depends on CPU_V7 && SMP
1447 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1448 adequately shooting down all use of the old entries. This
1449 option enables the Linux kernel workaround for this erratum
1450 which sends an IPI to the CPUs that are running the same ASID
1451 as the one being invalidated.
1455 source "arch/arm/common/Kconfig"
1465 Find out whether you have ISA slots on your motherboard. ISA is the
1466 name of a bus system, i.e. the way the CPU talks to the other stuff
1467 inside your box. Other bus systems are PCI, EISA, MicroChannel
1468 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1469 newer boards don't support it. If you have ISA, say Y, otherwise N.
1471 # Select ISA DMA controller support
1476 # Select ISA DMA interface
1481 bool "PCI support" if MIGHT_HAVE_PCI
1483 Find out whether you have a PCI motherboard. PCI is the name of a
1484 bus system, i.e. the way the CPU talks to the other stuff inside
1485 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1486 VESA. If you have PCI, say Y, otherwise N.
1492 config PCI_NANOENGINE
1493 bool "BSE nanoEngine PCI support"
1494 depends on SA1100_NANOENGINE
1496 Enable PCI on the BSE nanoEngine board.
1501 # Select the host bridge type
1502 config PCI_HOST_VIA82C505
1504 depends on PCI && ARCH_SHARK
1507 config PCI_HOST_ITE8152
1509 depends on PCI && MACH_ARMCORE
1513 source "drivers/pci/Kconfig"
1515 source "drivers/pcmcia/Kconfig"
1519 menu "Kernel Features"
1524 This option should be selected by machines which have an SMP-
1527 The only effect of this option is to make the SMP-related
1528 options available to the user for configuration.
1531 bool "Symmetric Multi-Processing"
1532 depends on CPU_V6K || CPU_V7
1533 depends on GENERIC_CLOCKEVENTS
1536 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1537 select USE_GENERIC_SMP_HELPERS
1539 This enables support for systems with more than one CPU. If you have
1540 a system with only one CPU, like most personal computers, say N. If
1541 you have a system with more than one CPU, say Y.
1543 If you say N here, the kernel will run on single and multiprocessor
1544 machines, but will use only one CPU of a multiprocessor machine. If
1545 you say Y here, the kernel will run on many, but not all, single
1546 processor machines. On a single processor machine, the kernel will
1547 run faster if you say N here.
1549 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1550 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1551 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1553 If you don't know what to do here, say N.
1556 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1557 depends on SMP && !XIP_KERNEL
1560 SMP kernels contain instructions which fail on non-SMP processors.
1561 Enabling this option allows the kernel to modify itself to make
1562 these instructions safe. Disabling it allows about 1K of space
1565 If you don't know what to do here, say Y.
1567 config ARM_CPU_TOPOLOGY
1568 bool "Support cpu topology definition"
1569 depends on SMP && CPU_V7
1572 Support ARM cpu topology definition. The MPIDR register defines
1573 affinity between processors which is then used to describe the cpu
1574 topology of an ARM System.
1577 bool "Multi-core scheduler support"
1578 depends on ARM_CPU_TOPOLOGY
1580 Multi-core scheduler support improves the CPU scheduler's decision
1581 making when dealing with multi-core CPU chips at a cost of slightly
1582 increased overhead in some places. If unsure say N here.
1585 bool "SMT scheduler support"
1586 depends on ARM_CPU_TOPOLOGY
1588 Improves the CPU scheduler's decision making when dealing with
1589 MultiThreading at a cost of slightly increased overhead in some
1590 places. If unsure say N here.
1595 This option enables support for the ARM system coherency unit
1597 config HAVE_ARM_ARCH_TIMER
1598 bool "Architected timer support"
1600 select ARM_ARCH_TIMER
1602 This option enables support for the ARM architected timer
1608 This options enables support for the ARM timer and watchdog unit
1611 bool "Multi-Cluster Power Management"
1612 depends on CPU_V7 && SMP
1614 This option provides the common power management infrastructure
1615 for (multi-)cluster based systems, such as big.LITTLE based
1619 prompt "Memory split"
1622 Select the desired split between kernel and user memory.
1624 If you are not absolutely sure what you are doing, leave this
1628 bool "3G/1G user/kernel split"
1630 bool "2G/2G user/kernel split"
1632 bool "1G/3G user/kernel split"
1637 default 0x40000000 if VMSPLIT_1G
1638 default 0x80000000 if VMSPLIT_2G
1642 int "Maximum number of CPUs (2-32)"
1648 bool "Support for hot-pluggable CPUs"
1649 depends on SMP && HOTPLUG
1651 Say Y here to experiment with turning CPUs off and on. CPUs
1652 can be controlled through /sys/devices/system/cpu.
1655 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1658 Say Y here if you want Linux to communicate with system firmware
1659 implementing the PSCI specification for CPU-centric power
1660 management operations described in ARM document number ARM DEN
1661 0022A ("Power State Coordination Interface System Software on
1665 bool "Use local timer interrupts"
1668 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1670 Enable support for local timers on SMP platforms, rather then the
1671 legacy IPI broadcast method. Local timers allows the system
1672 accounting to be spread across the timer interval, preventing a
1673 "thundering herd" at every timer tick.
1675 # The GPIO number here must be sorted by descending number. In case of
1676 # a multiplatform kernel, we just want the highest value required by the
1677 # selected platforms.
1680 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1681 default 512 if SOC_OMAP5
1682 default 355 if ARCH_U8500
1683 default 288 if ARCH_VT8500 || ARCH_SUNXI
1684 default 264 if MACH_H4700
1687 Maximum number of GPIOs in the system.
1689 If unsure, leave the default value.
1691 source kernel/Kconfig.preempt
1695 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1696 ARCH_S5PV210 || ARCH_EXYNOS4
1697 default AT91_TIMER_HZ if ARCH_AT91
1698 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1702 def_bool HIGH_RES_TIMERS
1704 config THUMB2_KERNEL
1705 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1706 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1707 default y if CPU_THUMBONLY
1709 select ARM_ASM_UNIFIED
1712 By enabling this option, the kernel will be compiled in
1713 Thumb-2 mode. A compiler/assembler that understand the unified
1714 ARM-Thumb syntax is needed.
1718 config THUMB2_AVOID_R_ARM_THM_JUMP11
1719 bool "Work around buggy Thumb-2 short branch relocations in gas"
1720 depends on THUMB2_KERNEL && MODULES
1723 Various binutils versions can resolve Thumb-2 branches to
1724 locally-defined, preemptible global symbols as short-range "b.n"
1725 branch instructions.
1727 This is a problem, because there's no guarantee the final
1728 destination of the symbol, or any candidate locations for a
1729 trampoline, are within range of the branch. For this reason, the
1730 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1731 relocation in modules at all, and it makes little sense to add
1734 The symptom is that the kernel fails with an "unsupported
1735 relocation" error when loading some modules.
1737 Until fixed tools are available, passing
1738 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1739 code which hits this problem, at the cost of a bit of extra runtime
1740 stack usage in some cases.
1742 The problem is described in more detail at:
1743 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1745 Only Thumb-2 kernels are affected.
1747 Unless you are sure your tools don't have this problem, say Y.
1749 config ARM_ASM_UNIFIED
1753 bool "Use the ARM EABI to compile the kernel"
1755 This option allows for the kernel to be compiled using the latest
1756 ARM ABI (aka EABI). This is only useful if you are using a user
1757 space environment that is also compiled with EABI.
1759 Since there are major incompatibilities between the legacy ABI and
1760 EABI, especially with regard to structure member alignment, this
1761 option also changes the kernel syscall calling convention to
1762 disambiguate both ABIs and allow for backward compatibility support
1763 (selected with CONFIG_OABI_COMPAT).
1765 To use this you need GCC version 4.0.0 or later.
1768 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1769 depends on AEABI && !THUMB2_KERNEL
1772 This option preserves the old syscall interface along with the
1773 new (ARM EABI) one. It also provides a compatibility layer to
1774 intercept syscalls that have structure arguments which layout
1775 in memory differs between the legacy ABI and the new ARM EABI
1776 (only for non "thumb" binaries). This option adds a tiny
1777 overhead to all syscalls and produces a slightly larger kernel.
1778 If you know you'll be using only pure EABI user space then you
1779 can say N here. If this option is not selected and you attempt
1780 to execute a legacy ABI binary then the result will be
1781 UNPREDICTABLE (in fact it can be predicted that it won't work
1782 at all). If in doubt say Y.
1784 config ARCH_HAS_HOLES_MEMORYMODEL
1787 config ARCH_SPARSEMEM_ENABLE
1790 config ARCH_SPARSEMEM_DEFAULT
1791 def_bool ARCH_SPARSEMEM_ENABLE
1793 config ARCH_SELECT_MEMORY_MODEL
1794 def_bool ARCH_SPARSEMEM_ENABLE
1796 config HAVE_ARCH_PFN_VALID
1797 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1800 bool "High Memory Support"
1803 The address space of ARM processors is only 4 Gigabytes large
1804 and it has to accommodate user address space, kernel address
1805 space as well as some memory mapped IO. That means that, if you
1806 have a large amount of physical memory and/or IO, not all of the
1807 memory can be "permanently mapped" by the kernel. The physical
1808 memory that is not permanently mapped is called "high memory".
1810 Depending on the selected kernel/user memory split, minimum
1811 vmalloc space and actual amount of RAM, you may not need this
1812 option which should result in a slightly faster kernel.
1817 bool "Allocate 2nd-level pagetables from highmem"
1820 config HW_PERF_EVENTS
1821 bool "Enable hardware performance counter support for perf events"
1822 depends on PERF_EVENTS
1825 Enable hardware performance counter support for perf events. If
1826 disabled, perf events will use software events only.
1830 config FORCE_MAX_ZONEORDER
1831 int "Maximum zone order" if ARCH_SHMOBILE
1832 range 11 64 if ARCH_SHMOBILE
1833 default "12" if SOC_AM33XX
1834 default "9" if SA1111
1837 The kernel memory allocator divides physically contiguous memory
1838 blocks into "zones", where each zone is a power of two number of
1839 pages. This option selects the largest power of two that the kernel
1840 keeps in the memory allocator. If you need to allocate very large
1841 blocks of physically contiguous memory, then you may need to
1842 increase this value.
1844 This config option is actually maximum order plus one. For example,
1845 a value of 11 means that the largest free memory block is 2^10 pages.
1847 config ALIGNMENT_TRAP
1849 depends on CPU_CP15_MMU
1850 default y if !ARCH_EBSA110
1851 select HAVE_PROC_CPU if PROC_FS
1853 ARM processors cannot fetch/store information which is not
1854 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1855 address divisible by 4. On 32-bit ARM processors, these non-aligned
1856 fetch/store instructions will be emulated in software if you say
1857 here, which has a severe performance impact. This is necessary for
1858 correct operation of some network protocols. With an IP-only
1859 configuration it is safe to say N, otherwise say Y.
1861 config UACCESS_WITH_MEMCPY
1862 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1864 default y if CPU_FEROCEON
1866 Implement faster copy_to_user and clear_user methods for CPU
1867 cores where a 8-word STM instruction give significantly higher
1868 memory write throughput than a sequence of individual 32bit stores.
1870 A possible side effect is a slight increase in scheduling latency
1871 between threads sharing the same address space if they invoke
1872 such copy operations with large buffers.
1874 However, if the CPU data cache is using a write-allocate mode,
1875 this option is unlikely to provide any performance gain.
1879 prompt "Enable seccomp to safely compute untrusted bytecode"
1881 This kernel feature is useful for number crunching applications
1882 that may need to compute untrusted bytecode during their
1883 execution. By using pipes or other transports made available to
1884 the process as file descriptors supporting the read/write
1885 syscalls, it's possible to isolate those applications in
1886 their own address space using seccomp. Once seccomp is
1887 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1888 and the task is only allowed to execute a few safe syscalls
1889 defined by each seccomp mode.
1891 config CC_STACKPROTECTOR
1892 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1894 This option turns on the -fstack-protector GCC feature. This
1895 feature puts, at the beginning of functions, a canary value on
1896 the stack just before the return address, and validates
1897 the value just before actually returning. Stack based buffer
1898 overflows (that need to overwrite this return address) now also
1899 overwrite the canary, which gets detected and the attack is then
1900 neutralized via a kernel panic.
1901 This feature requires gcc version 4.2 or above.
1908 bool "Xen guest support on ARM (EXPERIMENTAL)"
1909 depends on ARM && AEABI && OF
1910 depends on CPU_V7 && !CPU_V6
1911 depends on !GENERIC_ATOMIC64
1913 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1920 bool "Flattened Device Tree support"
1923 select OF_EARLY_FLATTREE
1925 Include support for flattened device tree machine descriptions.
1928 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1931 This is the traditional way of passing data to the kernel at boot
1932 time. If you are solely relying on the flattened device tree (or
1933 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1934 to remove ATAGS support from your kernel binary. If unsure,
1937 config DEPRECATED_PARAM_STRUCT
1938 bool "Provide old way to pass kernel parameters"
1941 This was deprecated in 2001 and announced to live on for 5 years.
1942 Some old boot loaders still use this way.
1944 # Compressed boot loader in ROM. Yes, we really want to ask about
1945 # TEXT and BSS so we preserve their values in the config files.
1946 config ZBOOT_ROM_TEXT
1947 hex "Compressed ROM boot loader base address"
1950 The physical address at which the ROM-able zImage is to be
1951 placed in the target. Platforms which normally make use of
1952 ROM-able zImage formats normally set this to a suitable
1953 value in their defconfig file.
1955 If ZBOOT_ROM is not enabled, this has no effect.
1957 config ZBOOT_ROM_BSS
1958 hex "Compressed ROM boot loader BSS address"
1961 The base address of an area of read/write memory in the target
1962 for the ROM-able zImage which must be available while the
1963 decompressor is running. It must be large enough to hold the
1964 entire decompressed kernel plus an additional 128 KiB.
1965 Platforms which normally make use of ROM-able zImage formats
1966 normally set this to a suitable value in their defconfig file.
1968 If ZBOOT_ROM is not enabled, this has no effect.
1971 bool "Compressed boot loader in ROM/flash"
1972 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1974 Say Y here if you intend to execute your compressed kernel image
1975 (zImage) directly from ROM or flash. If unsure, say N.
1978 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1979 depends on ZBOOT_ROM && ARCH_SH7372
1980 default ZBOOT_ROM_NONE
1982 Include experimental SD/MMC loading code in the ROM-able zImage.
1983 With this enabled it is possible to write the ROM-able zImage
1984 kernel image to an MMC or SD card and boot the kernel straight
1985 from the reset vector. At reset the processor Mask ROM will load
1986 the first part of the ROM-able zImage which in turn loads the
1987 rest the kernel image to RAM.
1989 config ZBOOT_ROM_NONE
1990 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1992 Do not load image from SD or MMC
1994 config ZBOOT_ROM_MMCIF
1995 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1997 Load image from MMCIF hardware block.
1999 config ZBOOT_ROM_SH_MOBILE_SDHI
2000 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2002 Load image from SDHI hardware block
2006 config ARM_APPENDED_DTB
2007 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2008 depends on OF && !ZBOOT_ROM
2010 With this option, the boot code will look for a device tree binary
2011 (DTB) appended to zImage
2012 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2014 This is meant as a backward compatibility convenience for those
2015 systems with a bootloader that can't be upgraded to accommodate
2016 the documented boot protocol using a device tree.
2018 Beware that there is very little in terms of protection against
2019 this option being confused by leftover garbage in memory that might
2020 look like a DTB header after a reboot if no actual DTB is appended
2021 to zImage. Do not leave this option active in a production kernel
2022 if you don't intend to always append a DTB. Proper passing of the
2023 location into r2 of a bootloader provided DTB is always preferable
2026 config ARM_ATAG_DTB_COMPAT
2027 bool "Supplement the appended DTB with traditional ATAG information"
2028 depends on ARM_APPENDED_DTB
2030 Some old bootloaders can't be updated to a DTB capable one, yet
2031 they provide ATAGs with memory configuration, the ramdisk address,
2032 the kernel cmdline string, etc. Such information is dynamically
2033 provided by the bootloader and can't always be stored in a static
2034 DTB. To allow a device tree enabled kernel to be used with such
2035 bootloaders, this option allows zImage to extract the information
2036 from the ATAG list and store it at run time into the appended DTB.
2039 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2040 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2042 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2043 bool "Use bootloader kernel arguments if available"
2045 Uses the command-line options passed by the boot loader instead of
2046 the device tree bootargs property. If the boot loader doesn't provide
2047 any, the device tree bootargs property will be used.
2049 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2050 bool "Extend with bootloader kernel arguments"
2052 The command-line arguments provided by the boot loader will be
2053 appended to the the device tree bootargs property.
2058 string "Default kernel command string"
2061 On some architectures (EBSA110 and CATS), there is currently no way
2062 for the boot loader to pass arguments to the kernel. For these
2063 architectures, you should supply some command-line options at build
2064 time by entering them here. As a minimum, you should specify the
2065 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2068 prompt "Kernel command line type" if CMDLINE != ""
2069 default CMDLINE_FROM_BOOTLOADER
2072 config CMDLINE_FROM_BOOTLOADER
2073 bool "Use bootloader kernel arguments if available"
2075 Uses the command-line options passed by the boot loader. If
2076 the boot loader doesn't provide any, the default kernel command
2077 string provided in CMDLINE will be used.
2079 config CMDLINE_EXTEND
2080 bool "Extend bootloader kernel arguments"
2082 The command-line arguments provided by the boot loader will be
2083 appended to the default kernel command string.
2085 config CMDLINE_FORCE
2086 bool "Always use the default kernel command string"
2088 Always use the default kernel command string, even if the boot
2089 loader passes other arguments to the kernel.
2090 This is useful if you cannot or don't want to change the
2091 command-line options your boot loader passes to the kernel.
2095 bool "Kernel Execute-In-Place from ROM"
2096 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2098 Execute-In-Place allows the kernel to run from non-volatile storage
2099 directly addressable by the CPU, such as NOR flash. This saves RAM
2100 space since the text section of the kernel is not loaded from flash
2101 to RAM. Read-write sections, such as the data section and stack,
2102 are still copied to RAM. The XIP kernel is not compressed since
2103 it has to run directly from flash, so it will take more space to
2104 store it. The flash address used to link the kernel object files,
2105 and for storing it, is configuration dependent. Therefore, if you
2106 say Y here, you must know the proper physical address where to
2107 store the kernel image depending on your own flash memory usage.
2109 Also note that the make target becomes "make xipImage" rather than
2110 "make zImage" or "make Image". The final kernel binary to put in
2111 ROM memory will be arch/arm/boot/xipImage.
2115 config XIP_PHYS_ADDR
2116 hex "XIP Kernel Physical Location"
2117 depends on XIP_KERNEL
2118 default "0x00080000"
2120 This is the physical address in your flash memory the kernel will
2121 be linked for and stored to. This address is dependent on your
2125 bool "Kexec system call (EXPERIMENTAL)"
2126 depends on (!SMP || HOTPLUG_CPU)
2128 kexec is a system call that implements the ability to shutdown your
2129 current kernel, and to start another kernel. It is like a reboot
2130 but it is independent of the system firmware. And like a reboot
2131 you can start any kernel with it, not just Linux.
2133 It is an ongoing process to be certain the hardware in a machine
2134 is properly shutdown, so do not be surprised if this code does not
2135 initially work for you. It may help to enable device hotplugging
2139 bool "Export atags in procfs"
2140 depends on ATAGS && KEXEC
2143 Should the atags used to boot the kernel be exported in an "atags"
2144 file in procfs. Useful with kexec.
2147 bool "Build kdump crash kernel (EXPERIMENTAL)"
2149 Generate crash dump after being started by kexec. This should
2150 be normally only set in special crash dump kernels which are
2151 loaded in the main kernel with kexec-tools into a specially
2152 reserved region and then later executed after a crash by
2153 kdump/kexec. The crash dump kernel must be compiled to a
2154 memory address not used by the main kernel
2156 For more details see Documentation/kdump/kdump.txt
2158 config AUTO_ZRELADDR
2159 bool "Auto calculation of the decompressed kernel image address"
2160 depends on !ZBOOT_ROM && !ARCH_U300
2162 ZRELADDR is the physical address where the decompressed kernel
2163 image will be placed. If AUTO_ZRELADDR is selected, the address
2164 will be determined at run-time by masking the current IP with
2165 0xf8000000. This assumes the zImage being placed in the first 128MB
2166 from start of memory.
2170 menu "CPU Power Management"
2174 source "drivers/cpufreq/Kconfig"
2177 tristate "CPUfreq driver for i.MX CPUs"
2178 depends on ARCH_MXC && CPU_FREQ
2179 select CPU_FREQ_TABLE
2181 This enables the CPUfreq driver for i.MX CPUs.
2183 config CPU_FREQ_SA1100
2186 config CPU_FREQ_SA1110
2189 config CPU_FREQ_INTEGRATOR
2190 tristate "CPUfreq driver for ARM Integrator CPUs"
2191 depends on ARCH_INTEGRATOR && CPU_FREQ
2194 This enables the CPUfreq driver for ARM Integrator CPUs.
2196 For details, take a look at <file:Documentation/cpu-freq>.
2202 depends on CPU_FREQ && ARCH_PXA && PXA25x
2204 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2205 select CPU_FREQ_TABLE
2210 Internal configuration node for common cpufreq on Samsung SoC
2212 config CPU_FREQ_S3C24XX
2213 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2214 depends on ARCH_S3C24XX && CPU_FREQ
2217 This enables the CPUfreq driver for the Samsung S3C24XX family
2220 For details, take a look at <file:Documentation/cpu-freq>.
2224 config CPU_FREQ_S3C24XX_PLL
2225 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2226 depends on CPU_FREQ_S3C24XX
2228 Compile in support for changing the PLL frequency from the
2229 S3C24XX series CPUfreq driver. The PLL takes time to settle
2230 after a frequency change, so by default it is not enabled.
2232 This also means that the PLL tables for the selected CPU(s) will
2233 be built which may increase the size of the kernel image.
2235 config CPU_FREQ_S3C24XX_DEBUG
2236 bool "Debug CPUfreq Samsung driver core"
2237 depends on CPU_FREQ_S3C24XX
2239 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2241 config CPU_FREQ_S3C24XX_IODEBUG
2242 bool "Debug CPUfreq Samsung driver IO timing"
2243 depends on CPU_FREQ_S3C24XX
2245 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2247 config CPU_FREQ_S3C24XX_DEBUGFS
2248 bool "Export debugfs for CPUFreq"
2249 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2251 Export status information via debugfs.
2255 source "drivers/cpuidle/Kconfig"
2259 menu "Floating point emulation"
2261 comment "At least one emulation must be selected"
2264 bool "NWFPE math emulation"
2265 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2267 Say Y to include the NWFPE floating point emulator in the kernel.
2268 This is necessary to run most binaries. Linux does not currently
2269 support floating point hardware so you need to say Y here even if
2270 your machine has an FPA or floating point co-processor podule.
2272 You may say N here if you are going to load the Acorn FPEmulator
2273 early in the bootup.
2276 bool "Support extended precision"
2277 depends on FPE_NWFPE
2279 Say Y to include 80-bit support in the kernel floating-point
2280 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2281 Note that gcc does not generate 80-bit operations by default,
2282 so in most cases this option only enlarges the size of the
2283 floating point emulator without any good reason.
2285 You almost surely want to say N here.
2288 bool "FastFPE math emulation (EXPERIMENTAL)"
2289 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2291 Say Y here to include the FAST floating point emulator in the kernel.
2292 This is an experimental much faster emulator which now also has full
2293 precision for the mantissa. It does not support any exceptions.
2294 It is very simple, and approximately 3-6 times faster than NWFPE.
2296 It should be sufficient for most programs. It may be not suitable
2297 for scientific calculations, but you have to check this for yourself.
2298 If you do not feel you need a faster FP emulation you should better
2302 bool "VFP-format floating point maths"
2303 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2305 Say Y to include VFP support code in the kernel. This is needed
2306 if your hardware includes a VFP unit.
2308 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2309 release notes and additional status information.
2311 Say N if your target does not have VFP hardware.
2319 bool "Advanced SIMD (NEON) Extension support"
2320 depends on VFPv3 && CPU_V7
2322 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2327 menu "Userspace binary formats"
2329 source "fs/Kconfig.binfmt"
2332 tristate "RISC OS personality"
2335 Say Y here to include the kernel code necessary if you want to run
2336 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2337 experimental; if this sounds frightening, say N and sleep in peace.
2338 You can also say M here to compile this support as a module (which
2339 will be called arthur).
2343 menu "Power management options"
2345 source "kernel/power/Kconfig"
2347 config ARCH_SUSPEND_POSSIBLE
2348 depends on !ARCH_S5PC100
2349 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2350 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2353 config ARM_CPU_SUSPEND
2358 source "net/Kconfig"
2360 source "drivers/Kconfig"
2364 source "arch/arm/Kconfig.debug"
2366 source "security/Kconfig"
2368 source "crypto/Kconfig"
2370 source "lib/Kconfig"
2372 source "arch/arm/kvm/Kconfig"