5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config HARDIRQS_SW_RESEND
133 config GENERIC_IRQ_PROBE
137 config GENERIC_LOCKBREAK
140 depends on SMP && PREEMPT
142 config RWSEM_GENERIC_SPINLOCK
146 config RWSEM_XCHGADD_ALGORITHM
149 config ARCH_HAS_ILOG2_U32
152 config ARCH_HAS_ILOG2_U64
155 config ARCH_HAS_CPUFREQ
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
162 config ARCH_HAS_CPU_IDLE_WAIT
165 config GENERIC_HWEIGHT
169 config GENERIC_CALIBRATE_DELAY
173 config ARCH_MAY_HAVE_PC_FDC
179 config NEED_DMA_MAP_STATE
182 config ARCH_HAS_DMA_SET_COHERENT_MASK
185 config GENERIC_ISA_DMA
191 config NEED_RET_TO_USER
199 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
200 default DRAM_BASE if REMAP_VECTORS_TO_RAM
203 The base address of exception vectors.
205 config ARM_PATCH_PHYS_VIRT
206 bool "Patch physical to virtual translations at runtime" if EMBEDDED
208 depends on !XIP_KERNEL && MMU
209 depends on !ARCH_REALVIEW || !SPARSEMEM
211 Patch phys-to-virt and virt-to-phys translation functions at
212 boot and module load time according to the position of the
213 kernel in system memory.
215 This can only be used with non-XIP MMU kernels where the base
216 of physical memory is at a 16MB boundary.
218 Only disable this option if you know that you do not require
219 this feature (eg, building a kernel for a single machine) and
220 you need to shrink the kernel to the minimal size.
222 config NEED_MACH_IO_H
225 Select this when mach/io.h is required to provide special
226 definitions for this platform. The need for mach/io.h should
227 be avoided when possible.
229 config NEED_MACH_MEMORY_H
232 Select this when mach/memory.h is required to provide special
233 definitions for this platform. The need for mach/memory.h should
234 be avoided when possible.
237 hex "Physical address of main memory" if MMU
238 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
239 default DRAM_BASE if !MMU
241 Please provide the physical address corresponding to the
242 location of main memory in your system.
248 source "init/Kconfig"
250 source "kernel/Kconfig.freezer"
255 bool "MMU-based Paged Memory Management Support"
258 Select if you want MMU-based virtualised addressing space
259 support by paged memory management. If unsure, say 'Y'.
262 # The "ARM system type" choice list is ordered alphabetically by option
263 # text. Please add new entries in the option alphabetic order.
266 prompt "ARM system type"
267 default ARCH_VERSATILE
269 config ARCH_INTEGRATOR
270 bool "ARM Ltd. Integrator family"
272 select ARCH_HAS_CPUFREQ
274 select HAVE_MACH_CLKDEV
277 select GENERIC_CLOCKEVENTS
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_FPGA_IRQ
280 select NEED_MACH_IO_H
281 select NEED_MACH_MEMORY_H
284 Support for ARM's Integrator platform.
287 bool "ARM Ltd. RealView family"
290 select HAVE_MACH_CLKDEV
292 select GENERIC_CLOCKEVENTS
293 select ARCH_WANT_OPTIONAL_GPIOLIB
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
296 select ARM_TIMER_SP804
297 select GPIO_PL061 if GPIOLIB
298 select NEED_MACH_MEMORY_H
300 This enables support for ARM Ltd RealView boards.
302 config ARCH_VERSATILE
303 bool "ARM Ltd. Versatile family"
307 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
313 select PLAT_VERSATILE_FPGA_IRQ
314 select ARM_TIMER_SP804
316 This enables support for ARM Ltd Versatile board.
319 bool "ARM Ltd. Versatile Express family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select HAVE_MACH_CLKDEV
325 select GENERIC_CLOCKEVENTS
327 select HAVE_PATA_PLATFORM
330 select PLAT_VERSATILE
331 select PLAT_VERSATILE_CLCD
333 This enables support for the ARM Ltd Versatile Express boards.
337 select ARCH_REQUIRE_GPIOLIB
341 select NEED_MACH_IO_H if PCCARD
343 This enables support for systems based on the Atmel AT91RM9200,
347 bool "Broadcom BCMRING"
351 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
354 select ARCH_WANT_OPTIONAL_GPIOLIB
356 Support for Broadcom's BCMRing platform.
359 bool "Calxeda Highbank-based"
360 select ARCH_WANT_OPTIONAL_GPIOLIB
363 select ARM_TIMER_SP804
367 select GENERIC_CLOCKEVENTS
373 Support for the Calxeda Highbank SoC based boards.
376 bool "Cirrus Logic CLPS711x/EP721x-based"
378 select ARCH_USES_GETTIMEOFFSET
379 select NEED_MACH_MEMORY_H
381 Support for Cirrus Logic 711x/721x based boards.
384 bool "Cavium Networks CNS3XXX family"
386 select GENERIC_CLOCKEVENTS
388 select MIGHT_HAVE_CACHE_L2X0
389 select MIGHT_HAVE_PCI
390 select PCI_DOMAINS if PCI
392 Support for Cavium Networks CNS3XXX platform.
395 bool "Cortina Systems Gemini"
397 select ARCH_REQUIRE_GPIOLIB
398 select ARCH_USES_GETTIMEOFFSET
400 Support for the Cortina Systems Gemini family SoCs
403 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
406 select GENERIC_CLOCKEVENTS
408 select GENERIC_IRQ_CHIP
409 select MIGHT_HAVE_CACHE_L2X0
413 Support for CSR SiRFSoC ARM Cortex A9 Platform
420 select ARCH_USES_GETTIMEOFFSET
421 select NEED_MACH_IO_H
422 select NEED_MACH_MEMORY_H
424 This is an evaluation board for the StrongARM processor available
425 from Digital. It has limited hardware on-board, including an
426 Ethernet interface, two PCMCIA sockets, two serial ports and a
435 select ARCH_REQUIRE_GPIOLIB
436 select ARCH_HAS_HOLES_MEMORYMODEL
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_MEMORY_H
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
448 select NEED_MACH_IO_H
449 select NEED_MACH_MEMORY_H
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
455 bool "Freescale MXC/iMX-based"
456 select GENERIC_CLOCKEVENTS
457 select ARCH_REQUIRE_GPIOLIB
460 select GENERIC_IRQ_CHIP
461 select MULTI_IRQ_HANDLER
463 Support for Freescale MXC/iMX-based family of processors
466 bool "Freescale MXS-based"
467 select GENERIC_CLOCKEVENTS
468 select ARCH_REQUIRE_GPIOLIB
472 select HAVE_CLK_PREPARE
475 Support for Freescale MXS-based family of processors
478 bool "Hilscher NetX based"
482 select GENERIC_CLOCKEVENTS
484 This enables support for systems based on the Hilscher NetX Soc
487 bool "Hynix HMS720x-based"
490 select ARCH_USES_GETTIMEOFFSET
492 This enables support for systems based on the Hynix HMS720x
500 select ARCH_SUPPORTS_MSI
502 select NEED_MACH_IO_H
503 select NEED_MACH_MEMORY_H
504 select NEED_RET_TO_USER
506 Support for Intel's IOP13XX (XScale) family of processors.
512 select NEED_MACH_IO_H
513 select NEED_RET_TO_USER
516 select ARCH_REQUIRE_GPIOLIB
518 Support for Intel's 80219 and IOP32X (XScale) family of
525 select NEED_MACH_IO_H
526 select NEED_RET_TO_USER
529 select ARCH_REQUIRE_GPIOLIB
531 Support for Intel's IOP33X (XScale) family of processors.
538 select ARCH_USES_GETTIMEOFFSET
539 select NEED_MACH_IO_H
540 select NEED_MACH_MEMORY_H
542 Support for Intel's IXP23xx (XScale) family of processors.
545 bool "IXP2400/2800-based"
549 select ARCH_USES_GETTIMEOFFSET
550 select NEED_MACH_IO_H
551 select NEED_MACH_MEMORY_H
553 Support for Intel's IXP2400/2800 (XScale) family of processors.
558 select ARCH_HAS_DMA_SET_COHERENT_MASK
562 select GENERIC_CLOCKEVENTS
563 select MIGHT_HAVE_PCI
564 select NEED_MACH_IO_H
565 select DMABOUNCE if PCI
567 Support for Intel's IXP4XX (XScale) family of processors.
573 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select NEED_MACH_IO_H
578 Support for the Marvell Dove SoC 88AP510
581 bool "Marvell Kirkwood"
584 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
586 select NEED_MACH_IO_H
589 Support for the following Marvell Kirkwood series SoCs:
590 88F6180, 88F6192 and 88F6281.
596 select ARCH_REQUIRE_GPIOLIB
599 select USB_ARCH_HAS_OHCI
601 select GENERIC_CLOCKEVENTS
603 Support for the NXP LPC32XX family of processors
606 bool "Marvell MV78xx0"
609 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
611 select NEED_MACH_IO_H
614 Support for the following Marvell MV78xx0 series SoCs:
622 select ARCH_REQUIRE_GPIOLIB
623 select GENERIC_CLOCKEVENTS
626 Support for the following Marvell Orion 5x series SoCs:
627 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
628 Orion-2 (5281), Orion-1-90 (6183).
631 bool "Marvell PXA168/910/MMP2"
633 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
640 select GENERIC_ALLOCATOR
642 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
645 bool "Micrel/Kendin KS8695"
647 select ARCH_REQUIRE_GPIOLIB
648 select ARCH_USES_GETTIMEOFFSET
649 select NEED_MACH_MEMORY_H
651 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
652 System-on-Chip devices.
655 bool "Nuvoton W90X900 CPU"
657 select ARCH_REQUIRE_GPIOLIB
660 select GENERIC_CLOCKEVENTS
662 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
663 At present, the w90x900 has been renamed nuc900, regarding
664 the ARM series product line, you can login the following
665 link address to know more.
667 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
668 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
674 select GENERIC_CLOCKEVENTS
678 select MIGHT_HAVE_CACHE_L2X0
679 select NEED_MACH_IO_H if PCI
680 select ARCH_HAS_CPUFREQ
682 This enables support for NVIDIA Tegra based systems (Tegra APX,
683 Tegra 6xx and Tegra 2 series).
685 config ARCH_PICOXCELL
686 bool "Picochip picoXcell"
687 select ARCH_REQUIRE_GPIOLIB
688 select ARM_PATCH_PHYS_VIRT
692 select GENERIC_CLOCKEVENTS
699 This enables support for systems based on the Picochip picoXcell
700 family of Femtocell devices. The picoxcell support requires device tree
704 bool "Philips Nexperia PNX4008 Mobile"
707 select ARCH_USES_GETTIMEOFFSET
709 This enables support for Philips PNX4008 mobile platform.
712 bool "PXA2xx/PXA3xx-based"
715 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
719 select GENERIC_CLOCKEVENTS
725 select MULTI_IRQ_HANDLER
726 select ARM_CPU_SUSPEND if PM
729 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
734 select GENERIC_CLOCKEVENTS
735 select ARCH_REQUIRE_GPIOLIB
738 Support for Qualcomm MSM/QSD based systems. This runs on the
739 apps processor of the MSM/QSD and depends on a shared memory
740 interface to the modem processor which runs the baseband
741 stack and controls some vital subsystems
742 (clock and power control, etc).
745 bool "Renesas SH-Mobile / R-Mobile"
748 select HAVE_MACH_CLKDEV
750 select GENERIC_CLOCKEVENTS
751 select MIGHT_HAVE_CACHE_L2X0
754 select MULTI_IRQ_HANDLER
755 select PM_GENERIC_DOMAINS if PM
756 select NEED_MACH_MEMORY_H
758 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
764 select ARCH_MAY_HAVE_PC_FDC
765 select HAVE_PATA_PLATFORM
768 select ARCH_SPARSEMEM_ENABLE
769 select ARCH_USES_GETTIMEOFFSET
771 select NEED_MACH_IO_H
772 select NEED_MACH_MEMORY_H
774 On the Acorn Risc-PC, Linux can support the internal IDE disk and
775 CD-ROM interface, serial and parallel port, and the floppy drive.
782 select ARCH_SPARSEMEM_ENABLE
784 select ARCH_HAS_CPUFREQ
786 select GENERIC_CLOCKEVENTS
789 select ARCH_REQUIRE_GPIOLIB
791 select NEED_MACH_MEMORY_H
794 Support for StrongARM 11x0 based boards.
797 bool "Samsung S3C24XX SoCs"
799 select ARCH_HAS_CPUFREQ
802 select ARCH_USES_GETTIMEOFFSET
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select NEED_MACH_IO_H
808 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
809 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
810 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
811 Samsung SMDK2410 development board (and derivatives).
814 bool "Samsung S3C64XX"
822 select ARCH_USES_GETTIMEOFFSET
823 select ARCH_HAS_CPUFREQ
824 select ARCH_REQUIRE_GPIOLIB
825 select SAMSUNG_CLKSRC
826 select SAMSUNG_IRQ_VIC_TIMER
827 select S3C_GPIO_TRACK
829 select USB_ARCH_HAS_OHCI
830 select SAMSUNG_GPIOLIB_4BIT
831 select HAVE_S3C2410_I2C if I2C
832 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 Samsung S3C64XX series based systems
837 bool "Samsung S5P6440 S5P6450"
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C_RTC if RTC_CLASS
848 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
852 bool "Samsung S5PC100"
857 select ARCH_USES_GETTIMEOFFSET
858 select HAVE_S3C2410_I2C if I2C
859 select HAVE_S3C_RTC if RTC_CLASS
860 select HAVE_S3C2410_WATCHDOG if WATCHDOG
862 Samsung S5PC100 series based systems
865 bool "Samsung S5PV210/S5PC110"
867 select ARCH_SPARSEMEM_ENABLE
868 select ARCH_HAS_HOLES_MEMORYMODEL
873 select ARCH_HAS_CPUFREQ
874 select GENERIC_CLOCKEVENTS
875 select HAVE_S3C2410_I2C if I2C
876 select HAVE_S3C_RTC if RTC_CLASS
877 select HAVE_S3C2410_WATCHDOG if WATCHDOG
878 select NEED_MACH_MEMORY_H
880 Samsung S5PV210/S5PC110 series based systems
883 bool "SAMSUNG EXYNOS"
885 select ARCH_SPARSEMEM_ENABLE
886 select ARCH_HAS_HOLES_MEMORYMODEL
890 select ARCH_HAS_CPUFREQ
891 select GENERIC_CLOCKEVENTS
892 select HAVE_S3C_RTC if RTC_CLASS
893 select HAVE_S3C2410_I2C if I2C
894 select HAVE_S3C2410_WATCHDOG if WATCHDOG
895 select NEED_MACH_MEMORY_H
897 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
906 select ARCH_USES_GETTIMEOFFSET
907 select NEED_MACH_MEMORY_H
908 select NEED_MACH_IO_H
910 Support for the StrongARM based Digital DNARD machine, also known
911 as "Shark" (<http://www.shark-linux.de/shark.html>).
914 bool "ST-Ericsson U300 Series"
920 select ARM_PATCH_PHYS_VIRT
922 select GENERIC_CLOCKEVENTS
924 select HAVE_MACH_CLKDEV
926 select ARCH_REQUIRE_GPIOLIB
928 Support for ST-Ericsson U300 series mobile platforms.
931 bool "ST-Ericsson U8500 Series"
935 select GENERIC_CLOCKEVENTS
937 select ARCH_REQUIRE_GPIOLIB
938 select ARCH_HAS_CPUFREQ
940 select MIGHT_HAVE_CACHE_L2X0
942 Support for ST-Ericsson's Ux500 architecture
945 bool "STMicroelectronics Nomadik"
950 select GENERIC_CLOCKEVENTS
951 select MIGHT_HAVE_CACHE_L2X0
952 select ARCH_REQUIRE_GPIOLIB
954 Support for the Nomadik platform by ST-Ericsson
958 select GENERIC_CLOCKEVENTS
959 select ARCH_REQUIRE_GPIOLIB
963 select GENERIC_ALLOCATOR
964 select GENERIC_IRQ_CHIP
965 select ARCH_HAS_HOLES_MEMORYMODEL
967 Support for TI's DaVinci platform.
972 select ARCH_REQUIRE_GPIOLIB
973 select ARCH_HAS_CPUFREQ
975 select GENERIC_CLOCKEVENTS
976 select ARCH_HAS_HOLES_MEMORYMODEL
978 Support for TI's OMAP platform (OMAP1/2/3/4).
983 select ARCH_REQUIRE_GPIOLIB
987 select GENERIC_CLOCKEVENTS
990 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
993 bool "VIA/WonderMedia 85xx"
996 select ARCH_HAS_CPUFREQ
997 select GENERIC_CLOCKEVENTS
998 select ARCH_REQUIRE_GPIOLIB
1001 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1004 bool "Xilinx Zynq ARM Cortex A9 Platform"
1006 select GENERIC_CLOCKEVENTS
1007 select CLKDEV_LOOKUP
1011 select MIGHT_HAVE_CACHE_L2X0
1014 Support for Xilinx Zynq ARM Cortex A9 Platform
1018 # This is sorted alphabetically by mach-* pathname. However, plat-*
1019 # Kconfigs may be included either alphabetically (according to the
1020 # plat- suffix) or along side the corresponding mach-* source.
1022 source "arch/arm/mach-at91/Kconfig"
1024 source "arch/arm/mach-bcmring/Kconfig"
1026 source "arch/arm/mach-clps711x/Kconfig"
1028 source "arch/arm/mach-cns3xxx/Kconfig"
1030 source "arch/arm/mach-davinci/Kconfig"
1032 source "arch/arm/mach-dove/Kconfig"
1034 source "arch/arm/mach-ep93xx/Kconfig"
1036 source "arch/arm/mach-footbridge/Kconfig"
1038 source "arch/arm/mach-gemini/Kconfig"
1040 source "arch/arm/mach-h720x/Kconfig"
1042 source "arch/arm/mach-integrator/Kconfig"
1044 source "arch/arm/mach-iop32x/Kconfig"
1046 source "arch/arm/mach-iop33x/Kconfig"
1048 source "arch/arm/mach-iop13xx/Kconfig"
1050 source "arch/arm/mach-ixp4xx/Kconfig"
1052 source "arch/arm/mach-ixp2000/Kconfig"
1054 source "arch/arm/mach-ixp23xx/Kconfig"
1056 source "arch/arm/mach-kirkwood/Kconfig"
1058 source "arch/arm/mach-ks8695/Kconfig"
1060 source "arch/arm/mach-lpc32xx/Kconfig"
1062 source "arch/arm/mach-msm/Kconfig"
1064 source "arch/arm/mach-mv78xx0/Kconfig"
1066 source "arch/arm/plat-mxc/Kconfig"
1068 source "arch/arm/mach-mxs/Kconfig"
1070 source "arch/arm/mach-netx/Kconfig"
1072 source "arch/arm/mach-nomadik/Kconfig"
1073 source "arch/arm/plat-nomadik/Kconfig"
1075 source "arch/arm/plat-omap/Kconfig"
1077 source "arch/arm/mach-omap1/Kconfig"
1079 source "arch/arm/mach-omap2/Kconfig"
1081 source "arch/arm/mach-orion5x/Kconfig"
1083 source "arch/arm/mach-pxa/Kconfig"
1084 source "arch/arm/plat-pxa/Kconfig"
1086 source "arch/arm/mach-mmp/Kconfig"
1088 source "arch/arm/mach-realview/Kconfig"
1090 source "arch/arm/mach-sa1100/Kconfig"
1092 source "arch/arm/plat-samsung/Kconfig"
1093 source "arch/arm/plat-s3c24xx/Kconfig"
1094 source "arch/arm/plat-s5p/Kconfig"
1096 source "arch/arm/plat-spear/Kconfig"
1098 source "arch/arm/mach-s3c24xx/Kconfig"
1100 source "arch/arm/mach-s3c2412/Kconfig"
1101 source "arch/arm/mach-s3c2440/Kconfig"
1105 source "arch/arm/mach-s3c64xx/Kconfig"
1108 source "arch/arm/mach-s5p64x0/Kconfig"
1110 source "arch/arm/mach-s5pc100/Kconfig"
1112 source "arch/arm/mach-s5pv210/Kconfig"
1114 source "arch/arm/mach-exynos/Kconfig"
1116 source "arch/arm/mach-shmobile/Kconfig"
1118 source "arch/arm/mach-tegra/Kconfig"
1120 source "arch/arm/mach-u300/Kconfig"
1122 source "arch/arm/mach-ux500/Kconfig"
1124 source "arch/arm/mach-versatile/Kconfig"
1126 source "arch/arm/mach-vexpress/Kconfig"
1127 source "arch/arm/plat-versatile/Kconfig"
1129 source "arch/arm/mach-vt8500/Kconfig"
1131 source "arch/arm/mach-w90x900/Kconfig"
1133 # Definitions to make life easier
1139 select GENERIC_CLOCKEVENTS
1144 select GENERIC_IRQ_CHIP
1150 config PLAT_VERSATILE
1153 config ARM_TIMER_SP804
1156 select HAVE_SCHED_CLOCK
1158 source arch/arm/mm/Kconfig
1162 default 16 if ARCH_EP93XX
1166 bool "Enable iWMMXt support"
1167 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1168 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1170 Enable support for iWMMXt context switching at run time if
1171 running on a CPU that supports it.
1175 depends on CPU_XSCALE
1179 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1180 (!ARCH_OMAP3 || OMAP3_EMU)
1184 config MULTI_IRQ_HANDLER
1187 Allow each machine to specify it's own IRQ handler at run time.
1190 source "arch/arm/Kconfig-nommu"
1193 config ARM_ERRATA_326103
1194 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1197 Executing a SWP instruction to read-only memory does not set bit 11
1198 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1199 treat the access as a read, preventing a COW from occurring and
1200 causing the faulting task to livelock.
1202 config ARM_ERRATA_411920
1203 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1204 depends on CPU_V6 || CPU_V6K
1206 Invalidation of the Instruction Cache operation can
1207 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1208 It does not affect the MPCore. This option enables the ARM Ltd.
1209 recommended workaround.
1211 config ARM_ERRATA_430973
1212 bool "ARM errata: Stale prediction on replaced interworking branch"
1215 This option enables the workaround for the 430973 Cortex-A8
1216 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1217 interworking branch is replaced with another code sequence at the
1218 same virtual address, whether due to self-modifying code or virtual
1219 to physical address re-mapping, Cortex-A8 does not recover from the
1220 stale interworking branch prediction. This results in Cortex-A8
1221 executing the new code sequence in the incorrect ARM or Thumb state.
1222 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1223 and also flushes the branch target cache at every context switch.
1224 Note that setting specific bits in the ACTLR register may not be
1225 available in non-secure mode.
1227 config ARM_ERRATA_458693
1228 bool "ARM errata: Processor deadlock when a false hazard is created"
1231 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1232 erratum. For very specific sequences of memory operations, it is
1233 possible for a hazard condition intended for a cache line to instead
1234 be incorrectly associated with a different cache line. This false
1235 hazard might then cause a processor deadlock. The workaround enables
1236 the L1 caching of the NEON accesses and disables the PLD instruction
1237 in the ACTLR register. Note that setting specific bits in the ACTLR
1238 register may not be available in non-secure mode.
1240 config ARM_ERRATA_460075
1241 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1244 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1245 erratum. Any asynchronous access to the L2 cache may encounter a
1246 situation in which recent store transactions to the L2 cache are lost
1247 and overwritten with stale memory contents from external memory. The
1248 workaround disables the write-allocate mode for the L2 cache via the
1249 ACTLR register. Note that setting specific bits in the ACTLR register
1250 may not be available in non-secure mode.
1252 config ARM_ERRATA_742230
1253 bool "ARM errata: DMB operation may be faulty"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 742230 Cortex-A9
1257 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1258 between two write operations may not ensure the correct visibility
1259 ordering of the two writes. This workaround sets a specific bit in
1260 the diagnostic register of the Cortex-A9 which causes the DMB
1261 instruction to behave as a DSB, ensuring the correct behaviour of
1264 config ARM_ERRATA_742231
1265 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 742231 Cortex-A9
1269 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1270 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1271 accessing some data located in the same cache line, may get corrupted
1272 data due to bad handling of the address hazard when the line gets
1273 replaced from one of the CPUs at the same time as another CPU is
1274 accessing it. This workaround sets specific bits in the diagnostic
1275 register of the Cortex-A9 which reduces the linefill issuing
1276 capabilities of the processor.
1278 config PL310_ERRATA_588369
1279 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1280 depends on CACHE_L2X0
1282 The PL310 L2 cache controller implements three types of Clean &
1283 Invalidate maintenance operations: by Physical Address
1284 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1285 They are architecturally defined to behave as the execution of a
1286 clean operation followed immediately by an invalidate operation,
1287 both performing to the same memory location. This functionality
1288 is not correctly implemented in PL310 as clean lines are not
1289 invalidated as a result of these operations.
1291 config ARM_ERRATA_720789
1292 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1295 This option enables the workaround for the 720789 Cortex-A9 (prior to
1296 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1297 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1298 As a consequence of this erratum, some TLB entries which should be
1299 invalidated are not, resulting in an incoherency in the system page
1300 tables. The workaround changes the TLB flushing routines to invalidate
1301 entries regardless of the ASID.
1303 config PL310_ERRATA_727915
1304 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1305 depends on CACHE_L2X0
1307 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1308 operation (offset 0x7FC). This operation runs in background so that
1309 PL310 can handle normal accesses while it is in progress. Under very
1310 rare circumstances, due to this erratum, write data can be lost when
1311 PL310 treats a cacheable write transaction during a Clean &
1312 Invalidate by Way operation.
1314 config ARM_ERRATA_743622
1315 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1318 This option enables the workaround for the 743622 Cortex-A9
1319 (r2p*) erratum. Under very rare conditions, a faulty
1320 optimisation in the Cortex-A9 Store Buffer may lead to data
1321 corruption. This workaround sets a specific bit in the diagnostic
1322 register of the Cortex-A9 which disables the Store Buffer
1323 optimisation, preventing the defect from occurring. This has no
1324 visible impact on the overall performance or power consumption of the
1327 config ARM_ERRATA_751472
1328 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1331 This option enables the workaround for the 751472 Cortex-A9 (prior
1332 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1333 completion of a following broadcasted operation if the second
1334 operation is received by a CPU before the ICIALLUIS has completed,
1335 potentially leading to corrupted entries in the cache or TLB.
1337 config PL310_ERRATA_753970
1338 bool "PL310 errata: cache sync operation may be faulty"
1339 depends on CACHE_PL310
1341 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1343 Under some condition the effect of cache sync operation on
1344 the store buffer still remains when the operation completes.
1345 This means that the store buffer is always asked to drain and
1346 this prevents it from merging any further writes. The workaround
1347 is to replace the normal offset of cache sync operation (0x730)
1348 by another offset targeting an unmapped PL310 register 0x740.
1349 This has the same effect as the cache sync operation: store buffer
1350 drain and waiting for all buffers empty.
1352 config ARM_ERRATA_754322
1353 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1356 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1357 r3p*) erratum. A speculative memory access may cause a page table walk
1358 which starts prior to an ASID switch but completes afterwards. This
1359 can populate the micro-TLB with a stale entry which may be hit with
1360 the new ASID. This workaround places two dsb instructions in the mm
1361 switching code so that no page table walks can cross the ASID switch.
1363 config ARM_ERRATA_754327
1364 bool "ARM errata: no automatic Store Buffer drain"
1365 depends on CPU_V7 && SMP
1367 This option enables the workaround for the 754327 Cortex-A9 (prior to
1368 r2p0) erratum. The Store Buffer does not have any automatic draining
1369 mechanism and therefore a livelock may occur if an external agent
1370 continuously polls a memory location waiting to observe an update.
1371 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1372 written polling loops from denying visibility of updates to memory.
1374 config ARM_ERRATA_364296
1375 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1376 depends on CPU_V6 && !SMP
1378 This options enables the workaround for the 364296 ARM1136
1379 r0p2 erratum (possible cache data corruption with
1380 hit-under-miss enabled). It sets the undocumented bit 31 in
1381 the auxiliary control register and the FI bit in the control
1382 register, thus disabling hit-under-miss without putting the
1383 processor into full low interrupt latency mode. ARM11MPCore
1386 config ARM_ERRATA_764369
1387 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1388 depends on CPU_V7 && SMP
1390 This option enables the workaround for erratum 764369
1391 affecting Cortex-A9 MPCore with two or more processors (all
1392 current revisions). Under certain timing circumstances, a data
1393 cache line maintenance operation by MVA targeting an Inner
1394 Shareable memory region may fail to proceed up to either the
1395 Point of Coherency or to the Point of Unification of the
1396 system. This workaround adds a DSB instruction before the
1397 relevant cache maintenance functions and sets a specific bit
1398 in the diagnostic control register of the SCU.
1400 config PL310_ERRATA_769419
1401 bool "PL310 errata: no automatic Store Buffer drain"
1402 depends on CACHE_L2X0
1404 On revisions of the PL310 prior to r3p2, the Store Buffer does
1405 not automatically drain. This can cause normal, non-cacheable
1406 writes to be retained when the memory system is idle, leading
1407 to suboptimal I/O performance for drivers using coherent DMA.
1408 This option adds a write barrier to the cpu_idle loop so that,
1409 on systems with an outer cache, the store buffer is drained
1414 source "arch/arm/common/Kconfig"
1424 Find out whether you have ISA slots on your motherboard. ISA is the
1425 name of a bus system, i.e. the way the CPU talks to the other stuff
1426 inside your box. Other bus systems are PCI, EISA, MicroChannel
1427 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1428 newer boards don't support it. If you have ISA, say Y, otherwise N.
1430 # Select ISA DMA controller support
1435 # Select ISA DMA interface
1440 bool "PCI support" if MIGHT_HAVE_PCI
1442 Find out whether you have a PCI motherboard. PCI is the name of a
1443 bus system, i.e. the way the CPU talks to the other stuff inside
1444 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1445 VESA. If you have PCI, say Y, otherwise N.
1451 config PCI_NANOENGINE
1452 bool "BSE nanoEngine PCI support"
1453 depends on SA1100_NANOENGINE
1455 Enable PCI on the BSE nanoEngine board.
1460 # Select the host bridge type
1461 config PCI_HOST_VIA82C505
1463 depends on PCI && ARCH_SHARK
1466 config PCI_HOST_ITE8152
1468 depends on PCI && MACH_ARMCORE
1472 source "drivers/pci/Kconfig"
1474 source "drivers/pcmcia/Kconfig"
1478 menu "Kernel Features"
1480 source "kernel/time/Kconfig"
1485 This option should be selected by machines which have an SMP-
1488 The only effect of this option is to make the SMP-related
1489 options available to the user for configuration.
1492 bool "Symmetric Multi-Processing"
1493 depends on CPU_V6K || CPU_V7
1494 depends on GENERIC_CLOCKEVENTS
1497 select USE_GENERIC_SMP_HELPERS
1498 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1500 This enables support for systems with more than one CPU. If you have
1501 a system with only one CPU, like most personal computers, say N. If
1502 you have a system with more than one CPU, say Y.
1504 If you say N here, the kernel will run on single and multiprocessor
1505 machines, but will use only one CPU of a multiprocessor machine. If
1506 you say Y here, the kernel will run on many, but not all, single
1507 processor machines. On a single processor machine, the kernel will
1508 run faster if you say N here.
1510 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1511 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1512 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1514 If you don't know what to do here, say N.
1517 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1518 depends on EXPERIMENTAL
1519 depends on SMP && !XIP_KERNEL
1522 SMP kernels contain instructions which fail on non-SMP processors.
1523 Enabling this option allows the kernel to modify itself to make
1524 these instructions safe. Disabling it allows about 1K of space
1527 If you don't know what to do here, say Y.
1529 config ARM_CPU_TOPOLOGY
1530 bool "Support cpu topology definition"
1531 depends on SMP && CPU_V7
1534 Support ARM cpu topology definition. The MPIDR register defines
1535 affinity between processors which is then used to describe the cpu
1536 topology of an ARM System.
1539 bool "Multi-core scheduler support"
1540 depends on ARM_CPU_TOPOLOGY
1542 Multi-core scheduler support improves the CPU scheduler's decision
1543 making when dealing with multi-core CPU chips at a cost of slightly
1544 increased overhead in some places. If unsure say N here.
1547 bool "SMT scheduler support"
1548 depends on ARM_CPU_TOPOLOGY
1550 Improves the CPU scheduler's decision making when dealing with
1551 MultiThreading at a cost of slightly increased overhead in some
1552 places. If unsure say N here.
1557 This option enables support for the ARM system coherency unit
1564 This options enables support for the ARM timer and watchdog unit
1567 prompt "Memory split"
1570 Select the desired split between kernel and user memory.
1572 If you are not absolutely sure what you are doing, leave this
1576 bool "3G/1G user/kernel split"
1578 bool "2G/2G user/kernel split"
1580 bool "1G/3G user/kernel split"
1585 default 0x40000000 if VMSPLIT_1G
1586 default 0x80000000 if VMSPLIT_2G
1590 int "Maximum number of CPUs (2-32)"
1596 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1597 depends on SMP && HOTPLUG && EXPERIMENTAL
1599 Say Y here to experiment with turning CPUs off and on. CPUs
1600 can be controlled through /sys/devices/system/cpu.
1603 bool "Use local timer interrupts"
1606 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1608 Enable support for local timers on SMP platforms, rather then the
1609 legacy IPI broadcast method. Local timers allows the system
1610 accounting to be spread across the timer interval, preventing a
1611 "thundering herd" at every timer tick.
1615 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1616 default 355 if ARCH_U8500
1617 default 264 if MACH_H4700
1620 Maximum number of GPIOs in the system.
1622 If unsure, leave the default value.
1624 source kernel/Kconfig.preempt
1628 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1629 ARCH_S5PV210 || ARCH_EXYNOS4
1630 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1631 default AT91_TIMER_HZ if ARCH_AT91
1632 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1635 config THUMB2_KERNEL
1636 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1637 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1639 select ARM_ASM_UNIFIED
1642 By enabling this option, the kernel will be compiled in
1643 Thumb-2 mode. A compiler/assembler that understand the unified
1644 ARM-Thumb syntax is needed.
1648 config THUMB2_AVOID_R_ARM_THM_JUMP11
1649 bool "Work around buggy Thumb-2 short branch relocations in gas"
1650 depends on THUMB2_KERNEL && MODULES
1653 Various binutils versions can resolve Thumb-2 branches to
1654 locally-defined, preemptible global symbols as short-range "b.n"
1655 branch instructions.
1657 This is a problem, because there's no guarantee the final
1658 destination of the symbol, or any candidate locations for a
1659 trampoline, are within range of the branch. For this reason, the
1660 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1661 relocation in modules at all, and it makes little sense to add
1664 The symptom is that the kernel fails with an "unsupported
1665 relocation" error when loading some modules.
1667 Until fixed tools are available, passing
1668 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1669 code which hits this problem, at the cost of a bit of extra runtime
1670 stack usage in some cases.
1672 The problem is described in more detail at:
1673 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1675 Only Thumb-2 kernels are affected.
1677 Unless you are sure your tools don't have this problem, say Y.
1679 config ARM_ASM_UNIFIED
1683 bool "Use the ARM EABI to compile the kernel"
1685 This option allows for the kernel to be compiled using the latest
1686 ARM ABI (aka EABI). This is only useful if you are using a user
1687 space environment that is also compiled with EABI.
1689 Since there are major incompatibilities between the legacy ABI and
1690 EABI, especially with regard to structure member alignment, this
1691 option also changes the kernel syscall calling convention to
1692 disambiguate both ABIs and allow for backward compatibility support
1693 (selected with CONFIG_OABI_COMPAT).
1695 To use this you need GCC version 4.0.0 or later.
1698 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1699 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1702 This option preserves the old syscall interface along with the
1703 new (ARM EABI) one. It also provides a compatibility layer to
1704 intercept syscalls that have structure arguments which layout
1705 in memory differs between the legacy ABI and the new ARM EABI
1706 (only for non "thumb" binaries). This option adds a tiny
1707 overhead to all syscalls and produces a slightly larger kernel.
1708 If you know you'll be using only pure EABI user space then you
1709 can say N here. If this option is not selected and you attempt
1710 to execute a legacy ABI binary then the result will be
1711 UNPREDICTABLE (in fact it can be predicted that it won't work
1712 at all). If in doubt say Y.
1714 config ARCH_HAS_HOLES_MEMORYMODEL
1717 config ARCH_SPARSEMEM_ENABLE
1720 config ARCH_SPARSEMEM_DEFAULT
1721 def_bool ARCH_SPARSEMEM_ENABLE
1723 config ARCH_SELECT_MEMORY_MODEL
1724 def_bool ARCH_SPARSEMEM_ENABLE
1726 config HAVE_ARCH_PFN_VALID
1727 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1730 bool "High Memory Support"
1733 The address space of ARM processors is only 4 Gigabytes large
1734 and it has to accommodate user address space, kernel address
1735 space as well as some memory mapped IO. That means that, if you
1736 have a large amount of physical memory and/or IO, not all of the
1737 memory can be "permanently mapped" by the kernel. The physical
1738 memory that is not permanently mapped is called "high memory".
1740 Depending on the selected kernel/user memory split, minimum
1741 vmalloc space and actual amount of RAM, you may not need this
1742 option which should result in a slightly faster kernel.
1747 bool "Allocate 2nd-level pagetables from highmem"
1750 config HW_PERF_EVENTS
1751 bool "Enable hardware performance counter support for perf events"
1752 depends on PERF_EVENTS && CPU_HAS_PMU
1755 Enable hardware performance counter support for perf events. If
1756 disabled, perf events will use software events only.
1760 config FORCE_MAX_ZONEORDER
1761 int "Maximum zone order" if ARCH_SHMOBILE
1762 range 11 64 if ARCH_SHMOBILE
1763 default "9" if SA1111
1766 The kernel memory allocator divides physically contiguous memory
1767 blocks into "zones", where each zone is a power of two number of
1768 pages. This option selects the largest power of two that the kernel
1769 keeps in the memory allocator. If you need to allocate very large
1770 blocks of physically contiguous memory, then you may need to
1771 increase this value.
1773 This config option is actually maximum order plus one. For example,
1774 a value of 11 means that the largest free memory block is 2^10 pages.
1777 bool "Timer and CPU usage LEDs"
1778 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1779 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1780 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1781 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1782 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1783 ARCH_AT91 || ARCH_DAVINCI || \
1784 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1786 If you say Y here, the LEDs on your machine will be used
1787 to provide useful information about your current system status.
1789 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1790 be able to select which LEDs are active using the options below. If
1791 you are compiling a kernel for the EBSA-110 or the LART however, the
1792 red LED will simply flash regularly to indicate that the system is
1793 still functional. It is safe to say Y here if you have a CATS
1794 system, but the driver will do nothing.
1797 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1798 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1799 || MACH_OMAP_PERSEUS2
1801 depends on !GENERIC_CLOCKEVENTS
1802 default y if ARCH_EBSA110
1804 If you say Y here, one of the system LEDs (the green one on the
1805 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1806 will flash regularly to indicate that the system is still
1807 operational. This is mainly useful to kernel hackers who are
1808 debugging unstable kernels.
1810 The LART uses the same LED for both Timer LED and CPU usage LED
1811 functions. You may choose to use both, but the Timer LED function
1812 will overrule the CPU usage LED.
1815 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1817 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1818 || MACH_OMAP_PERSEUS2
1821 If you say Y here, the red LED will be used to give a good real
1822 time indication of CPU usage, by lighting whenever the idle task
1823 is not currently executing.
1825 The LART uses the same LED for both Timer LED and CPU usage LED
1826 functions. You may choose to use both, but the Timer LED function
1827 will overrule the CPU usage LED.
1829 config ALIGNMENT_TRAP
1831 depends on CPU_CP15_MMU
1832 default y if !ARCH_EBSA110
1833 select HAVE_PROC_CPU if PROC_FS
1835 ARM processors cannot fetch/store information which is not
1836 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1837 address divisible by 4. On 32-bit ARM processors, these non-aligned
1838 fetch/store instructions will be emulated in software if you say
1839 here, which has a severe performance impact. This is necessary for
1840 correct operation of some network protocols. With an IP-only
1841 configuration it is safe to say N, otherwise say Y.
1843 config UACCESS_WITH_MEMCPY
1844 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1845 depends on MMU && EXPERIMENTAL
1846 default y if CPU_FEROCEON
1848 Implement faster copy_to_user and clear_user methods for CPU
1849 cores where a 8-word STM instruction give significantly higher
1850 memory write throughput than a sequence of individual 32bit stores.
1852 A possible side effect is a slight increase in scheduling latency
1853 between threads sharing the same address space if they invoke
1854 such copy operations with large buffers.
1856 However, if the CPU data cache is using a write-allocate mode,
1857 this option is unlikely to provide any performance gain.
1861 prompt "Enable seccomp to safely compute untrusted bytecode"
1863 This kernel feature is useful for number crunching applications
1864 that may need to compute untrusted bytecode during their
1865 execution. By using pipes or other transports made available to
1866 the process as file descriptors supporting the read/write
1867 syscalls, it's possible to isolate those applications in
1868 their own address space using seccomp. Once seccomp is
1869 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1870 and the task is only allowed to execute a few safe syscalls
1871 defined by each seccomp mode.
1873 config CC_STACKPROTECTOR
1874 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1875 depends on EXPERIMENTAL
1877 This option turns on the -fstack-protector GCC feature. This
1878 feature puts, at the beginning of functions, a canary value on
1879 the stack just before the return address, and validates
1880 the value just before actually returning. Stack based buffer
1881 overflows (that need to overwrite this return address) now also
1882 overwrite the canary, which gets detected and the attack is then
1883 neutralized via a kernel panic.
1884 This feature requires gcc version 4.2 or above.
1886 config DEPRECATED_PARAM_STRUCT
1887 bool "Provide old way to pass kernel parameters"
1889 This was deprecated in 2001 and announced to live on for 5 years.
1890 Some old boot loaders still use this way.
1897 bool "Flattened Device Tree support"
1899 select OF_EARLY_FLATTREE
1902 Include support for flattened device tree machine descriptions.
1904 # Compressed boot loader in ROM. Yes, we really want to ask about
1905 # TEXT and BSS so we preserve their values in the config files.
1906 config ZBOOT_ROM_TEXT
1907 hex "Compressed ROM boot loader base address"
1910 The physical address at which the ROM-able zImage is to be
1911 placed in the target. Platforms which normally make use of
1912 ROM-able zImage formats normally set this to a suitable
1913 value in their defconfig file.
1915 If ZBOOT_ROM is not enabled, this has no effect.
1917 config ZBOOT_ROM_BSS
1918 hex "Compressed ROM boot loader BSS address"
1921 The base address of an area of read/write memory in the target
1922 for the ROM-able zImage which must be available while the
1923 decompressor is running. It must be large enough to hold the
1924 entire decompressed kernel plus an additional 128 KiB.
1925 Platforms which normally make use of ROM-able zImage formats
1926 normally set this to a suitable value in their defconfig file.
1928 If ZBOOT_ROM is not enabled, this has no effect.
1931 bool "Compressed boot loader in ROM/flash"
1932 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1934 Say Y here if you intend to execute your compressed kernel image
1935 (zImage) directly from ROM or flash. If unsure, say N.
1938 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1939 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1940 default ZBOOT_ROM_NONE
1942 Include experimental SD/MMC loading code in the ROM-able zImage.
1943 With this enabled it is possible to write the the ROM-able zImage
1944 kernel image to an MMC or SD card and boot the kernel straight
1945 from the reset vector. At reset the processor Mask ROM will load
1946 the first part of the the ROM-able zImage which in turn loads the
1947 rest the kernel image to RAM.
1949 config ZBOOT_ROM_NONE
1950 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1952 Do not load image from SD or MMC
1954 config ZBOOT_ROM_MMCIF
1955 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1957 Load image from MMCIF hardware block.
1959 config ZBOOT_ROM_SH_MOBILE_SDHI
1960 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1962 Load image from SDHI hardware block
1966 config ARM_APPENDED_DTB
1967 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1968 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1970 With this option, the boot code will look for a device tree binary
1971 (DTB) appended to zImage
1972 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1974 This is meant as a backward compatibility convenience for those
1975 systems with a bootloader that can't be upgraded to accommodate
1976 the documented boot protocol using a device tree.
1978 Beware that there is very little in terms of protection against
1979 this option being confused by leftover garbage in memory that might
1980 look like a DTB header after a reboot if no actual DTB is appended
1981 to zImage. Do not leave this option active in a production kernel
1982 if you don't intend to always append a DTB. Proper passing of the
1983 location into r2 of a bootloader provided DTB is always preferable
1986 config ARM_ATAG_DTB_COMPAT
1987 bool "Supplement the appended DTB with traditional ATAG information"
1988 depends on ARM_APPENDED_DTB
1990 Some old bootloaders can't be updated to a DTB capable one, yet
1991 they provide ATAGs with memory configuration, the ramdisk address,
1992 the kernel cmdline string, etc. Such information is dynamically
1993 provided by the bootloader and can't always be stored in a static
1994 DTB. To allow a device tree enabled kernel to be used with such
1995 bootloaders, this option allows zImage to extract the information
1996 from the ATAG list and store it at run time into the appended DTB.
1999 string "Default kernel command string"
2002 On some architectures (EBSA110 and CATS), there is currently no way
2003 for the boot loader to pass arguments to the kernel. For these
2004 architectures, you should supply some command-line options at build
2005 time by entering them here. As a minimum, you should specify the
2006 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2009 prompt "Kernel command line type" if CMDLINE != ""
2010 default CMDLINE_FROM_BOOTLOADER
2012 config CMDLINE_FROM_BOOTLOADER
2013 bool "Use bootloader kernel arguments if available"
2015 Uses the command-line options passed by the boot loader. If
2016 the boot loader doesn't provide any, the default kernel command
2017 string provided in CMDLINE will be used.
2019 config CMDLINE_EXTEND
2020 bool "Extend bootloader kernel arguments"
2022 The command-line arguments provided by the boot loader will be
2023 appended to the default kernel command string.
2025 config CMDLINE_FORCE
2026 bool "Always use the default kernel command string"
2028 Always use the default kernel command string, even if the boot
2029 loader passes other arguments to the kernel.
2030 This is useful if you cannot or don't want to change the
2031 command-line options your boot loader passes to the kernel.
2035 bool "Kernel Execute-In-Place from ROM"
2036 depends on !ZBOOT_ROM && !ARM_LPAE
2038 Execute-In-Place allows the kernel to run from non-volatile storage
2039 directly addressable by the CPU, such as NOR flash. This saves RAM
2040 space since the text section of the kernel is not loaded from flash
2041 to RAM. Read-write sections, such as the data section and stack,
2042 are still copied to RAM. The XIP kernel is not compressed since
2043 it has to run directly from flash, so it will take more space to
2044 store it. The flash address used to link the kernel object files,
2045 and for storing it, is configuration dependent. Therefore, if you
2046 say Y here, you must know the proper physical address where to
2047 store the kernel image depending on your own flash memory usage.
2049 Also note that the make target becomes "make xipImage" rather than
2050 "make zImage" or "make Image". The final kernel binary to put in
2051 ROM memory will be arch/arm/boot/xipImage.
2055 config XIP_PHYS_ADDR
2056 hex "XIP Kernel Physical Location"
2057 depends on XIP_KERNEL
2058 default "0x00080000"
2060 This is the physical address in your flash memory the kernel will
2061 be linked for and stored to. This address is dependent on your
2065 bool "Kexec system call (EXPERIMENTAL)"
2066 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2068 kexec is a system call that implements the ability to shutdown your
2069 current kernel, and to start another kernel. It is like a reboot
2070 but it is independent of the system firmware. And like a reboot
2071 you can start any kernel with it, not just Linux.
2073 It is an ongoing process to be certain the hardware in a machine
2074 is properly shutdown, so do not be surprised if this code does not
2075 initially work for you. It may help to enable device hotplugging
2079 bool "Export atags in procfs"
2083 Should the atags used to boot the kernel be exported in an "atags"
2084 file in procfs. Useful with kexec.
2087 bool "Build kdump crash kernel (EXPERIMENTAL)"
2088 depends on EXPERIMENTAL
2090 Generate crash dump after being started by kexec. This should
2091 be normally only set in special crash dump kernels which are
2092 loaded in the main kernel with kexec-tools into a specially
2093 reserved region and then later executed after a crash by
2094 kdump/kexec. The crash dump kernel must be compiled to a
2095 memory address not used by the main kernel
2097 For more details see Documentation/kdump/kdump.txt
2099 config AUTO_ZRELADDR
2100 bool "Auto calculation of the decompressed kernel image address"
2101 depends on !ZBOOT_ROM && !ARCH_U300
2103 ZRELADDR is the physical address where the decompressed kernel
2104 image will be placed. If AUTO_ZRELADDR is selected, the address
2105 will be determined at run-time by masking the current IP with
2106 0xf8000000. This assumes the zImage being placed in the first 128MB
2107 from start of memory.
2111 menu "CPU Power Management"
2115 source "drivers/cpufreq/Kconfig"
2118 tristate "CPUfreq driver for i.MX CPUs"
2119 depends on ARCH_MXC && CPU_FREQ
2121 This enables the CPUfreq driver for i.MX CPUs.
2123 config CPU_FREQ_SA1100
2126 config CPU_FREQ_SA1110
2129 config CPU_FREQ_INTEGRATOR
2130 tristate "CPUfreq driver for ARM Integrator CPUs"
2131 depends on ARCH_INTEGRATOR && CPU_FREQ
2134 This enables the CPUfreq driver for ARM Integrator CPUs.
2136 For details, take a look at <file:Documentation/cpu-freq>.
2142 depends on CPU_FREQ && ARCH_PXA && PXA25x
2144 select CPU_FREQ_TABLE
2145 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2150 Internal configuration node for common cpufreq on Samsung SoC
2152 config CPU_FREQ_S3C24XX
2153 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2154 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2157 This enables the CPUfreq driver for the Samsung S3C24XX family
2160 For details, take a look at <file:Documentation/cpu-freq>.
2164 config CPU_FREQ_S3C24XX_PLL
2165 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2166 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2168 Compile in support for changing the PLL frequency from the
2169 S3C24XX series CPUfreq driver. The PLL takes time to settle
2170 after a frequency change, so by default it is not enabled.
2172 This also means that the PLL tables for the selected CPU(s) will
2173 be built which may increase the size of the kernel image.
2175 config CPU_FREQ_S3C24XX_DEBUG
2176 bool "Debug CPUfreq Samsung driver core"
2177 depends on CPU_FREQ_S3C24XX
2179 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2181 config CPU_FREQ_S3C24XX_IODEBUG
2182 bool "Debug CPUfreq Samsung driver IO timing"
2183 depends on CPU_FREQ_S3C24XX
2185 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2187 config CPU_FREQ_S3C24XX_DEBUGFS
2188 bool "Export debugfs for CPUFreq"
2189 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2191 Export status information via debugfs.
2195 source "drivers/cpuidle/Kconfig"
2199 menu "Floating point emulation"
2201 comment "At least one emulation must be selected"
2204 bool "NWFPE math emulation"
2205 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2207 Say Y to include the NWFPE floating point emulator in the kernel.
2208 This is necessary to run most binaries. Linux does not currently
2209 support floating point hardware so you need to say Y here even if
2210 your machine has an FPA or floating point co-processor podule.
2212 You may say N here if you are going to load the Acorn FPEmulator
2213 early in the bootup.
2216 bool "Support extended precision"
2217 depends on FPE_NWFPE
2219 Say Y to include 80-bit support in the kernel floating-point
2220 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2221 Note that gcc does not generate 80-bit operations by default,
2222 so in most cases this option only enlarges the size of the
2223 floating point emulator without any good reason.
2225 You almost surely want to say N here.
2228 bool "FastFPE math emulation (EXPERIMENTAL)"
2229 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2231 Say Y here to include the FAST floating point emulator in the kernel.
2232 This is an experimental much faster emulator which now also has full
2233 precision for the mantissa. It does not support any exceptions.
2234 It is very simple, and approximately 3-6 times faster than NWFPE.
2236 It should be sufficient for most programs. It may be not suitable
2237 for scientific calculations, but you have to check this for yourself.
2238 If you do not feel you need a faster FP emulation you should better
2242 bool "VFP-format floating point maths"
2243 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2245 Say Y to include VFP support code in the kernel. This is needed
2246 if your hardware includes a VFP unit.
2248 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2249 release notes and additional status information.
2251 Say N if your target does not have VFP hardware.
2259 bool "Advanced SIMD (NEON) Extension support"
2260 depends on VFPv3 && CPU_V7
2262 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2267 menu "Userspace binary formats"
2269 source "fs/Kconfig.binfmt"
2272 tristate "RISC OS personality"
2275 Say Y here to include the kernel code necessary if you want to run
2276 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2277 experimental; if this sounds frightening, say N and sleep in peace.
2278 You can also say M here to compile this support as a module (which
2279 will be called arthur).
2283 menu "Power management options"
2285 source "kernel/power/Kconfig"
2287 config ARCH_SUSPEND_POSSIBLE
2288 depends on !ARCH_S5PC100
2289 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2290 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2293 config ARM_CPU_SUSPEND
2298 source "net/Kconfig"
2300 source "drivers/Kconfig"
2304 source "arch/arm/Kconfig.debug"
2306 source "security/Kconfig"
2308 source "crypto/Kconfig"
2310 source "lib/Kconfig"