4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SCHED_CLOCK
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_STRNCPY_FROM_USER
21 select GENERIC_STRNLEN_USER
22 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_DEBUG_KMEMLEAK
31 select HAVE_DMA_API_DEBUG
33 select HAVE_DMA_CONTIGUOUS if MMU
34 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
35 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
36 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
37 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
38 select HAVE_GENERIC_DMA_COHERENT
39 select HAVE_GENERIC_HARDIRQS
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
52 select HAVE_PERF_EVENTS
53 select HAVE_REGS_AND_STACK_ACCESS_API
54 select HAVE_SYSCALL_TRACEPOINTS
57 select PERF_USE_VMALLOC
59 select SYS_SUPPORTS_APM_EMULATION
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select MODULES_USE_ELF_REL
62 select CLONE_BACKWARDS
63 select OLD_SIGSUSPEND3
65 select HAVE_CONTEXT_TRACKING
67 The ARM series is a line of low-power-consumption RISC chip designs
68 licensed by ARM Ltd and targeted at embedded applications and
69 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
70 manufactured, but legacy ARM-based PC hardware remains popular in
71 Europe. There is an ARM Linux project with a web page at
72 <http://www.arm.linux.org.uk/>.
74 config ARM_HAS_SG_CHAIN
77 config NEED_SG_DMA_LENGTH
80 config ARM_DMA_USE_IOMMU
82 select ARM_HAS_SG_CHAIN
83 select NEED_SG_DMA_LENGTH
87 config ARM_DMA_IOMMU_ALIGNMENT
88 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
92 DMA mapping framework by default aligns all buffers to the smallest
93 PAGE_SIZE order which is greater than or equal to the requested buffer
94 size. This works well for buffers up to a few hundreds kilobytes, but
95 for larger buffers it just a waste of address space. Drivers which has
96 relatively small addressing window (like 64Mib) might run out of
97 virtual space with just a few allocations.
99 With this parameter you can specify the maximum PAGE_SIZE order for
100 DMA IOMMU buffers. Larger buffers will be aligned only to this
101 specified order. The order is expressed as a power of two multiplied
109 config MIGHT_HAVE_PCI
112 config SYS_SUPPORTS_APM_EMULATION
117 select GENERIC_ALLOCATOR
128 The Extended Industry Standard Architecture (EISA) bus was
129 developed as an open alternative to the IBM MicroChannel bus.
131 The EISA bus provided some of the features of the IBM MicroChannel
132 bus while maintaining backward compatibility with cards made for
133 the older ISA bus. The EISA bus saw limited use between 1988 and
134 1995 when it was made obsolete by the PCI bus.
136 Say Y here if you are building a kernel for an EISA-based machine.
143 config STACKTRACE_SUPPORT
147 config HAVE_LATENCYTOP_SUPPORT
152 config LOCKDEP_SUPPORT
156 config TRACE_IRQFLAGS_SUPPORT
160 config RWSEM_GENERIC_SPINLOCK
164 config RWSEM_XCHGADD_ALGORITHM
167 config ARCH_HAS_ILOG2_U32
170 config ARCH_HAS_ILOG2_U64
173 config ARCH_HAS_CPUFREQ
176 Internal node to signify that the ARCH has CPUFREQ support
177 and that the relevant menu configurations are displayed for
180 config ARCH_HAS_BANDGAP
183 config GENERIC_HWEIGHT
187 config GENERIC_CALIBRATE_DELAY
191 config ARCH_MAY_HAVE_PC_FDC
197 config NEED_DMA_MAP_STATE
200 config ARCH_HAS_DMA_SET_COHERENT_MASK
203 config GENERIC_ISA_DMA
209 config NEED_RET_TO_USER
217 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
218 default DRAM_BASE if REMAP_VECTORS_TO_RAM
221 The base address of exception vectors.
223 config ARM_PATCH_PHYS_VIRT
224 bool "Patch physical to virtual translations at runtime" if EMBEDDED
226 depends on !XIP_KERNEL && MMU
227 depends on !ARCH_REALVIEW || !SPARSEMEM
229 Patch phys-to-virt and virt-to-phys translation functions at
230 boot and module load time according to the position of the
231 kernel in system memory.
233 This can only be used with non-XIP MMU kernels where the base
234 of physical memory is at a 16MB boundary.
236 Only disable this option if you know that you do not require
237 this feature (eg, building a kernel for a single machine) and
238 you need to shrink the kernel to the minimal size.
240 config NEED_MACH_GPIO_H
243 Select this when mach/gpio.h is required to provide special
244 definitions for this platform. The need for mach/gpio.h should
245 be avoided when possible.
247 config NEED_MACH_IO_H
250 Select this when mach/io.h is required to provide special
251 definitions for this platform. The need for mach/io.h should
252 be avoided when possible.
254 config NEED_MACH_MEMORY_H
257 Select this when mach/memory.h is required to provide special
258 definitions for this platform. The need for mach/memory.h should
259 be avoided when possible.
262 hex "Physical address of main memory" if MMU
263 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
264 default DRAM_BASE if !MMU
266 Please provide the physical address corresponding to the
267 location of main memory in your system.
273 source "init/Kconfig"
275 source "kernel/Kconfig.freezer"
280 bool "MMU-based Paged Memory Management Support"
283 Select if you want MMU-based virtualised addressing space
284 support by paged memory management. If unsure, say 'Y'.
287 # The "ARM system type" choice list is ordered alphabetically by option
288 # text. Please add new entries in the option alphabetic order.
291 prompt "ARM system type"
292 default ARCH_VERSATILE if !MMU
293 default ARCH_MULTIPLATFORM if MMU
295 config ARCH_MULTIPLATFORM
296 bool "Allow multiple platforms to be selected"
298 select ARM_PATCH_PHYS_VIRT
301 select MULTI_IRQ_HANDLER
305 config ARCH_INTEGRATOR
306 bool "ARM Ltd. Integrator family"
307 select ARCH_HAS_CPUFREQ
310 select COMMON_CLK_VERSATILE
311 select GENERIC_CLOCKEVENTS
314 select MULTI_IRQ_HANDLER
315 select NEED_MACH_MEMORY_H
316 select PLAT_VERSATILE
318 select VERSATILE_FPGA_IRQ
320 Support for ARM's Integrator platform.
323 bool "ARM Ltd. RealView family"
324 select ARCH_WANT_OPTIONAL_GPIOLIB
326 select ARM_TIMER_SP804
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
330 select GPIO_PL061 if GPIOLIB
332 select NEED_MACH_MEMORY_H
333 select PLAT_VERSATILE
334 select PLAT_VERSATILE_CLCD
336 This enables support for ARM Ltd RealView boards.
338 config ARCH_VERSATILE
339 bool "ARM Ltd. Versatile family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
345 select GENERIC_CLOCKEVENTS
346 select HAVE_MACH_CLKDEV
348 select PLAT_VERSATILE
349 select PLAT_VERSATILE_CLCD
350 select PLAT_VERSATILE_CLOCK
351 select VERSATILE_FPGA_IRQ
353 This enables support for ARM Ltd Versatile board.
357 select ARCH_REQUIRE_GPIOLIB
361 select NEED_MACH_GPIO_H
362 select NEED_MACH_IO_H if PCCARD
364 select PINCTRL_AT91 if USE_OF
366 This enables support for systems based on Atmel
367 AT91RM9200 and AT91SAM9* processors.
370 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
371 select ARCH_REQUIRE_GPIOLIB
377 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
382 Support for Cirrus Logic 711x/721x/731x based boards.
385 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_USES_GETTIMEOFFSET
388 select NEED_MACH_GPIO_H
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_IO_H
399 select NEED_MACH_MEMORY_H
402 This is an evaluation board for the StrongARM processor available
403 from Digital. It has limited hardware on-board, including an
404 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 select ARCH_HAS_HOLES_MEMORYMODEL
410 select ARCH_REQUIRE_GPIOLIB
411 select ARCH_USES_GETTIMEOFFSET
416 select NEED_MACH_MEMORY_H
418 This enables support for the Cirrus EP93xx series of CPUs.
420 config ARCH_FOOTBRIDGE
424 select GENERIC_CLOCKEVENTS
426 select NEED_MACH_IO_H if !MMU
427 select NEED_MACH_MEMORY_H
429 Support for systems based on the DC21285 companion chip
430 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
433 bool "Hilscher NetX based"
437 select GENERIC_CLOCKEVENTS
439 This enables support for systems based on the Hilscher NetX Soc
444 select ARCH_SUPPORTS_MSI
446 select NEED_MACH_MEMORY_H
447 select NEED_RET_TO_USER
452 Support for Intel's IOP13XX (XScale) family of processors.
457 select ARCH_REQUIRE_GPIOLIB
459 select NEED_MACH_GPIO_H
460 select NEED_RET_TO_USER
464 Support for Intel's 80219 and IOP32X (XScale) family of
470 select ARCH_REQUIRE_GPIOLIB
472 select NEED_MACH_GPIO_H
473 select NEED_RET_TO_USER
477 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_HAS_DMA_SET_COHERENT_MASK
483 select ARCH_REQUIRE_GPIOLIB
486 select DMABOUNCE if PCI
487 select GENERIC_CLOCKEVENTS
488 select MIGHT_HAVE_PCI
489 select NEED_MACH_IO_H
490 select USB_EHCI_BIG_ENDIAN_MMIO
491 select USB_EHCI_BIG_ENDIAN_DESC
493 Support for Intel's IXP4XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
499 select GENERIC_CLOCKEVENTS
500 select MIGHT_HAVE_PCI
503 select PLAT_ORION_LEGACY
504 select USB_ARCH_HAS_EHCI
507 Support for the Marvell Dove SoC 88AP510
510 bool "Marvell Kirkwood"
511 select ARCH_HAS_CPUFREQ
512 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
518 select PINCTRL_KIRKWOOD
519 select PLAT_ORION_LEGACY
522 Support for the following Marvell Kirkwood series SoCs:
523 88F6180, 88F6192 and 88F6281.
526 bool "Marvell MV78xx0"
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
534 Support for the following Marvell MV78xx0 series SoCs:
540 select ARCH_REQUIRE_GPIOLIB
542 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
547 Support for the following Marvell Orion 5x series SoCs:
548 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
549 Orion-2 (5281), Orion-1-90 (6183).
552 bool "Marvell PXA168/910/MMP2"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_ALLOCATOR
557 select GENERIC_CLOCKEVENTS
560 select NEED_MACH_GPIO_H
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
604 select USB_ARCH_HAS_OHCI
607 Support for the NXP LPC32XX family of processors
610 bool "PXA2xx/PXA3xx-based"
612 select ARCH_HAS_CPUFREQ
614 select ARCH_REQUIRE_GPIOLIB
615 select ARM_CPU_SUSPEND if PM
619 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
623 select NEED_MACH_GPIO_H
627 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Qualcomm MSM/QSD based systems. This runs on the
637 apps processor of the MSM/QSD and depends on a shared memory
638 interface to the modem processor which runs the baseband
639 stack and controls some vital subsystems
640 (clock and power control, etc).
643 bool "Renesas SH-Mobile / R-Mobile"
644 select ARM_PATCH_PHYS_VIRT
646 select GENERIC_CLOCKEVENTS
647 select HAVE_ARM_SCU if SMP
648 select HAVE_ARM_TWD if LOCAL_TIMERS
650 select HAVE_MACH_CLKDEV
652 select MIGHT_HAVE_CACHE_L2X0
653 select MULTI_IRQ_HANDLER
656 select PM_GENERIC_DOMAINS if PM
659 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
664 select ARCH_MAY_HAVE_PC_FDC
665 select ARCH_SPARSEMEM_ENABLE
666 select ARCH_USES_GETTIMEOFFSET
669 select HAVE_PATA_PLATFORM
671 select NEED_MACH_IO_H
672 select NEED_MACH_MEMORY_H
676 On the Acorn Risc-PC, Linux can support the internal IDE disk and
677 CD-ROM interface, serial and parallel port, and the floppy drive.
681 select ARCH_HAS_CPUFREQ
683 select ARCH_REQUIRE_GPIOLIB
684 select ARCH_SPARSEMEM_ENABLE
689 select GENERIC_CLOCKEVENTS
692 select NEED_MACH_GPIO_H
693 select NEED_MACH_MEMORY_H
696 Support for StrongARM 11x0 based boards.
699 bool "Samsung S3C24XX SoCs"
700 select ARCH_HAS_CPUFREQ
701 select ARCH_REQUIRE_GPIOLIB
704 select GENERIC_CLOCKEVENTS
707 select HAVE_S3C2410_I2C if I2C
708 select HAVE_S3C2410_WATCHDOG if WATCHDOG
709 select HAVE_S3C_RTC if RTC_CLASS
710 select MULTI_IRQ_HANDLER
711 select NEED_MACH_GPIO_H
712 select NEED_MACH_IO_H
715 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
716 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
717 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
718 Samsung SMDK2410 development board (and derivatives).
721 bool "Samsung S3C64XX"
722 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
728 select GENERIC_CLOCKEVENTS
731 select HAVE_S3C2410_I2C if I2C
732 select HAVE_S3C2410_WATCHDOG if WATCHDOG
734 select NEED_MACH_GPIO_H
738 select S3C_GPIO_TRACK
740 select SAMSUNG_CLKSRC
741 select SAMSUNG_GPIOLIB_4BIT
742 select SAMSUNG_IRQ_VIC_TIMER
743 select SAMSUNG_WDT_RESET
744 select USB_ARCH_HAS_OHCI
746 Samsung S3C64XX series based systems
749 bool "Samsung S5P6440 S5P6450"
753 select GENERIC_CLOCKEVENTS
756 select HAVE_S3C2410_I2C if I2C
757 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 select HAVE_S3C_RTC if RTC_CLASS
759 select NEED_MACH_GPIO_H
760 select SAMSUNG_WDT_RESET
763 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
767 bool "Samsung S5PC100"
768 select ARCH_REQUIRE_GPIOLIB
772 select GENERIC_CLOCKEVENTS
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 select HAVE_S3C_RTC if RTC_CLASS
778 select NEED_MACH_GPIO_H
779 select SAMSUNG_WDT_RESET
782 Samsung S5PC100 series based systems
785 bool "Samsung S5PV210/S5PC110"
786 select ARCH_HAS_CPUFREQ
787 select ARCH_HAS_HOLES_MEMORYMODEL
788 select ARCH_SPARSEMEM_ENABLE
792 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
799 select NEED_MACH_MEMORY_H
802 Samsung S5PV210/S5PC110 series based systems
805 bool "Samsung EXYNOS"
806 select ARCH_HAS_CPUFREQ
807 select ARCH_HAS_HOLES_MEMORYMODEL
808 select ARCH_REQUIRE_GPIOLIB
809 select ARCH_SPARSEMEM_ENABLE
814 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select HAVE_S3C_RTC if RTC_CLASS
819 select NEED_MACH_MEMORY_H
823 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
827 select ARCH_USES_GETTIMEOFFSET
831 select NEED_MACH_MEMORY_H
836 Support for the StrongARM based Digital DNARD machine, also known
837 as "Shark" (<http://www.shark-linux.de/shark.html>).
841 select ARCH_HAS_HOLES_MEMORYMODEL
842 select ARCH_REQUIRE_GPIOLIB
844 select GENERIC_ALLOCATOR
845 select GENERIC_CLOCKEVENTS
846 select GENERIC_IRQ_CHIP
848 select NEED_MACH_GPIO_H
853 Support for TI's DaVinci platform.
858 select ARCH_HAS_CPUFREQ
859 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_REQUIRE_GPIOLIB
864 select GENERIC_CLOCKEVENTS
865 select GENERIC_IRQ_CHIP
869 select NEED_MACH_IO_H if PCCARD
870 select NEED_MACH_MEMORY_H
872 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
876 menu "Multiple platform selection"
877 depends on ARCH_MULTIPLATFORM
879 comment "CPU Core family selection"
881 config ARCH_MULTI_V4T
882 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
883 depends on !ARCH_MULTI_V6_V7
884 select ARCH_MULTI_V4_V5
885 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
886 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
887 CPU_ARM925T || CPU_ARM940T)
890 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
891 depends on !ARCH_MULTI_V6_V7
892 select ARCH_MULTI_V4_V5
893 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
894 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
895 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
897 config ARCH_MULTI_V4_V5
901 bool "ARMv6 based platforms (ARM11)"
902 select ARCH_MULTI_V6_V7
906 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
908 select ARCH_MULTI_V6_V7
911 config ARCH_MULTI_V6_V7
914 config ARCH_MULTI_CPU_AUTO
915 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
921 # This is sorted alphabetically by mach-* pathname. However, plat-*
922 # Kconfigs may be included either alphabetically (according to the
923 # plat- suffix) or along side the corresponding mach-* source.
925 source "arch/arm/mach-mvebu/Kconfig"
927 source "arch/arm/mach-at91/Kconfig"
929 source "arch/arm/mach-bcm/Kconfig"
931 source "arch/arm/mach-bcm2835/Kconfig"
933 source "arch/arm/mach-clps711x/Kconfig"
935 source "arch/arm/mach-cns3xxx/Kconfig"
937 source "arch/arm/mach-davinci/Kconfig"
939 source "arch/arm/mach-dove/Kconfig"
941 source "arch/arm/mach-ep93xx/Kconfig"
943 source "arch/arm/mach-footbridge/Kconfig"
945 source "arch/arm/mach-gemini/Kconfig"
947 source "arch/arm/mach-highbank/Kconfig"
949 source "arch/arm/mach-integrator/Kconfig"
951 source "arch/arm/mach-iop32x/Kconfig"
953 source "arch/arm/mach-iop33x/Kconfig"
955 source "arch/arm/mach-iop13xx/Kconfig"
957 source "arch/arm/mach-ixp4xx/Kconfig"
959 source "arch/arm/mach-keystone/Kconfig"
961 source "arch/arm/mach-kirkwood/Kconfig"
963 source "arch/arm/mach-ks8695/Kconfig"
965 source "arch/arm/mach-msm/Kconfig"
967 source "arch/arm/mach-mv78xx0/Kconfig"
969 source "arch/arm/mach-imx/Kconfig"
971 source "arch/arm/mach-mxs/Kconfig"
973 source "arch/arm/mach-netx/Kconfig"
975 source "arch/arm/mach-nomadik/Kconfig"
977 source "arch/arm/mach-nspire/Kconfig"
979 source "arch/arm/plat-omap/Kconfig"
981 source "arch/arm/mach-omap1/Kconfig"
983 source "arch/arm/mach-omap2/Kconfig"
985 source "arch/arm/mach-orion5x/Kconfig"
987 source "arch/arm/mach-picoxcell/Kconfig"
989 source "arch/arm/mach-pxa/Kconfig"
990 source "arch/arm/plat-pxa/Kconfig"
992 source "arch/arm/mach-mmp/Kconfig"
994 source "arch/arm/mach-realview/Kconfig"
996 source "arch/arm/mach-rockchip/Kconfig"
998 source "arch/arm/mach-sa1100/Kconfig"
1000 source "arch/arm/plat-samsung/Kconfig"
1002 source "arch/arm/mach-socfpga/Kconfig"
1004 source "arch/arm/mach-spear/Kconfig"
1006 source "arch/arm/mach-sti/Kconfig"
1008 source "arch/arm/mach-s3c24xx/Kconfig"
1011 source "arch/arm/mach-s3c64xx/Kconfig"
1014 source "arch/arm/mach-s5p64x0/Kconfig"
1016 source "arch/arm/mach-s5pc100/Kconfig"
1018 source "arch/arm/mach-s5pv210/Kconfig"
1020 source "arch/arm/mach-exynos/Kconfig"
1022 source "arch/arm/mach-shmobile/Kconfig"
1024 source "arch/arm/mach-sunxi/Kconfig"
1026 source "arch/arm/mach-prima2/Kconfig"
1028 source "arch/arm/mach-tegra/Kconfig"
1030 source "arch/arm/mach-u300/Kconfig"
1032 source "arch/arm/mach-ux500/Kconfig"
1034 source "arch/arm/mach-versatile/Kconfig"
1036 source "arch/arm/mach-vexpress/Kconfig"
1037 source "arch/arm/plat-versatile/Kconfig"
1039 source "arch/arm/mach-virt/Kconfig"
1041 source "arch/arm/mach-vt8500/Kconfig"
1043 source "arch/arm/mach-w90x900/Kconfig"
1045 source "arch/arm/mach-zynq/Kconfig"
1047 # Definitions to make life easier
1053 select GENERIC_CLOCKEVENTS
1059 select GENERIC_IRQ_CHIP
1062 config PLAT_ORION_LEGACY
1069 config PLAT_VERSATILE
1072 config ARM_TIMER_SP804
1075 select CLKSRC_OF if OF
1077 source arch/arm/mm/Kconfig
1081 default 16 if ARCH_EP93XX
1085 bool "Enable iWMMXt support" if !CPU_PJ4
1086 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1087 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1089 Enable support for iWMMXt context switching at run time if
1090 running on a CPU that supports it.
1094 depends on CPU_XSCALE
1097 config MULTI_IRQ_HANDLER
1100 Allow each machine to specify it's own IRQ handler at run time.
1103 source "arch/arm/Kconfig-nommu"
1106 config ARM_ERRATA_326103
1107 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1110 Executing a SWP instruction to read-only memory does not set bit 11
1111 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1112 treat the access as a read, preventing a COW from occurring and
1113 causing the faulting task to livelock.
1115 config ARM_ERRATA_411920
1116 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1117 depends on CPU_V6 || CPU_V6K
1119 Invalidation of the Instruction Cache operation can
1120 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1121 It does not affect the MPCore. This option enables the ARM Ltd.
1122 recommended workaround.
1124 config ARM_ERRATA_430973
1125 bool "ARM errata: Stale prediction on replaced interworking branch"
1128 This option enables the workaround for the 430973 Cortex-A8
1129 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1130 interworking branch is replaced with another code sequence at the
1131 same virtual address, whether due to self-modifying code or virtual
1132 to physical address re-mapping, Cortex-A8 does not recover from the
1133 stale interworking branch prediction. This results in Cortex-A8
1134 executing the new code sequence in the incorrect ARM or Thumb state.
1135 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1136 and also flushes the branch target cache at every context switch.
1137 Note that setting specific bits in the ACTLR register may not be
1138 available in non-secure mode.
1140 config ARM_ERRATA_458693
1141 bool "ARM errata: Processor deadlock when a false hazard is created"
1143 depends on !ARCH_MULTIPLATFORM
1145 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1146 erratum. For very specific sequences of memory operations, it is
1147 possible for a hazard condition intended for a cache line to instead
1148 be incorrectly associated with a different cache line. This false
1149 hazard might then cause a processor deadlock. The workaround enables
1150 the L1 caching of the NEON accesses and disables the PLD instruction
1151 in the ACTLR register. Note that setting specific bits in the ACTLR
1152 register may not be available in non-secure mode.
1154 config ARM_ERRATA_460075
1155 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1157 depends on !ARCH_MULTIPLATFORM
1159 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1160 erratum. Any asynchronous access to the L2 cache may encounter a
1161 situation in which recent store transactions to the L2 cache are lost
1162 and overwritten with stale memory contents from external memory. The
1163 workaround disables the write-allocate mode for the L2 cache via the
1164 ACTLR register. Note that setting specific bits in the ACTLR register
1165 may not be available in non-secure mode.
1167 config ARM_ERRATA_742230
1168 bool "ARM errata: DMB operation may be faulty"
1169 depends on CPU_V7 && SMP
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 742230 Cortex-A9
1173 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1174 between two write operations may not ensure the correct visibility
1175 ordering of the two writes. This workaround sets a specific bit in
1176 the diagnostic register of the Cortex-A9 which causes the DMB
1177 instruction to behave as a DSB, ensuring the correct behaviour of
1180 config ARM_ERRATA_742231
1181 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1182 depends on CPU_V7 && SMP
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 742231 Cortex-A9
1186 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1187 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1188 accessing some data located in the same cache line, may get corrupted
1189 data due to bad handling of the address hazard when the line gets
1190 replaced from one of the CPUs at the same time as another CPU is
1191 accessing it. This workaround sets specific bits in the diagnostic
1192 register of the Cortex-A9 which reduces the linefill issuing
1193 capabilities of the processor.
1195 config PL310_ERRATA_588369
1196 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1197 depends on CACHE_L2X0
1199 The PL310 L2 cache controller implements three types of Clean &
1200 Invalidate maintenance operations: by Physical Address
1201 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1202 They are architecturally defined to behave as the execution of a
1203 clean operation followed immediately by an invalidate operation,
1204 both performing to the same memory location. This functionality
1205 is not correctly implemented in PL310 as clean lines are not
1206 invalidated as a result of these operations.
1208 config ARM_ERRATA_643719
1209 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1210 depends on CPU_V7 && SMP
1212 This option enables the workaround for the 643719 Cortex-A9 (prior to
1213 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1214 register returns zero when it should return one. The workaround
1215 corrects this value, ensuring cache maintenance operations which use
1216 it behave as intended and avoiding data corruption.
1218 config ARM_ERRATA_720789
1219 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1222 This option enables the workaround for the 720789 Cortex-A9 (prior to
1223 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1224 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1225 As a consequence of this erratum, some TLB entries which should be
1226 invalidated are not, resulting in an incoherency in the system page
1227 tables. The workaround changes the TLB flushing routines to invalidate
1228 entries regardless of the ASID.
1230 config PL310_ERRATA_727915
1231 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1232 depends on CACHE_L2X0
1234 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1235 operation (offset 0x7FC). This operation runs in background so that
1236 PL310 can handle normal accesses while it is in progress. Under very
1237 rare circumstances, due to this erratum, write data can be lost when
1238 PL310 treats a cacheable write transaction during a Clean &
1239 Invalidate by Way operation.
1241 config ARM_ERRATA_743622
1242 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1244 depends on !ARCH_MULTIPLATFORM
1246 This option enables the workaround for the 743622 Cortex-A9
1247 (r2p*) erratum. Under very rare conditions, a faulty
1248 optimisation in the Cortex-A9 Store Buffer may lead to data
1249 corruption. This workaround sets a specific bit in the diagnostic
1250 register of the Cortex-A9 which disables the Store Buffer
1251 optimisation, preventing the defect from occurring. This has no
1252 visible impact on the overall performance or power consumption of the
1255 config ARM_ERRATA_751472
1256 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1258 depends on !ARCH_MULTIPLATFORM
1260 This option enables the workaround for the 751472 Cortex-A9 (prior
1261 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1262 completion of a following broadcasted operation if the second
1263 operation is received by a CPU before the ICIALLUIS has completed,
1264 potentially leading to corrupted entries in the cache or TLB.
1266 config PL310_ERRATA_753970
1267 bool "PL310 errata: cache sync operation may be faulty"
1268 depends on CACHE_PL310
1270 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1272 Under some condition the effect of cache sync operation on
1273 the store buffer still remains when the operation completes.
1274 This means that the store buffer is always asked to drain and
1275 this prevents it from merging any further writes. The workaround
1276 is to replace the normal offset of cache sync operation (0x730)
1277 by another offset targeting an unmapped PL310 register 0x740.
1278 This has the same effect as the cache sync operation: store buffer
1279 drain and waiting for all buffers empty.
1281 config ARM_ERRATA_754322
1282 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1285 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1286 r3p*) erratum. A speculative memory access may cause a page table walk
1287 which starts prior to an ASID switch but completes afterwards. This
1288 can populate the micro-TLB with a stale entry which may be hit with
1289 the new ASID. This workaround places two dsb instructions in the mm
1290 switching code so that no page table walks can cross the ASID switch.
1292 config ARM_ERRATA_754327
1293 bool "ARM errata: no automatic Store Buffer drain"
1294 depends on CPU_V7 && SMP
1296 This option enables the workaround for the 754327 Cortex-A9 (prior to
1297 r2p0) erratum. The Store Buffer does not have any automatic draining
1298 mechanism and therefore a livelock may occur if an external agent
1299 continuously polls a memory location waiting to observe an update.
1300 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1301 written polling loops from denying visibility of updates to memory.
1303 config ARM_ERRATA_364296
1304 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1307 This options enables the workaround for the 364296 ARM1136
1308 r0p2 erratum (possible cache data corruption with
1309 hit-under-miss enabled). It sets the undocumented bit 31 in
1310 the auxiliary control register and the FI bit in the control
1311 register, thus disabling hit-under-miss without putting the
1312 processor into full low interrupt latency mode. ARM11MPCore
1315 config ARM_ERRATA_764369
1316 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1317 depends on CPU_V7 && SMP
1319 This option enables the workaround for erratum 764369
1320 affecting Cortex-A9 MPCore with two or more processors (all
1321 current revisions). Under certain timing circumstances, a data
1322 cache line maintenance operation by MVA targeting an Inner
1323 Shareable memory region may fail to proceed up to either the
1324 Point of Coherency or to the Point of Unification of the
1325 system. This workaround adds a DSB instruction before the
1326 relevant cache maintenance functions and sets a specific bit
1327 in the diagnostic control register of the SCU.
1329 config PL310_ERRATA_769419
1330 bool "PL310 errata: no automatic Store Buffer drain"
1331 depends on CACHE_L2X0
1333 On revisions of the PL310 prior to r3p2, the Store Buffer does
1334 not automatically drain. This can cause normal, non-cacheable
1335 writes to be retained when the memory system is idle, leading
1336 to suboptimal I/O performance for drivers using coherent DMA.
1337 This option adds a write barrier to the cpu_idle loop so that,
1338 on systems with an outer cache, the store buffer is drained
1341 config ARM_ERRATA_775420
1342 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1345 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1346 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1347 operation aborts with MMU exception, it might cause the processor
1348 to deadlock. This workaround puts DSB before executing ISB if
1349 an abort may occur on cache maintenance.
1351 config ARM_ERRATA_798181
1352 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1353 depends on CPU_V7 && SMP
1355 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1356 adequately shooting down all use of the old entries. This
1357 option enables the Linux kernel workaround for this erratum
1358 which sends an IPI to the CPUs that are running the same ASID
1359 as the one being invalidated.
1363 source "arch/arm/common/Kconfig"
1373 Find out whether you have ISA slots on your motherboard. ISA is the
1374 name of a bus system, i.e. the way the CPU talks to the other stuff
1375 inside your box. Other bus systems are PCI, EISA, MicroChannel
1376 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1377 newer boards don't support it. If you have ISA, say Y, otherwise N.
1379 # Select ISA DMA controller support
1384 # Select ISA DMA interface
1389 bool "PCI support" if MIGHT_HAVE_PCI
1391 Find out whether you have a PCI motherboard. PCI is the name of a
1392 bus system, i.e. the way the CPU talks to the other stuff inside
1393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1394 VESA. If you have PCI, say Y, otherwise N.
1400 config PCI_NANOENGINE
1401 bool "BSE nanoEngine PCI support"
1402 depends on SA1100_NANOENGINE
1404 Enable PCI on the BSE nanoEngine board.
1409 # Select the host bridge type
1410 config PCI_HOST_VIA82C505
1412 depends on PCI && ARCH_SHARK
1415 config PCI_HOST_ITE8152
1417 depends on PCI && MACH_ARMCORE
1421 source "drivers/pci/Kconfig"
1422 source "drivers/pci/pcie/Kconfig"
1424 source "drivers/pcmcia/Kconfig"
1428 menu "Kernel Features"
1433 This option should be selected by machines which have an SMP-
1436 The only effect of this option is to make the SMP-related
1437 options available to the user for configuration.
1440 bool "Symmetric Multi-Processing"
1441 depends on CPU_V6K || CPU_V7
1442 depends on GENERIC_CLOCKEVENTS
1444 depends on MMU || ARM_MPU
1445 select USE_GENERIC_SMP_HELPERS
1447 This enables support for systems with more than one CPU. If you have
1448 a system with only one CPU, like most personal computers, say N. If
1449 you have a system with more than one CPU, say Y.
1451 If you say N here, the kernel will run on single and multiprocessor
1452 machines, but will use only one CPU of a multiprocessor machine. If
1453 you say Y here, the kernel will run on many, but not all, single
1454 processor machines. On a single processor machine, the kernel will
1455 run faster if you say N here.
1457 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1458 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1459 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1461 If you don't know what to do here, say N.
1464 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1465 depends on SMP && !XIP_KERNEL && MMU
1468 SMP kernels contain instructions which fail on non-SMP processors.
1469 Enabling this option allows the kernel to modify itself to make
1470 these instructions safe. Disabling it allows about 1K of space
1473 If you don't know what to do here, say Y.
1475 config ARM_CPU_TOPOLOGY
1476 bool "Support cpu topology definition"
1477 depends on SMP && CPU_V7
1480 Support ARM cpu topology definition. The MPIDR register defines
1481 affinity between processors which is then used to describe the cpu
1482 topology of an ARM System.
1485 bool "Multi-core scheduler support"
1486 depends on ARM_CPU_TOPOLOGY
1488 Multi-core scheduler support improves the CPU scheduler's decision
1489 making when dealing with multi-core CPU chips at a cost of slightly
1490 increased overhead in some places. If unsure say N here.
1493 bool "SMT scheduler support"
1494 depends on ARM_CPU_TOPOLOGY
1496 Improves the CPU scheduler's decision making when dealing with
1497 MultiThreading at a cost of slightly increased overhead in some
1498 places. If unsure say N here.
1503 This option enables support for the ARM system coherency unit
1505 config HAVE_ARM_ARCH_TIMER
1506 bool "Architected timer support"
1508 select ARM_ARCH_TIMER
1510 This option enables support for the ARM architected timer
1515 select CLKSRC_OF if OF
1517 This options enables support for the ARM timer and watchdog unit
1520 bool "Multi-Cluster Power Management"
1521 depends on CPU_V7 && SMP
1523 This option provides the common power management infrastructure
1524 for (multi-)cluster based systems, such as big.LITTLE based
1528 prompt "Memory split"
1531 Select the desired split between kernel and user memory.
1533 If you are not absolutely sure what you are doing, leave this
1537 bool "3G/1G user/kernel split"
1539 bool "2G/2G user/kernel split"
1541 bool "1G/3G user/kernel split"
1546 default 0x40000000 if VMSPLIT_1G
1547 default 0x80000000 if VMSPLIT_2G
1551 int "Maximum number of CPUs (2-32)"
1557 bool "Support for hot-pluggable CPUs"
1560 Say Y here to experiment with turning CPUs off and on. CPUs
1561 can be controlled through /sys/devices/system/cpu.
1564 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1567 Say Y here if you want Linux to communicate with system firmware
1568 implementing the PSCI specification for CPU-centric power
1569 management operations described in ARM document number ARM DEN
1570 0022A ("Power State Coordination Interface System Software on
1574 bool "Use local timer interrupts"
1578 Enable support for local timers on SMP platforms, rather then the
1579 legacy IPI broadcast method. Local timers allows the system
1580 accounting to be spread across the timer interval, preventing a
1581 "thundering herd" at every timer tick.
1583 # The GPIO number here must be sorted by descending number. In case of
1584 # a multiplatform kernel, we just want the highest value required by the
1585 # selected platforms.
1588 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1589 default 512 if SOC_OMAP5
1590 default 512 if ARCH_KEYSTONE
1591 default 392 if ARCH_U8500
1592 default 352 if ARCH_VT8500
1593 default 288 if ARCH_SUNXI
1594 default 264 if MACH_H4700
1597 Maximum number of GPIOs in the system.
1599 If unsure, leave the default value.
1601 source kernel/Kconfig.preempt
1605 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1606 ARCH_S5PV210 || ARCH_EXYNOS4
1607 default AT91_TIMER_HZ if ARCH_AT91
1608 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1612 def_bool HIGH_RES_TIMERS
1614 config THUMB2_KERNEL
1615 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1616 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1617 default y if CPU_THUMBONLY
1619 select ARM_ASM_UNIFIED
1622 By enabling this option, the kernel will be compiled in
1623 Thumb-2 mode. A compiler/assembler that understand the unified
1624 ARM-Thumb syntax is needed.
1628 config THUMB2_AVOID_R_ARM_THM_JUMP11
1629 bool "Work around buggy Thumb-2 short branch relocations in gas"
1630 depends on THUMB2_KERNEL && MODULES
1633 Various binutils versions can resolve Thumb-2 branches to
1634 locally-defined, preemptible global symbols as short-range "b.n"
1635 branch instructions.
1637 This is a problem, because there's no guarantee the final
1638 destination of the symbol, or any candidate locations for a
1639 trampoline, are within range of the branch. For this reason, the
1640 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1641 relocation in modules at all, and it makes little sense to add
1644 The symptom is that the kernel fails with an "unsupported
1645 relocation" error when loading some modules.
1647 Until fixed tools are available, passing
1648 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1649 code which hits this problem, at the cost of a bit of extra runtime
1650 stack usage in some cases.
1652 The problem is described in more detail at:
1653 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1655 Only Thumb-2 kernels are affected.
1657 Unless you are sure your tools don't have this problem, say Y.
1659 config ARM_ASM_UNIFIED
1663 bool "Use the ARM EABI to compile the kernel"
1665 This option allows for the kernel to be compiled using the latest
1666 ARM ABI (aka EABI). This is only useful if you are using a user
1667 space environment that is also compiled with EABI.
1669 Since there are major incompatibilities between the legacy ABI and
1670 EABI, especially with regard to structure member alignment, this
1671 option also changes the kernel syscall calling convention to
1672 disambiguate both ABIs and allow for backward compatibility support
1673 (selected with CONFIG_OABI_COMPAT).
1675 To use this you need GCC version 4.0.0 or later.
1678 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1679 depends on AEABI && !THUMB2_KERNEL
1682 This option preserves the old syscall interface along with the
1683 new (ARM EABI) one. It also provides a compatibility layer to
1684 intercept syscalls that have structure arguments which layout
1685 in memory differs between the legacy ABI and the new ARM EABI
1686 (only for non "thumb" binaries). This option adds a tiny
1687 overhead to all syscalls and produces a slightly larger kernel.
1688 If you know you'll be using only pure EABI user space then you
1689 can say N here. If this option is not selected and you attempt
1690 to execute a legacy ABI binary then the result will be
1691 UNPREDICTABLE (in fact it can be predicted that it won't work
1692 at all). If in doubt say Y.
1694 config ARCH_HAS_HOLES_MEMORYMODEL
1697 config ARCH_SPARSEMEM_ENABLE
1700 config ARCH_SPARSEMEM_DEFAULT
1701 def_bool ARCH_SPARSEMEM_ENABLE
1703 config ARCH_SELECT_MEMORY_MODEL
1704 def_bool ARCH_SPARSEMEM_ENABLE
1706 config HAVE_ARCH_PFN_VALID
1707 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1710 bool "High Memory Support"
1713 The address space of ARM processors is only 4 Gigabytes large
1714 and it has to accommodate user address space, kernel address
1715 space as well as some memory mapped IO. That means that, if you
1716 have a large amount of physical memory and/or IO, not all of the
1717 memory can be "permanently mapped" by the kernel. The physical
1718 memory that is not permanently mapped is called "high memory".
1720 Depending on the selected kernel/user memory split, minimum
1721 vmalloc space and actual amount of RAM, you may not need this
1722 option which should result in a slightly faster kernel.
1727 bool "Allocate 2nd-level pagetables from highmem"
1730 config HW_PERF_EVENTS
1731 bool "Enable hardware performance counter support for perf events"
1732 depends on PERF_EVENTS
1735 Enable hardware performance counter support for perf events. If
1736 disabled, perf events will use software events only.
1738 config SYS_SUPPORTS_HUGETLBFS
1742 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1748 config FORCE_MAX_ZONEORDER
1749 int "Maximum zone order" if ARCH_SHMOBILE
1750 range 11 64 if ARCH_SHMOBILE
1751 default "12" if SOC_AM33XX
1752 default "9" if SA1111
1755 The kernel memory allocator divides physically contiguous memory
1756 blocks into "zones", where each zone is a power of two number of
1757 pages. This option selects the largest power of two that the kernel
1758 keeps in the memory allocator. If you need to allocate very large
1759 blocks of physically contiguous memory, then you may need to
1760 increase this value.
1762 This config option is actually maximum order plus one. For example,
1763 a value of 11 means that the largest free memory block is 2^10 pages.
1765 config ALIGNMENT_TRAP
1767 depends on CPU_CP15_MMU
1768 default y if !ARCH_EBSA110
1769 select HAVE_PROC_CPU if PROC_FS
1771 ARM processors cannot fetch/store information which is not
1772 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1773 address divisible by 4. On 32-bit ARM processors, these non-aligned
1774 fetch/store instructions will be emulated in software if you say
1775 here, which has a severe performance impact. This is necessary for
1776 correct operation of some network protocols. With an IP-only
1777 configuration it is safe to say N, otherwise say Y.
1779 config UACCESS_WITH_MEMCPY
1780 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1782 default y if CPU_FEROCEON
1784 Implement faster copy_to_user and clear_user methods for CPU
1785 cores where a 8-word STM instruction give significantly higher
1786 memory write throughput than a sequence of individual 32bit stores.
1788 A possible side effect is a slight increase in scheduling latency
1789 between threads sharing the same address space if they invoke
1790 such copy operations with large buffers.
1792 However, if the CPU data cache is using a write-allocate mode,
1793 this option is unlikely to provide any performance gain.
1797 prompt "Enable seccomp to safely compute untrusted bytecode"
1799 This kernel feature is useful for number crunching applications
1800 that may need to compute untrusted bytecode during their
1801 execution. By using pipes or other transports made available to
1802 the process as file descriptors supporting the read/write
1803 syscalls, it's possible to isolate those applications in
1804 their own address space using seccomp. Once seccomp is
1805 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1806 and the task is only allowed to execute a few safe syscalls
1807 defined by each seccomp mode.
1809 config CC_STACKPROTECTOR
1810 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1812 This option turns on the -fstack-protector GCC feature. This
1813 feature puts, at the beginning of functions, a canary value on
1814 the stack just before the return address, and validates
1815 the value just before actually returning. Stack based buffer
1816 overflows (that need to overwrite this return address) now also
1817 overwrite the canary, which gets detected and the attack is then
1818 neutralized via a kernel panic.
1819 This feature requires gcc version 4.2 or above.
1826 bool "Xen guest support on ARM (EXPERIMENTAL)"
1827 depends on ARM && AEABI && OF
1828 depends on CPU_V7 && !CPU_V6
1829 depends on !GENERIC_ATOMIC64
1832 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1839 bool "Flattened Device Tree support"
1842 select OF_EARLY_FLATTREE
1844 Include support for flattened device tree machine descriptions.
1847 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1850 This is the traditional way of passing data to the kernel at boot
1851 time. If you are solely relying on the flattened device tree (or
1852 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1853 to remove ATAGS support from your kernel binary. If unsure,
1856 config DEPRECATED_PARAM_STRUCT
1857 bool "Provide old way to pass kernel parameters"
1860 This was deprecated in 2001 and announced to live on for 5 years.
1861 Some old boot loaders still use this way.
1863 # Compressed boot loader in ROM. Yes, we really want to ask about
1864 # TEXT and BSS so we preserve their values in the config files.
1865 config ZBOOT_ROM_TEXT
1866 hex "Compressed ROM boot loader base address"
1869 The physical address at which the ROM-able zImage is to be
1870 placed in the target. Platforms which normally make use of
1871 ROM-able zImage formats normally set this to a suitable
1872 value in their defconfig file.
1874 If ZBOOT_ROM is not enabled, this has no effect.
1876 config ZBOOT_ROM_BSS
1877 hex "Compressed ROM boot loader BSS address"
1880 The base address of an area of read/write memory in the target
1881 for the ROM-able zImage which must be available while the
1882 decompressor is running. It must be large enough to hold the
1883 entire decompressed kernel plus an additional 128 KiB.
1884 Platforms which normally make use of ROM-able zImage formats
1885 normally set this to a suitable value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1890 bool "Compressed boot loader in ROM/flash"
1891 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1893 Say Y here if you intend to execute your compressed kernel image
1894 (zImage) directly from ROM or flash. If unsure, say N.
1897 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1898 depends on ZBOOT_ROM && ARCH_SH7372
1899 default ZBOOT_ROM_NONE
1901 Include experimental SD/MMC loading code in the ROM-able zImage.
1902 With this enabled it is possible to write the ROM-able zImage
1903 kernel image to an MMC or SD card and boot the kernel straight
1904 from the reset vector. At reset the processor Mask ROM will load
1905 the first part of the ROM-able zImage which in turn loads the
1906 rest the kernel image to RAM.
1908 config ZBOOT_ROM_NONE
1909 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1911 Do not load image from SD or MMC
1913 config ZBOOT_ROM_MMCIF
1914 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1916 Load image from MMCIF hardware block.
1918 config ZBOOT_ROM_SH_MOBILE_SDHI
1919 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1921 Load image from SDHI hardware block
1925 config ARM_APPENDED_DTB
1926 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1927 depends on OF && !ZBOOT_ROM
1929 With this option, the boot code will look for a device tree binary
1930 (DTB) appended to zImage
1931 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1933 This is meant as a backward compatibility convenience for those
1934 systems with a bootloader that can't be upgraded to accommodate
1935 the documented boot protocol using a device tree.
1937 Beware that there is very little in terms of protection against
1938 this option being confused by leftover garbage in memory that might
1939 look like a DTB header after a reboot if no actual DTB is appended
1940 to zImage. Do not leave this option active in a production kernel
1941 if you don't intend to always append a DTB. Proper passing of the
1942 location into r2 of a bootloader provided DTB is always preferable
1945 config ARM_ATAG_DTB_COMPAT
1946 bool "Supplement the appended DTB with traditional ATAG information"
1947 depends on ARM_APPENDED_DTB
1949 Some old bootloaders can't be updated to a DTB capable one, yet
1950 they provide ATAGs with memory configuration, the ramdisk address,
1951 the kernel cmdline string, etc. Such information is dynamically
1952 provided by the bootloader and can't always be stored in a static
1953 DTB. To allow a device tree enabled kernel to be used with such
1954 bootloaders, this option allows zImage to extract the information
1955 from the ATAG list and store it at run time into the appended DTB.
1958 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1959 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1961 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1962 bool "Use bootloader kernel arguments if available"
1964 Uses the command-line options passed by the boot loader instead of
1965 the device tree bootargs property. If the boot loader doesn't provide
1966 any, the device tree bootargs property will be used.
1968 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1969 bool "Extend with bootloader kernel arguments"
1971 The command-line arguments provided by the boot loader will be
1972 appended to the the device tree bootargs property.
1977 string "Default kernel command string"
1980 On some architectures (EBSA110 and CATS), there is currently no way
1981 for the boot loader to pass arguments to the kernel. For these
1982 architectures, you should supply some command-line options at build
1983 time by entering them here. As a minimum, you should specify the
1984 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1987 prompt "Kernel command line type" if CMDLINE != ""
1988 default CMDLINE_FROM_BOOTLOADER
1991 config CMDLINE_FROM_BOOTLOADER
1992 bool "Use bootloader kernel arguments if available"
1994 Uses the command-line options passed by the boot loader. If
1995 the boot loader doesn't provide any, the default kernel command
1996 string provided in CMDLINE will be used.
1998 config CMDLINE_EXTEND
1999 bool "Extend bootloader kernel arguments"
2001 The command-line arguments provided by the boot loader will be
2002 appended to the default kernel command string.
2004 config CMDLINE_FORCE
2005 bool "Always use the default kernel command string"
2007 Always use the default kernel command string, even if the boot
2008 loader passes other arguments to the kernel.
2009 This is useful if you cannot or don't want to change the
2010 command-line options your boot loader passes to the kernel.
2014 bool "Kernel Execute-In-Place from ROM"
2015 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2017 Execute-In-Place allows the kernel to run from non-volatile storage
2018 directly addressable by the CPU, such as NOR flash. This saves RAM
2019 space since the text section of the kernel is not loaded from flash
2020 to RAM. Read-write sections, such as the data section and stack,
2021 are still copied to RAM. The XIP kernel is not compressed since
2022 it has to run directly from flash, so it will take more space to
2023 store it. The flash address used to link the kernel object files,
2024 and for storing it, is configuration dependent. Therefore, if you
2025 say Y here, you must know the proper physical address where to
2026 store the kernel image depending on your own flash memory usage.
2028 Also note that the make target becomes "make xipImage" rather than
2029 "make zImage" or "make Image". The final kernel binary to put in
2030 ROM memory will be arch/arm/boot/xipImage.
2034 config XIP_PHYS_ADDR
2035 hex "XIP Kernel Physical Location"
2036 depends on XIP_KERNEL
2037 default "0x00080000"
2039 This is the physical address in your flash memory the kernel will
2040 be linked for and stored to. This address is dependent on your
2044 bool "Kexec system call (EXPERIMENTAL)"
2045 depends on (!SMP || PM_SLEEP_SMP)
2047 kexec is a system call that implements the ability to shutdown your
2048 current kernel, and to start another kernel. It is like a reboot
2049 but it is independent of the system firmware. And like a reboot
2050 you can start any kernel with it, not just Linux.
2052 It is an ongoing process to be certain the hardware in a machine
2053 is properly shutdown, so do not be surprised if this code does not
2054 initially work for you. It may help to enable device hotplugging
2058 bool "Export atags in procfs"
2059 depends on ATAGS && KEXEC
2062 Should the atags used to boot the kernel be exported in an "atags"
2063 file in procfs. Useful with kexec.
2066 bool "Build kdump crash kernel (EXPERIMENTAL)"
2068 Generate crash dump after being started by kexec. This should
2069 be normally only set in special crash dump kernels which are
2070 loaded in the main kernel with kexec-tools into a specially
2071 reserved region and then later executed after a crash by
2072 kdump/kexec. The crash dump kernel must be compiled to a
2073 memory address not used by the main kernel
2075 For more details see Documentation/kdump/kdump.txt
2077 config AUTO_ZRELADDR
2078 bool "Auto calculation of the decompressed kernel image address"
2079 depends on !ZBOOT_ROM
2081 ZRELADDR is the physical address where the decompressed kernel
2082 image will be placed. If AUTO_ZRELADDR is selected, the address
2083 will be determined at run-time by masking the current IP with
2084 0xf8000000. This assumes the zImage being placed in the first 128MB
2085 from start of memory.
2089 menu "CPU Power Management"
2092 source "drivers/cpufreq/Kconfig"
2095 source "drivers/cpuidle/Kconfig"
2099 menu "Floating point emulation"
2101 comment "At least one emulation must be selected"
2104 bool "NWFPE math emulation"
2105 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2107 Say Y to include the NWFPE floating point emulator in the kernel.
2108 This is necessary to run most binaries. Linux does not currently
2109 support floating point hardware so you need to say Y here even if
2110 your machine has an FPA or floating point co-processor podule.
2112 You may say N here if you are going to load the Acorn FPEmulator
2113 early in the bootup.
2116 bool "Support extended precision"
2117 depends on FPE_NWFPE
2119 Say Y to include 80-bit support in the kernel floating-point
2120 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2121 Note that gcc does not generate 80-bit operations by default,
2122 so in most cases this option only enlarges the size of the
2123 floating point emulator without any good reason.
2125 You almost surely want to say N here.
2128 bool "FastFPE math emulation (EXPERIMENTAL)"
2129 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2131 Say Y here to include the FAST floating point emulator in the kernel.
2132 This is an experimental much faster emulator which now also has full
2133 precision for the mantissa. It does not support any exceptions.
2134 It is very simple, and approximately 3-6 times faster than NWFPE.
2136 It should be sufficient for most programs. It may be not suitable
2137 for scientific calculations, but you have to check this for yourself.
2138 If you do not feel you need a faster FP emulation you should better
2142 bool "VFP-format floating point maths"
2143 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2145 Say Y to include VFP support code in the kernel. This is needed
2146 if your hardware includes a VFP unit.
2148 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2149 release notes and additional status information.
2151 Say N if your target does not have VFP hardware.
2159 bool "Advanced SIMD (NEON) Extension support"
2160 depends on VFPv3 && CPU_V7
2162 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2167 menu "Userspace binary formats"
2169 source "fs/Kconfig.binfmt"
2172 tristate "RISC OS personality"
2175 Say Y here to include the kernel code necessary if you want to run
2176 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2177 experimental; if this sounds frightening, say N and sleep in peace.
2178 You can also say M here to compile this support as a module (which
2179 will be called arthur).
2183 menu "Power management options"
2185 source "kernel/power/Kconfig"
2187 config ARCH_SUSPEND_POSSIBLE
2188 depends on !ARCH_S5PC100
2189 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2190 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2193 config ARM_CPU_SUSPEND
2198 source "net/Kconfig"
2200 source "drivers/Kconfig"
2204 source "arch/arm/Kconfig.debug"
2206 source "security/Kconfig"
2208 source "crypto/Kconfig"
2210 source "lib/Kconfig"
2212 source "arch/arm/kvm/Kconfig"