arch/arm/boot/dts/armada-370.dtsi

   1 /*
   2  * Device Tree Include file for Marvell Armada 370 family SoC
   3  *
   4  * Copyright (C) 2012 Marvell
   5  *
   6  * Lior Amsalem <alior@marvell.com>
   7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   9  *
  10  * This file is dual-licensed: you can use it either under the terms
  11  * of the GPL or the X11 license, at your option. Note that this dual
  12  * licensing only applies to this file, and not this project as a
  13  * whole.
  14  *
  15  *  a) This file is free software; you can redistribute it and/or
  16  *     modify it under the terms of the GNU General Public License as
  17  *     published by the Free Software Foundation; either version 2 of the
  18  *     License, or (at your option) any later version.
  19  *
  20  *     This file is distributed in the hope that it will be useful
  21  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *     GNU General Public License for more details.
  24  *
  25  * Or, alternatively
  26  *
  27  *  b) Permission is hereby granted, free of charge, to any person
  28  *     obtaining a copy of this software and associated documentation
  29  *     files (the "Software"), to deal in the Software without
  30  *     restriction, including without limitation the rights to use
  31  *     copy, modify, merge, publish, distribute, sublicense, and/or
  32  *     sell copies of the Software, and to permit persons to whom the
  33  *     Software is furnished to do so, subject to the following
  34  *     conditions:
  35  *
  36  *     The above copyright notice and this permission notice shall be
  37  *     included in all copies or substantial portions of the Software.
  38  *
  39  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
  40  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  41  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  42  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  43  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
  44  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  45  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  46  *     OTHER DEALINGS IN THE SOFTWARE.
  47  *
  48  * Contains definitions specific to the Armada 370 SoC that are not
  49  * common to all Armada SoCs.
  50  */
  51
  52 #include "armada-370-xp.dtsi"
  53 /include/ "skeleton.dtsi"
  54
  55 / {
  56         model = "Marvell Armada 370 family SoC";
  57         compatible = "marvell,armada370", "marvell,armada-370-xp";
  58
  59         aliases {
  60                 gpio0 = &gpio0;
  61                 gpio1 = &gpio1;
  62                 gpio2 = &gpio2;
  63         };
  64
  65         soc {
  66                 compatible = "marvell,armada370-mbus", "simple-bus";
  67
  68                 bootrom {
  69                         compatible = "marvell,bootrom";
  70                         reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
  71                 };
  72
  73                 pciec: pcie-controller {
  74                         compatible = "marvell,armada-370-pcie";
  75                         status = "disabled";
  76                         device_type = "pci";
  77
  78                         #address-cells = <3>;
  79                         #size-cells = <2>;
  80
  81                         msi-parent = <&mpic>;
  82                         bus-range = <0x00 0xff>;
  83
  84                         ranges =
  85                                <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
  86                                 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
  87                                 0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */
  88                                 0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */
  89                                 0x82000000 0x2 0     MBUS_ID(0x08, 0xe8) 0       1 0 /* Port 1.0 MEM */
  90                                 0x81000000 0x2 0     MBUS_ID(0x08, 0xe0) 0       1 0 /* Port 1.0 IO  */>;
  91
  92                         pcie0: pcie@1,0 {
  93                                 device_type = "pci";
  94                                 assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
  95                                 reg = <0x0800 0 0 0 0>;
  96                                 #address-cells = <3>;
  97                                 #size-cells = <2>;
  98                                 #interrupt-cells = <1>;
  99                                 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 100                                           0x81000000 0 0 0x81000000 0x1 0 1 0>;
 101                                 interrupt-map-mask = <0 0 0 0>;
 102                                 interrupt-map = <0 0 0 0 &mpic 58>;
 103                                 marvell,pcie-port = <0>;
 104                                 marvell,pcie-lane = <0>;
 105                                 clocks = <&gateclk 5>;
 106                                 status = "disabled";
 107                         };
 108
 109                         pcie2: pcie@2,0 {
 110                                 device_type = "pci";
 111                                 assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 112                                 reg = <0x1000 0 0 0 0>;
 113                                 #address-cells = <3>;
 114                                 #size-cells = <2>;
 115                                 #interrupt-cells = <1>;
 116                                 ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 117                                           0x81000000 0 0 0x81000000 0x2 0 1 0>;
 118                                 interrupt-map-mask = <0 0 0 0>;
 119                                 interrupt-map = <0 0 0 0 &mpic 62>;
 120                                 marvell,pcie-port = <1>;
 121                                 marvell,pcie-lane = <0>;
 122                                 clocks = <&gateclk 9>;
 123                                 status = "disabled";
 124                         };
 125                 };
 126
 127                 internal-regs {
 128                         L2: l2-cache {
 129                                 compatible = "marvell,aurora-outer-cache";
 130                                 reg = <0x08000 0x1000>;
 131                                 cache-id-part = <0x100>;
 132                                 cache-level = <2>;
 133                                 cache-unified;
 134                                 wt-override;
 135                         };
 136
 137                         gpio0: gpio@18100 {
 138                                 compatible = "marvell,orion-gpio";
 139                                 reg = <0x18100 0x40>;
 140                                 ngpios = <32>;
 141                                 gpio-controller;
 142                                 #gpio-cells = <2>;
 143                                 interrupt-controller;
 144                                 #interrupt-cells = <2>;
 145                                 interrupts = <82>, <83>, <84>, <85>;
 146                         };
 147
 148                         gpio1: gpio@18140 {
 149                                 compatible = "marvell,orion-gpio";
 150                                 reg = <0x18140 0x40>;
 151                                 ngpios = <32>;
 152                                 gpio-controller;
 153                                 #gpio-cells = <2>;
 154                                 interrupt-controller;
 155                                 #interrupt-cells = <2>;
 156                                 interrupts = <87>, <88>, <89>, <90>;
 157                         };
 158
 159                         gpio2: gpio@18180 {
 160                                 compatible = "marvell,orion-gpio";
 161                                 reg = <0x18180 0x40>;
 162                                 ngpios = <2>;
 163                                 gpio-controller;
 164                                 #gpio-cells = <2>;
 165                                 interrupt-controller;
 166                                 #interrupt-cells = <2>;
 167                                 interrupts = <91>;
 168                         };
 169
 170
 171                         systemc: system-controller@18200 {
 172                                 compatible = "marvell,armada-370-xp-system-controller";
 173                                 reg = <0x18200 0x100>;
 174                         };
 175
 176                         gateclk: clock-gating-control@18220 {
 177                                 compatible = "marvell,armada-370-gating-clock";
 178                                 reg = <0x18220 0x4>;
 179                                 clocks = <&coreclk 0>;
 180                                 #clock-cells = <1>;
 181                         };
 182
 183                         coreclk: mvebu-sar@18230 {
 184                                 compatible = "marvell,armada-370-core-clock";
 185                                 reg = <0x18230 0x08>;
 186                                 #clock-cells = <1>;
 187                         };
 188
 189                         thermal: thermal@18300 {
 190                                 compatible = "marvell,armada370-thermal";
 191                                 reg = <0x18300 0x4
 192                                         0x18304 0x4>;
 193                                 status = "okay";
 194                         };
 195
 196                         sscg: sscg@18330 {
 197                                 reg = <0x18330 0x4>;
 198                         };
 199
 200                         cpuconf: cpu-config@21000 {
 201                                 compatible = "marvell,armada-370-cpu-config";
 202                                 reg = <0x21000 0x8>;
 203                         };
 204
 205                         audio_controller: audio-controller@30000 {
 206                                 #sound-dai-cells = <1>;
 207                                 compatible = "marvell,armada370-audio";
 208                                 reg = <0x30000 0x4000>;
 209                                 interrupts = <93>;
 210                                 clocks = <&gateclk 0>;
 211                                 clock-names = "internal";
 212                                 status = "disabled";
 213                         };
 214
 215                         xor0: xor@60800 {
 216                                 compatible = "marvell,orion-xor";
 217                                 reg = <0x60800 0x100
 218                                        0x60A00 0x100>;
 219                                 status = "okay";
 220
 221                                 xor00 {
 222                                         interrupts = <51>;
 223                                         dmacap,memcpy;
 224                                         dmacap,xor;
 225                                 };
 226                                 xor01 {
 227                                         interrupts = <52>;
 228                                         dmacap,memcpy;
 229                                         dmacap,xor;
 230                                         dmacap,memset;
 231                                 };
 232                         };
 233
 234                         xor1: xor@60900 {
 235                                 compatible = "marvell,orion-xor";
 236                                 reg = <0x60900 0x100
 237                                        0x60b00 0x100>;
 238                                 status = "okay";
 239
 240                                 xor10 {
 241                                         interrupts = <94>;
 242                                         dmacap,memcpy;
 243                                         dmacap,xor;
 244                                 };
 245                                 xor11 {
 246                                         interrupts = <95>;
 247                                         dmacap,memcpy;
 248                                         dmacap,xor;
 249                                         dmacap,memset;
 250                                 };
 251                         };
 252
 253                         cesa: crypto@90000 {
 254                                 compatible = "marvell,armada-370-crypto";
 255                                 reg = <0x90000 0x10000>;
 256                                 reg-names = "regs";
 257                                 interrupts = <48>;
 258                                 clocks = <&gateclk 23>;
 259                                 clock-names = "cesa0";
 260                                 marvell,crypto-srams = <&crypto_sram>;
 261                                 marvell,crypto-sram-size = <0x7e0>;
 262                         };
 263                 };
 264
 265                 crypto_sram: sa-sram {
 266                         compatible = "mmio-sram";
 267                         reg = <MBUS_ID(0x09, 0x01) 0 0x800>;
 268                         reg-names = "sram";
 269                         clocks = <&gateclk 23>;
 270                         #address-cells = <1>;
 271                         #size-cells = <1>;
 272                         ranges = <0 MBUS_ID(0x09, 0x01) 0 0x800>;
 273
 274                         /*
 275                          * The Armada 370 has an erratum preventing the use of
 276                          * the standard workflow for CPU idle support (relying
 277                          * on the BootROM code to enter/exit idle state).
 278                          * Reserve some amount of the crypto SRAM to put the
 279                          * cpuidle workaround.
 280                          */
 281                         idle-sram@0 {
 282                                 reg = <0x0 0x20>;
 283                         };
 284                 };
 285         };
 286 };
 287
 288 /*
 289  * Default UART pinctrl setting without RTS/CTS, can be overwritten on
 290  * board level if a different configuration is used.
 291  */
 292
 293 &uart0 {
 294         pinctrl-0 = <&uart0_pins>;
 295         pinctrl-names = "default";
 296 };
 297
 298 &uart1 {
 299         pinctrl-0 = <&uart1_pins>;
 300         pinctrl-names = "default";
 301 };
 302
 303 &i2c0 {
 304         reg = <0x11000 0x20>;
 305 };
 306
 307 &i2c1 {
 308         reg = <0x11100 0x20>;
 309 };
 310
 311 &mpic {
 312         reg = <0x20a00 0x1d0>, <0x21870 0x58>;
 313 };
 314
 315 &timer {
 316         compatible = "marvell,armada-370-timer";
 317         clocks = <&coreclk 2>;
 318 };
 319
 320 &watchdog {
 321         compatible = "marvell,armada-370-wdt";
 322         clocks = <&coreclk 2>;
 323 };
 324
 325 &usb0 {
 326         clocks = <&coreclk 0>;
 327 };
 328
 329 &usb1 {
 330         clocks = <&coreclk 0>;
 331 };
 332
 333 &eth0 {
 334         compatible = "marvell,armada-370-neta";
 335 };
 336
 337 &eth1 {
 338         compatible = "marvell,armada-370-neta";
 339 };
 340
 341 &pinctrl {
 342         compatible = "marvell,mv88f6710-pinctrl";
 343
 344         spi0_pins1: spi0-pins1 {
 345                 marvell,pins = "mpp33", "mpp34",
 346                                "mpp35", "mpp36";
 347                 marvell,function = "spi0";
 348         };
 349
 350         spi0_pins2: spi0_pins2 {
 351                 marvell,pins = "mpp32", "mpp63",
 352                                "mpp64", "mpp65";
 353                 marvell,function = "spi0";
 354         };
 355
 356         spi1_pins: spi1-pins {
 357                 marvell,pins = "mpp49", "mpp50",
 358                                "mpp51", "mpp52";
 359                 marvell,function = "spi1";
 360         };
 361
 362         uart0_pins: uart0-pins {
 363                 marvell,pins = "mpp0", "mpp1";
 364                 marvell,function = "uart0";
 365         };
 366
 367         uart1_pins: uart1-pins {
 368                 marvell,pins = "mpp41", "mpp42";
 369                 marvell,function = "uart1";
 370         };
 371
 372         sdio_pins1: sdio-pins1 {
 373                 marvell,pins = "mpp9",  "mpp11", "mpp12",
 374                                 "mpp13", "mpp14", "mpp15";
 375                 marvell,function = "sd0";
 376         };
 377
 378         sdio_pins2: sdio-pins2 {
 379                 marvell,pins = "mpp47", "mpp48", "mpp49",
 380                                 "mpp50", "mpp51", "mpp52";
 381                 marvell,function = "sd0";
 382         };
 383
 384         sdio_pins3: sdio-pins3 {
 385                 marvell,pins = "mpp48", "mpp49", "mpp50",
 386                                 "mpp51", "mpp52", "mpp53";
 387                 marvell,function = "sd0";
 388         };
 389
 390         i2c0_pins: i2c0-pins {
 391                 marvell,pins = "mpp2", "mpp3";
 392                 marvell,function = "i2c0";
 393         };
 394
 395         i2s_pins1: i2s-pins1 {
 396                 marvell,pins = "mpp5", "mpp6", "mpp7",
 397                                "mpp8", "mpp9", "mpp10",
 398                                "mpp12", "mpp13";
 399                 marvell,function = "audio";
 400         };
 401
 402         i2s_pins2: i2s-pins2 {
 403                 marvell,pins = "mpp49", "mpp47", "mpp50",
 404                                "mpp59", "mpp57", "mpp61",
 405                                "mpp62", "mpp60", "mpp58";
 406                 marvell,function = "audio";
 407         };
 408
 409         mdio_pins: mdio-pins {
 410                 marvell,pins = "mpp17", "mpp18";
 411                 marvell,function = "ge";
 412         };
 413
 414         ge0_rgmii_pins: ge0-rgmii-pins {
 415                 marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
 416                                "mpp9", "mpp10", "mpp11", "mpp12",
 417                                "mpp13", "mpp14", "mpp15", "mpp16";
 418                 marvell,function = "ge0";
 419         };
 420
 421         ge1_rgmii_pins: ge1-rgmii-pins {
 422                 marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
 423                                "mpp23", "mpp24", "mpp25", "mpp26",
 424                                "mpp27", "mpp28", "mpp29", "mpp30";
 425                 marvell,function = "ge1";
 426         };
 427 };
 428
 429 /*
 430  * Default SPI pinctrl setting, can be overwritten on
 431  * board level if a different configuration is used.
 432  */
 433 &spi0 {
 434         compatible = "marvell,armada-370-spi", "marvell,orion-spi";
 435         pinctrl-0 = <&spi0_pins1>;
 436         pinctrl-names = "default";
 437 };
 438
 439 &spi1 {
 440         compatible = "marvell,armada-370-spi", "marvell,orion-spi";
 441         pinctrl-0 = <&spi1_pins>;
 442         pinctrl-names = "default";
 443 };