arch/arm/boot/dts/imx53.dtsi

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  * Copyright 2011 Linaro Ltd.
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include "skeleton.dtsi"
  14 #include "imx53-pinfunc.h"
  15 #include <dt-bindings/clock/imx5-clock.h>
  16 #include <dt-bindings/gpio/gpio.h>
  17 #include <dt-bindings/input/input.h>
  18
  19 / {
  20         aliases {
  21                 ethernet0 = &fec;
  22                 gpio0 = &gpio1;
  23                 gpio1 = &gpio2;
  24                 gpio2 = &gpio3;
  25                 gpio3 = &gpio4;
  26                 gpio4 = &gpio5;
  27                 gpio5 = &gpio6;
  28                 gpio6 = &gpio7;
  29                 i2c0 = &i2c1;
  30                 i2c1 = &i2c2;
  31                 i2c2 = &i2c3;
  32                 mmc0 = &esdhc1;
  33                 mmc1 = &esdhc2;
  34                 mmc2 = &esdhc3;
  35                 mmc3 = &esdhc4;
  36                 serial0 = &uart1;
  37                 serial1 = &uart2;
  38                 serial2 = &uart3;
  39                 serial3 = &uart4;
  40                 serial4 = &uart5;
  41                 spi0 = &ecspi1;
  42                 spi1 = &ecspi2;
  43                 spi2 = &cspi;
  44         };
  45
  46         cpus {
  47                 #address-cells = <1>;
  48                 #size-cells = <0>;
  49                 cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "arm,cortex-a8";
  52                         reg = <0x0>;
  53                 };
  54         };
  55
  56         display-subsystem {
  57                 compatible = "fsl,imx-display-subsystem";
  58                 ports = <&ipu_di0>, <&ipu_di1>;
  59         };
  60
  61         tzic: tz-interrupt-controller@0fffc000 {
  62                 compatible = "fsl,imx53-tzic", "fsl,tzic";
  63                 interrupt-controller;
  64                 #interrupt-cells = <1>;
  65                 reg = <0x0fffc000 0x4000>;
  66         };
  67
  68         clocks {
  69                 #address-cells = <1>;
  70                 #size-cells = <0>;
  71
  72                 ckil {
  73                         compatible = "fsl,imx-ckil", "fixed-clock";
  74                         #clock-cells = <0>;
  75                         clock-frequency = <32768>;
  76                 };
  77
  78                 ckih1 {
  79                         compatible = "fsl,imx-ckih1", "fixed-clock";
  80                         #clock-cells = <0>;
  81                         clock-frequency = <22579200>;
  82                 };
  83
  84                 ckih2 {
  85                         compatible = "fsl,imx-ckih2", "fixed-clock";
  86                         #clock-cells = <0>;
  87                         clock-frequency = <0>;
  88                 };
  89
  90                 osc {
  91                         compatible = "fsl,imx-osc", "fixed-clock";
  92                         #clock-cells = <0>;
  93                         clock-frequency = <24000000>;
  94                 };
  95         };
  96
  97         soc {
  98                 #address-cells = <1>;
  99                 #size-cells = <1>;
 100                 compatible = "simple-bus";
 101                 interrupt-parent = <&tzic>;
 102                 ranges;
 103
 104                 sata: sata@10000000 {
 105                         compatible = "fsl,imx53-ahci";
 106                         reg = <0x10000000 0x1000>;
 107                         interrupts = <28>;
 108                         clocks = <&clks IMX5_CLK_SATA_GATE>,
 109                                  <&clks IMX5_CLK_SATA_REF>,
 110                                  <&clks IMX5_CLK_AHB>;
 111                         clock-names = "sata", "sata_ref", "ahb";
 112                         status = "disabled";
 113                 };
 114
 115                 ipu: ipu@18000000 {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         compatible = "fsl,imx53-ipu";
 119                         reg = <0x18000000 0x08000000>;
 120                         interrupts = <11 10>;
 121                         clocks = <&clks IMX5_CLK_IPU_GATE>,
 122                                  <&clks IMX5_CLK_IPU_DI0_GATE>,
 123                                  <&clks IMX5_CLK_IPU_DI1_GATE>;
 124                         clock-names = "bus", "di0", "di1";
 125                         resets = <&src 2>;
 126
 127                         ipu_di0: port@2 {
 128                                 #address-cells = <1>;
 129                                 #size-cells = <0>;
 130                                 reg = <2>;
 131
 132                                 ipu_di0_disp0: endpoint@0 {
 133                                         reg = <0>;
 134                                 };
 135
 136                                 ipu_di0_lvds0: endpoint@1 {
 137                                         reg = <1>;
 138                                         remote-endpoint = <&lvds0_in>;
 139                                 };
 140                         };
 141
 142                         ipu_di1: port@3 {
 143                                 #address-cells = <1>;
 144                                 #size-cells = <0>;
 145                                 reg = <3>;
 146
 147                                 ipu_di1_disp1: endpoint@0 {
 148                                         reg = <0>;
 149                                 };
 150
 151                                 ipu_di1_lvds1: endpoint@1 {
 152                                         reg = <1>;
 153                                         remote-endpoint = <&lvds1_in>;
 154                                 };
 155
 156                                 ipu_di1_tve: endpoint@2 {
 157                                         reg = <2>;
 158                                         remote-endpoint = <&tve_in>;
 159                                 };
 160                         };
 161                 };
 162
 163                 aips@50000000 { /* AIPS1 */
 164                         compatible = "fsl,aips-bus", "simple-bus";
 165                         #address-cells = <1>;
 166                         #size-cells = <1>;
 167                         reg = <0x50000000 0x10000000>;
 168                         ranges;
 169
 170                         spba@50000000 {
 171                                 compatible = "fsl,spba-bus", "simple-bus";
 172                                 #address-cells = <1>;
 173                                 #size-cells = <1>;
 174                                 reg = <0x50000000 0x40000>;
 175                                 ranges;
 176
 177                                 esdhc1: esdhc@50004000 {
 178                                         compatible = "fsl,imx53-esdhc";
 179                                         reg = <0x50004000 0x4000>;
 180                                         interrupts = <1>;
 181                                         clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
 182                                                  <&clks IMX5_CLK_DUMMY>,
 183                                                  <&clks IMX5_CLK_ESDHC1_PER_GATE>;
 184                                         clock-names = "ipg", "ahb", "per";
 185                                         bus-width = <4>;
 186                                         status = "disabled";
 187                                 };
 188
 189                                 esdhc2: esdhc@50008000 {
 190                                         compatible = "fsl,imx53-esdhc";
 191                                         reg = <0x50008000 0x4000>;
 192                                         interrupts = <2>;
 193                                         clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
 194                                                  <&clks IMX5_CLK_DUMMY>,
 195                                                  <&clks IMX5_CLK_ESDHC2_PER_GATE>;
 196                                         clock-names = "ipg", "ahb", "per";
 197                                         bus-width = <4>;
 198                                         status = "disabled";
 199                                 };
 200
 201                                 uart3: serial@5000c000 {
 202                                         compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 203                                         reg = <0x5000c000 0x4000>;
 204                                         interrupts = <33>;
 205                                         clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
 206                                                  <&clks IMX5_CLK_UART3_PER_GATE>;
 207                                         clock-names = "ipg", "per";
 208                                         status = "disabled";
 209                                 };
 210
 211                                 ecspi1: ecspi@50010000 {
 212                                         #address-cells = <1>;
 213                                         #size-cells = <0>;
 214                                         compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 215                                         reg = <0x50010000 0x4000>;
 216                                         interrupts = <36>;
 217                                         clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
 218                                                  <&clks IMX5_CLK_ECSPI1_PER_GATE>;
 219                                         clock-names = "ipg", "per";
 220                                         status = "disabled";
 221                                 };
 222
 223                                 ssi2: ssi@50014000 {
 224                                         #sound-dai-cells = <0>;
 225                                         compatible = "fsl,imx53-ssi",
 226                                                         "fsl,imx51-ssi",
 227                                                         "fsl,imx21-ssi";
 228                                         reg = <0x50014000 0x4000>;
 229                                         interrupts = <30>;
 230                                         clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>,
 231                                                  <&clks IMX5_CLK_SSI2_ROOT_GATE>;
 232                                         clock-names = "ipg", "baud";
 233                                         dmas = <&sdma 24 1 0>,
 234                                                <&sdma 25 1 0>;
 235                                         dma-names = "rx", "tx";
 236                                         fsl,fifo-depth = <15>;
 237                                         status = "disabled";
 238                                 };
 239
 240                                 esdhc3: esdhc@50020000 {
 241                                         compatible = "fsl,imx53-esdhc";
 242                                         reg = <0x50020000 0x4000>;
 243                                         interrupts = <3>;
 244                                         clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>,
 245                                                  <&clks IMX5_CLK_DUMMY>,
 246                                                  <&clks IMX5_CLK_ESDHC3_PER_GATE>;
 247                                         clock-names = "ipg", "ahb", "per";
 248                                         bus-width = <4>;
 249                                         status = "disabled";
 250                                 };
 251
 252                                 esdhc4: esdhc@50024000 {
 253                                         compatible = "fsl,imx53-esdhc";
 254                                         reg = <0x50024000 0x4000>;
 255                                         interrupts = <4>;
 256                                         clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>,
 257                                                  <&clks IMX5_CLK_DUMMY>,
 258                                                  <&clks IMX5_CLK_ESDHC4_PER_GATE>;
 259                                         clock-names = "ipg", "ahb", "per";
 260                                         bus-width = <4>;
 261                                         status = "disabled";
 262                                 };
 263                         };
 264
 265                         aipstz1: bridge@53f00000 {
 266                                 compatible = "fsl,imx53-aipstz";
 267                                 reg = <0x53f00000 0x60>;
 268                         };
 269
 270                         usbphy0: usbphy@0 {
 271                                 compatible = "usb-nop-xceiv";
 272                                 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
 273                                 clock-names = "main_clk";
 274                                 status = "okay";
 275                         };
 276
 277                         usbphy1: usbphy@1 {
 278                                 compatible = "usb-nop-xceiv";
 279                                 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
 280                                 clock-names = "main_clk";
 281                                 status = "okay";
 282                         };
 283
 284                         usbotg: usb@53f80000 {
 285                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 286                                 reg = <0x53f80000 0x0200>;
 287                                 interrupts = <18>;
 288                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 289                                 fsl,usbmisc = <&usbmisc 0>;
 290                                 fsl,usbphy = <&usbphy0>;
 291                                 status = "disabled";
 292                         };
 293
 294                         usbh1: usb@53f80200 {
 295                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 296                                 reg = <0x53f80200 0x0200>;
 297                                 interrupts = <14>;
 298                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 299                                 fsl,usbmisc = <&usbmisc 1>;
 300                                 fsl,usbphy = <&usbphy1>;
 301                                 status = "disabled";
 302                         };
 303
 304                         usbh2: usb@53f80400 {
 305                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 306                                 reg = <0x53f80400 0x0200>;
 307                                 interrupts = <16>;
 308                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 309                                 fsl,usbmisc = <&usbmisc 2>;
 310                                 status = "disabled";
 311                         };
 312
 313                         usbh3: usb@53f80600 {
 314                                 compatible = "fsl,imx53-usb", "fsl,imx27-usb";
 315                                 reg = <0x53f80600 0x0200>;
 316                                 interrupts = <17>;
 317                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 318                                 fsl,usbmisc = <&usbmisc 3>;
 319                                 status = "disabled";
 320                         };
 321
 322                         usbmisc: usbmisc@53f80800 {
 323                                 #index-cells = <1>;
 324                                 compatible = "fsl,imx53-usbmisc";
 325                                 reg = <0x53f80800 0x200>;
 326                                 clocks = <&clks IMX5_CLK_USBOH3_GATE>;
 327                         };
 328
 329                         gpio1: gpio@53f84000 {
 330                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 331                                 reg = <0x53f84000 0x4000>;
 332                                 interrupts = <50 51>;
 333                                 gpio-controller;
 334                                 #gpio-cells = <2>;
 335                                 interrupt-controller;
 336                                 #interrupt-cells = <2>;
 337                         };
 338
 339                         gpio2: gpio@53f88000 {
 340                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 341                                 reg = <0x53f88000 0x4000>;
 342                                 interrupts = <52 53>;
 343                                 gpio-controller;
 344                                 #gpio-cells = <2>;
 345                                 interrupt-controller;
 346                                 #interrupt-cells = <2>;
 347                         };
 348
 349                         gpio3: gpio@53f8c000 {
 350                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 351                                 reg = <0x53f8c000 0x4000>;
 352                                 interrupts = <54 55>;
 353                                 gpio-controller;
 354                                 #gpio-cells = <2>;
 355                                 interrupt-controller;
 356                                 #interrupt-cells = <2>;
 357                         };
 358
 359                         gpio4: gpio@53f90000 {
 360                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 361                                 reg = <0x53f90000 0x4000>;
 362                                 interrupts = <56 57>;
 363                                 gpio-controller;
 364                                 #gpio-cells = <2>;
 365                                 interrupt-controller;
 366                                 #interrupt-cells = <2>;
 367                         };
 368
 369                         kpp: kpp@53f94000 {
 370                                 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp";
 371                                 reg = <0x53f94000 0x4000>;
 372                                 interrupts = <60>;
 373                                 clocks = <&clks IMX5_CLK_DUMMY>;
 374                                 status = "disabled";
 375                         };
 376
 377                         wdog1: wdog@53f98000 {
 378                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 379                                 reg = <0x53f98000 0x4000>;
 380                                 interrupts = <58>;
 381                                 clocks = <&clks IMX5_CLK_DUMMY>;
 382                         };
 383
 384                         wdog2: wdog@53f9c000 {
 385                                 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt";
 386                                 reg = <0x53f9c000 0x4000>;
 387                                 interrupts = <59>;
 388                                 clocks = <&clks IMX5_CLK_DUMMY>;
 389                                 status = "disabled";
 390                         };
 391
 392                         gpt: timer@53fa0000 {
 393                                 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt";
 394                                 reg = <0x53fa0000 0x4000>;
 395                                 interrupts = <39>;
 396                                 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>,
 397                                          <&clks IMX5_CLK_GPT_HF_GATE>;
 398                                 clock-names = "ipg", "per";
 399                         };
 400
 401                         iomuxc: iomuxc@53fa8000 {
 402                                 compatible = "fsl,imx53-iomuxc";
 403                                 reg = <0x53fa8000 0x4000>;
 404                         };
 405
 406                         gpr: iomuxc-gpr@53fa8000 {
 407                                 compatible = "fsl,imx53-iomuxc-gpr", "syscon";
 408                                 reg = <0x53fa8000 0xc>;
 409                         };
 410
 411                         ldb: ldb@53fa8008 {
 412                                 #address-cells = <1>;
 413                                 #size-cells = <0>;
 414                                 compatible = "fsl,imx53-ldb";
 415                                 reg = <0x53fa8008 0x4>;
 416                                 gpr = <&gpr>;
 417                                 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>,
 418                                          <&clks IMX5_CLK_LDB_DI1_SEL>,
 419                                          <&clks IMX5_CLK_IPU_DI0_SEL>,
 420                                          <&clks IMX5_CLK_IPU_DI1_SEL>,
 421                                          <&clks IMX5_CLK_LDB_DI0_GATE>,
 422                                          <&clks IMX5_CLK_LDB_DI1_GATE>;
 423                                 clock-names = "di0_pll", "di1_pll",
 424                                               "di0_sel", "di1_sel",
 425                                               "di0", "di1";
 426                                 status = "disabled";
 427
 428                                 lvds-channel@0 {
 429                                         #address-cells = <1>;
 430                                         #size-cells = <0>;
 431                                         reg = <0>;
 432                                         status = "disabled";
 433
 434                                         port@0 {
 435                                                 reg = <0>;
 436
 437                                                 lvds0_in: endpoint {
 438                                                         remote-endpoint = <&ipu_di0_lvds0>;
 439                                                 };
 440                                         };
 441                                 };
 442
 443                                 lvds-channel@1 {
 444                                         #address-cells = <1>;
 445                                         #size-cells = <0>;
 446                                         reg = <1>;
 447                                         status = "disabled";
 448
 449                                         port@1 {
 450                                                 reg = <1>;
 451
 452                                                 lvds1_in: endpoint {
 453                                                         remote-endpoint = <&ipu_di1_lvds1>;
 454                                                 };
 455                                         };
 456                                 };
 457                         };
 458
 459                         pwm1: pwm@53fb4000 {
 460                                 #pwm-cells = <2>;
 461                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 462                                 reg = <0x53fb4000 0x4000>;
 463                                 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>,
 464                                          <&clks IMX5_CLK_PWM1_HF_GATE>;
 465                                 clock-names = "ipg", "per";
 466                                 interrupts = <61>;
 467                         };
 468
 469                         pwm2: pwm@53fb8000 {
 470                                 #pwm-cells = <2>;
 471                                 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm";
 472                                 reg = <0x53fb8000 0x4000>;
 473                                 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>,
 474                                          <&clks IMX5_CLK_PWM2_HF_GATE>;
 475                                 clock-names = "ipg", "per";
 476                                 interrupts = <94>;
 477                         };
 478
 479                         uart1: serial@53fbc000 {
 480                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 481                                 reg = <0x53fbc000 0x4000>;
 482                                 interrupts = <31>;
 483                                 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>,
 484                                          <&clks IMX5_CLK_UART1_PER_GATE>;
 485                                 clock-names = "ipg", "per";
 486                                 status = "disabled";
 487                         };
 488
 489                         uart2: serial@53fc0000 {
 490                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 491                                 reg = <0x53fc0000 0x4000>;
 492                                 interrupts = <32>;
 493                                 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>,
 494                                          <&clks IMX5_CLK_UART2_PER_GATE>;
 495                                 clock-names = "ipg", "per";
 496                                 status = "disabled";
 497                         };
 498
 499                         can1: can@53fc8000 {
 500                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 501                                 reg = <0x53fc8000 0x4000>;
 502                                 interrupts = <82>;
 503                                 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>,
 504                                          <&clks IMX5_CLK_CAN1_SERIAL_GATE>;
 505                                 clock-names = "ipg", "per";
 506                                 status = "disabled";
 507                         };
 508
 509                         can2: can@53fcc000 {
 510                                 compatible = "fsl,imx53-flexcan", "fsl,p1010-flexcan";
 511                                 reg = <0x53fcc000 0x4000>;
 512                                 interrupts = <83>;
 513                                 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>,
 514                                          <&clks IMX5_CLK_CAN2_SERIAL_GATE>;
 515                                 clock-names = "ipg", "per";
 516                                 status = "disabled";
 517                         };
 518
 519                         src: src@53fd0000 {
 520                                 compatible = "fsl,imx53-src", "fsl,imx51-src";
 521                                 reg = <0x53fd0000 0x4000>;
 522                                 #reset-cells = <1>;
 523                         };
 524
 525                         clks: ccm@53fd4000{
 526                                 compatible = "fsl,imx53-ccm";
 527                                 reg = <0x53fd4000 0x4000>;
 528                                 interrupts = <0 71 0x04 0 72 0x04>;
 529                                 #clock-cells = <1>;
 530                         };
 531
 532                         gpio5: gpio@53fdc000 {
 533                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 534                                 reg = <0x53fdc000 0x4000>;
 535                                 interrupts = <103 104>;
 536                                 gpio-controller;
 537                                 #gpio-cells = <2>;
 538                                 interrupt-controller;
 539                                 #interrupt-cells = <2>;
 540                         };
 541
 542                         gpio6: gpio@53fe0000 {
 543                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 544                                 reg = <0x53fe0000 0x4000>;
 545                                 interrupts = <105 106>;
 546                                 gpio-controller;
 547                                 #gpio-cells = <2>;
 548                                 interrupt-controller;
 549                                 #interrupt-cells = <2>;
 550                         };
 551
 552                         gpio7: gpio@53fe4000 {
 553                                 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio";
 554                                 reg = <0x53fe4000 0x4000>;
 555                                 interrupts = <107 108>;
 556                                 gpio-controller;
 557                                 #gpio-cells = <2>;
 558                                 interrupt-controller;
 559                                 #interrupt-cells = <2>;
 560                         };
 561
 562                         i2c3: i2c@53fec000 {
 563                                 #address-cells = <1>;
 564                                 #size-cells = <0>;
 565                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 566                                 reg = <0x53fec000 0x4000>;
 567                                 interrupts = <64>;
 568                                 clocks = <&clks IMX5_CLK_I2C3_GATE>;
 569                                 status = "disabled";
 570                         };
 571
 572                         uart4: serial@53ff0000 {
 573                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 574                                 reg = <0x53ff0000 0x4000>;
 575                                 interrupts = <13>;
 576                                 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>,
 577                                          <&clks IMX5_CLK_UART4_PER_GATE>;
 578                                 clock-names = "ipg", "per";
 579                                 status = "disabled";
 580                         };
 581                 };
 582
 583                 aips@60000000 { /* AIPS2 */
 584                         compatible = "fsl,aips-bus", "simple-bus";
 585                         #address-cells = <1>;
 586                         #size-cells = <1>;
 587                         reg = <0x60000000 0x10000000>;
 588                         ranges;
 589
 590                         aipstz2: bridge@63f00000 {
 591                                 compatible = "fsl,imx53-aipstz";
 592                                 reg = <0x63f00000 0x60>;
 593                         };
 594
 595                         iim: iim@63f98000 {
 596                                 compatible = "fsl,imx53-iim", "fsl,imx27-iim";
 597                                 reg = <0x63f98000 0x4000>;
 598                                 interrupts = <69>;
 599                                 clocks = <&clks IMX5_CLK_IIM_GATE>;
 600                         };
 601
 602                         uart5: serial@63f90000 {
 603                                 compatible = "fsl,imx53-uart", "fsl,imx21-uart";
 604                                 reg = <0x63f90000 0x4000>;
 605                                 interrupts = <86>;
 606                                 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>,
 607                                          <&clks IMX5_CLK_UART5_PER_GATE>;
 608                                 clock-names = "ipg", "per";
 609                                 status = "disabled";
 610                         };
 611
 612                         owire: owire@63fa4000 {
 613                                 compatible = "fsl,imx53-owire", "fsl,imx21-owire";
 614                                 reg = <0x63fa4000 0x4000>;
 615                                 clocks = <&clks IMX5_CLK_OWIRE_GATE>;
 616                                 status = "disabled";
 617                         };
 618
 619                         ecspi2: ecspi@63fac000 {
 620                                 #address-cells = <1>;
 621                                 #size-cells = <0>;
 622                                 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi";
 623                                 reg = <0x63fac000 0x4000>;
 624                                 interrupts = <37>;
 625                                 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>,
 626                                          <&clks IMX5_CLK_ECSPI2_PER_GATE>;
 627                                 clock-names = "ipg", "per";
 628                                 status = "disabled";
 629                         };
 630
 631                         sdma: sdma@63fb0000 {
 632                                 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma";
 633                                 reg = <0x63fb0000 0x4000>;
 634                                 interrupts = <6>;
 635                                 clocks = <&clks IMX5_CLK_SDMA_GATE>,
 636                                          <&clks IMX5_CLK_SDMA_GATE>;
 637                                 clock-names = "ipg", "ahb";
 638                                 #dma-cells = <3>;
 639                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin";
 640                         };
 641
 642                         cspi: cspi@63fc0000 {
 643                                 #address-cells = <1>;
 644                                 #size-cells = <0>;
 645                                 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi";
 646                                 reg = <0x63fc0000 0x4000>;
 647                                 interrupts = <38>;
 648                                 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>,
 649                                          <&clks IMX5_CLK_CSPI_IPG_GATE>;
 650                                 clock-names = "ipg", "per";
 651                                 status = "disabled";
 652                         };
 653
 654                         i2c2: i2c@63fc4000 {
 655                                 #address-cells = <1>;
 656                                 #size-cells = <0>;
 657                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 658                                 reg = <0x63fc4000 0x4000>;
 659                                 interrupts = <63>;
 660                                 clocks = <&clks IMX5_CLK_I2C2_GATE>;
 661                                 status = "disabled";
 662                         };
 663
 664                         i2c1: i2c@63fc8000 {
 665                                 #address-cells = <1>;
 666                                 #size-cells = <0>;
 667                                 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c";
 668                                 reg = <0x63fc8000 0x4000>;
 669                                 interrupts = <62>;
 670                                 clocks = <&clks IMX5_CLK_I2C1_GATE>;
 671                                 status = "disabled";
 672                         };
 673
 674                         ssi1: ssi@63fcc000 {
 675                                 #sound-dai-cells = <0>;
 676                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 677                                                 "fsl,imx21-ssi";
 678                                 reg = <0x63fcc000 0x4000>;
 679                                 interrupts = <29>;
 680                                 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>,
 681                                          <&clks IMX5_CLK_SSI1_ROOT_GATE>;
 682                                 clock-names = "ipg", "baud";
 683                                 dmas = <&sdma 28 0 0>,
 684                                        <&sdma 29 0 0>;
 685                                 dma-names = "rx", "tx";
 686                                 fsl,fifo-depth = <15>;
 687                                 status = "disabled";
 688                         };
 689
 690                         audmux: audmux@63fd0000 {
 691                                 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux";
 692                                 reg = <0x63fd0000 0x4000>;
 693                                 status = "disabled";
 694                         };
 695
 696                         nfc: nand@63fdb000 {
 697                                 compatible = "fsl,imx53-nand";
 698                                 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>;
 699                                 interrupts = <8>;
 700                                 clocks = <&clks IMX5_CLK_NFC_GATE>;
 701                                 status = "disabled";
 702                         };
 703
 704                         ssi3: ssi@63fe8000 {
 705                                 #sound-dai-cells = <0>;
 706                                 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi",
 707                                                 "fsl,imx21-ssi";
 708                                 reg = <0x63fe8000 0x4000>;
 709                                 interrupts = <96>;
 710                                 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>,
 711                                          <&clks IMX5_CLK_SSI3_ROOT_GATE>;
 712                                 clock-names = "ipg", "baud";
 713                                 dmas = <&sdma 46 0 0>,
 714                                        <&sdma 47 0 0>;
 715                                 dma-names = "rx", "tx";
 716                                 fsl,fifo-depth = <15>;
 717                                 status = "disabled";
 718                         };
 719
 720                         fec: ethernet@63fec000 {
 721                                 compatible = "fsl,imx53-fec", "fsl,imx25-fec";
 722                                 reg = <0x63fec000 0x4000>;
 723                                 interrupts = <87>;
 724                                 clocks = <&clks IMX5_CLK_FEC_GATE>,
 725                                          <&clks IMX5_CLK_FEC_GATE>,
 726                                          <&clks IMX5_CLK_FEC_GATE>;
 727                                 clock-names = "ipg", "ahb", "ptp";
 728                                 status = "disabled";
 729                         };
 730
 731                         tve: tve@63ff0000 {
 732                                 compatible = "fsl,imx53-tve";
 733                                 reg = <0x63ff0000 0x1000>;
 734                                 interrupts = <92>;
 735                                 clocks = <&clks IMX5_CLK_TVE_GATE>,
 736                                          <&clks IMX5_CLK_IPU_DI1_SEL>;
 737                                 clock-names = "tve", "di_sel";
 738                                 status = "disabled";
 739
 740                                 port {
 741                                         tve_in: endpoint {
 742                                                 remote-endpoint = <&ipu_di1_tve>;
 743                                         };
 744                                 };
 745                         };
 746
 747                         vpu: vpu@63ff4000 {
 748                                 compatible = "fsl,imx53-vpu";
 749                                 reg = <0x63ff4000 0x1000>;
 750                                 interrupts = <9>;
 751                                 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>,
 752                                          <&clks IMX5_CLK_VPU_GATE>;
 753                                 clock-names = "per", "ahb";
 754                                 resets = <&src 1>;
 755                                 iram = <&ocram>;
 756                         };
 757                 };
 758
 759                 ocram: sram@f8000000 {
 760                         compatible = "mmio-sram";
 761                         reg = <0xf8000000 0x20000>;
 762                         clocks = <&clks IMX5_CLK_OCRAM>;
 763                 };
 764
 765                 pmu {
 766                         compatible = "arm,cortex-a8-pmu";
 767                         interrupts = <77>;
 768                 };
 769         };
 770 };