arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi

   1 /*
   2  * Copyright 2013 Christian Hemp, Phytec Messtechnik GmbH
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include <dt-bindings/gpio/gpio.h>
  13
  14 / {
  15         model = "Phytec phyFLEX-i.MX6 Quad";
  16         compatible = "phytec,imx6q-pfla02", "fsl,imx6q";
  17
  18         memory@10000000 {
  19                 device_type = "memory";
  20                 reg = <0x10000000 0x80000000>;
  21         };
  22
  23         regulators {
  24                 compatible = "simple-bus";
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 reg_usb_otg_vbus: regulator@0 {
  29                         compatible = "regulator-fixed";
  30                         reg = <0>;
  31                         regulator-name = "usb_otg_vbus";
  32                         regulator-min-microvolt = <5000000>;
  33                         regulator-max-microvolt = <5000000>;
  34                         gpio = <&gpio4 15 0>;
  35                         enable-active-high;
  36                 };
  37
  38                 reg_usb_h1_vbus: regulator@1 {
  39                         compatible = "regulator-fixed";
  40                         reg = <1>;
  41                         regulator-name = "usb_h1_vbus";
  42                         regulator-min-microvolt = <5000000>;
  43                         regulator-max-microvolt = <5000000>;
  44                         gpio = <&gpio1 0 0>;
  45                         enable-active-high;
  46                 };
  47         };
  48
  49         gpio_leds: leds {
  50                 compatible = "gpio-leds";
  51
  52                 green {
  53                         label = "phyflex:green";
  54                         gpios = <&gpio1 30 0>;
  55                 };
  56
  57                 red {
  58                         label = "phyflex:red";
  59                         gpios = <&gpio2 31 0>;
  60                 };
  61         };
  62 };
  63
  64 &audmux {
  65         pinctrl-names = "default";
  66         pinctrl-0 = <&pinctrl_audmux>;
  67         status = "disabled";
  68 };
  69
  70 &can1 {
  71         pinctrl-names = "default";
  72         pinctrl-0 = <&pinctrl_flexcan1>;
  73         status = "disabled";
  74 };
  75
  76 &ecspi3 {
  77         pinctrl-names = "default";
  78         pinctrl-0 = <&pinctrl_ecspi3>;
  79         status = "okay";
  80         cs-gpios = <&gpio4 24 0>;
  81
  82         flash@0 {
  83                 compatible = "m25p80", "jedec,spi-nor";
  84                 spi-max-frequency = <20000000>;
  85                 reg = <0>;
  86         };
  87 };
  88
  89 &fec {
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_enet>;
  92         phy-handle = <&ethphy>;
  93         phy-mode = "rgmii";
  94         phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
  95         phy-supply = <&vdd_eth_io_reg>;
  96         status = "disabled";
  97
  98         fec_mdio: mdio {
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101
 102                 ethphy: ethernet-phy@0 {
 103                         compatible = "ethernet-phy-ieee802.3-c22";
 104                         reg = <0>;
 105                         txc-skew-ps = <1680>;
 106                         rxc-skew-ps = <1860>;
 107                 };
 108         };
 109 };
 110
 111 &gpmi {
 112         pinctrl-names = "default";
 113         pinctrl-0 = <&pinctrl_gpmi_nand>;
 114         nand-on-flash-bbt;
 115         status = "okay";
 116 };
 117
 118 &i2c1 {
 119         pinctrl-names = "default";
 120         pinctrl-0 = <&pinctrl_i2c1>;
 121         status = "okay";
 122
 123         eeprom@50 {
 124                 compatible = "atmel,24c32";
 125                 reg = <0x50>;
 126         };
 127
 128         pmic@58 {
 129                 compatible = "dlg,da9063";
 130                 reg = <0x58>;
 131                 interrupt-parent = <&gpio2>;
 132                 interrupts = <9 IRQ_TYPE_LEVEL_LOW>; /* active-low GPIO2_9 */
 133                 interrupt-controller;
 134
 135                 regulators {
 136                         vddcore_reg: bcore1 {
 137                                 regulator-min-microvolt = <730000>;
 138                                 regulator-max-microvolt = <1380000>;
 139                                 regulator-always-on;
 140                         };
 141
 142                         vddsoc_reg: bcore2 {
 143                                 regulator-min-microvolt = <730000>;
 144                                 regulator-max-microvolt = <1380000>;
 145                                 regulator-always-on;
 146                         };
 147
 148                         vdd_ddr3_reg: bpro {
 149                                 regulator-min-microvolt = <1500000>;
 150                                 regulator-max-microvolt = <1500000>;
 151                                 regulator-always-on;
 152                         };
 153
 154                         vdd_3v3_reg: bperi {
 155                                 regulator-min-microvolt = <3300000>;
 156                                 regulator-max-microvolt = <3300000>;
 157                                 regulator-always-on;
 158                         };
 159
 160                         vdd_buckmem_reg: bmem {
 161                                 regulator-min-microvolt = <3300000>;
 162                                 regulator-max-microvolt = <3300000>;
 163                                 regulator-always-on;
 164                         };
 165
 166                         vdd_eth_reg: bio {
 167                                 regulator-min-microvolt = <1200000>;
 168                                 regulator-max-microvolt = <1200000>;
 169                                 regulator-always-on;
 170                         };
 171
 172                         vdd_eth_io_reg: ldo4 {
 173                                 regulator-min-microvolt = <2500000>;
 174                                 regulator-max-microvolt = <2500000>;
 175                                 regulator-always-on;
 176                         };
 177
 178                         vdd_mx6_snvs_reg: ldo5 {
 179                                 regulator-min-microvolt = <3000000>;
 180                                 regulator-max-microvolt = <3000000>;
 181                                 regulator-always-on;
 182                         };
 183
 184                         vdd_3v3_pmic_io_reg: ldo6 {
 185                                 regulator-min-microvolt = <3300000>;
 186                                 regulator-max-microvolt = <3300000>;
 187                                 regulator-always-on;
 188                         };
 189
 190                         vdd_sd0_reg: ldo9 {
 191                                 regulator-min-microvolt = <3300000>;
 192                                 regulator-max-microvolt = <3300000>;
 193                         };
 194
 195                         vdd_sd1_reg: ldo10 {
 196                                 regulator-min-microvolt = <3300000>;
 197                                 regulator-max-microvolt = <3300000>;
 198                         };
 199
 200                         vdd_mx6_high_reg: ldo11 {
 201                                 regulator-min-microvolt = <3000000>;
 202                                 regulator-max-microvolt = <3000000>;
 203                                 regulator-always-on;
 204                         };
 205                 };
 206         };
 207 };
 208
 209 &i2c2 {
 210         pinctrl-names = "default";
 211         pinctrl-0 = <&pinctrl_i2c2>;
 212         clock-frequency = <100000>;
 213 };
 214
 215 &i2c3 {
 216         pinctrl-names = "default";
 217         pinctrl-0 = <&pinctrl_i2c3>;
 218         clock-frequency = <100000>;
 219 };
 220
 221 &iomuxc {
 222         pinctrl-names = "default";
 223         pinctrl-0 = <&pinctrl_hog>;
 224
 225         imx6q-phytec-pfla02 {
 226                 pinctrl_hog: hoggrp {
 227                         fsl,pins = <
 228                                 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
 229                                 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
 230                                 MX6QDL_PAD_SD4_DAT1__GPIO2_IO09  0x80000000 /* PMIC interrupt */
 231                                 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* Green LED */
 232                                 MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x80000000 /* Red LED */
 233                         >;
 234                 };
 235
 236                 pinctrl_ecspi3: ecspi3grp {
 237                         fsl,pins = <
 238                                 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO      0x100b1
 239                                 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI      0x100b1
 240                                 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK      0x100b1
 241                         >;
 242                 };
 243
 244                 pinctrl_enet: enetgrp {
 245                         fsl,pins = <
 246                                 MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 247                                 MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 248                                 MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b030
 249                                 MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b030
 250                                 MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b030
 251                                 MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b030
 252                                 MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b030
 253                                 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b030
 254                                 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 255                                 MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b030
 256                                 MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b030
 257                                 MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b030
 258                                 MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b030
 259                                 MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b030
 260                                 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b030
 261                                 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x1b0b0
 262                         >;
 263                 };
 264
 265                 pinctrl_flexcan1: flexcan1grp {
 266                         fsl,pins = <
 267                                 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX        0x1b0b0
 268                                 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX        0x1b0b0
 269                         >;
 270                 };
 271
 272                 pinctrl_gpmi_nand: gpminandgrp {
 273                         fsl,pins = <
 274                                 MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 275                                 MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 276                                 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 277                                 MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 278                                 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 279                                 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B        0xb0b1
 280                                 MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 281                                 MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 282                                 MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 283                                 MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 284                                 MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 285                                 MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 286                                 MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 287                                 MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 288                                 MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 289                                 MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 290                                 MX6QDL_PAD_SD4_DAT0__NAND_DQS           0x00b1
 291                         >;
 292                 };
 293
 294                 pinctrl_i2c1: i2c1grp {
 295                         fsl,pins = <
 296                                 MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 297                                 MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 298                         >;
 299                 };
 300
 301                 pinctrl_i2c2: i2c2grp {
 302                         fsl,pins = <
 303                                 MX6QDL_PAD_EIM_EB2__I2C2_SCL            0x4001b8b1
 304                                 MX6QDL_PAD_EIM_D16__I2C2_SDA            0x4001b8b1
 305                         >;
 306                 };
 307
 308                 pinctrl_i2c3: i2c3grp {
 309                         fsl,pins = <
 310                                 MX6QDL_PAD_EIM_D17__I2C3_SCL            0x4001b8b1
 311                                 MX6QDL_PAD_EIM_D18__I2C3_SDA            0x4001b8b1
 312                         >;
 313                 };
 314
 315                 pinctrl_pcie: pciegrp {
 316                         fsl,pins = <MX6QDL_PAD_DI0_PIN15__GPIO4_IO17  0x80000000>;
 317                 };
 318
 319                 pinctrl_uart3: uart3grp {
 320                         fsl,pins = <
 321                                 MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 322                                 MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 323                                 MX6QDL_PAD_EIM_D30__UART3_RTS_B         0x1b0b1
 324                                 MX6QDL_PAD_EIM_D31__UART3_CTS_B         0x1b0b1
 325                         >;
 326                 };
 327
 328                 pinctrl_uart4: uart4grp {
 329                         fsl,pins = <
 330                                 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA      0x1b0b1
 331                                 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA      0x1b0b1
 332                         >;
 333                 };
 334
 335                 pinctrl_usbh1: usbh1grp {
 336                         fsl,pins = <
 337                                 MX6QDL_PAD_GPIO_0__USB_H1_PWR           0x80000000
 338                         >;
 339                 };
 340
 341                 pinctrl_usbotg: usbotggrp {
 342                         fsl,pins = <
 343                                 MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 344                                 MX6QDL_PAD_KEY_COL4__USB_OTG_OC         0x1b0b0
 345                                 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15         0x80000000
 346                         >;
 347                 };
 348
 349                 pinctrl_usdhc2: usdhc2grp {
 350                         fsl,pins = <
 351                                 MX6QDL_PAD_SD2_CMD__SD2_CMD             0x17059
 352                                 MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10059
 353                                 MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
 354                                 MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
 355                                 MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
 356                                 MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
 357                         >;
 358                 };
 359
 360                 pinctrl_usdhc3: usdhc3grp {
 361                         fsl,pins = <
 362                                 MX6QDL_PAD_SD3_CMD__SD3_CMD             0x17059
 363                                 MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10059
 364                                 MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
 365                                 MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
 366                                 MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
 367                                 MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
 368                         >;
 369                 };
 370
 371                 pinctrl_usdhc3_cdwp: usdhc3cdwp {
 372                         fsl,pins = <
 373                                 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000
 374                                 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
 375                         >;
 376                 };
 377
 378                 pinctrl_audmux: audmuxgrp {
 379                         fsl,pins = <
 380                                 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC        0x130b0
 381                                 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD        0x110b0
 382                                 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS       0x130b0
 383                                 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD        0x130b0
 384                         >;
 385                 };
 386         };
 387 };
 388
 389 &pcie {
 390         pinctrl-names = "default";
 391         pinctrl-0 = <&pinctrl_pcie>;
 392         reset-gpio = <&gpio4 17 GPIO_ACTIVE_LOW>;
 393         status = "disabled";
 394 };
 395
 396 &reg_arm {
 397         vin-supply = <&vddcore_reg>;
 398 };
 399
 400 &reg_pu {
 401         vin-supply = <&vddsoc_reg>;
 402 };
 403
 404 &reg_soc {
 405         vin-supply = <&vddsoc_reg>;
 406 };
 407
 408 &uart3 {
 409         pinctrl-names = "default";
 410         pinctrl-0 = <&pinctrl_uart3>;
 411         status = "disabled";
 412 };
 413
 414 &uart4 {
 415         pinctrl-names = "default";
 416         pinctrl-0 = <&pinctrl_uart4>;
 417         status = "disabled";
 418 };
 419
 420 &usbh1 {
 421         vbus-supply = <&reg_usb_h1_vbus>;
 422         pinctrl-names = "default";
 423         pinctrl-0 = <&pinctrl_usbh1>;
 424         status = "disabled";
 425 };
 426
 427 &usbotg {
 428         vbus-supply = <&reg_usb_otg_vbus>;
 429         pinctrl-names = "default";
 430         pinctrl-0 = <&pinctrl_usbotg>;
 431         disable-over-current;
 432         status = "disabled";
 433 };
 434
 435 &usdhc2 {
 436         pinctrl-names = "default";
 437         pinctrl-0 = <&pinctrl_usdhc2>;
 438         cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
 439         wp-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 440         status = "disabled";
 441 };
 442
 443 &usdhc3 {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&pinctrl_usdhc3
 446                      &pinctrl_usdhc3_cdwp>;
 447         cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 448         wp-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
 449         status = "disabled";
 450 };