arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi

   1 /*
   2  * Copyright (C) 2016-2017 Zodiac Inflight Innovations
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 #include <dt-bindings/gpio/gpio.h>
  43 #include <dt-bindings/sound/fsl-imx-audmux.h>
  44
  45 / {
  46         chosen {
  47                 stdout-path = &uart1;
  48         };
  49
  50         aliases {
  51                 mdio-gpio0 = &mdio1;
  52                 rtc0 = &ds1341;
  53         };
  54
  55         mdio1: mdio {
  56                 compatible = "virtual,mdio-gpio";
  57                 #address-cells = <1>;
  58                 #size-cells = <0>;
  59                 pinctrl-names = "default";
  60                 pinctrl-0 = <&pinctrl_mdio1>;
  61                 gpios = <&gpio6 5 GPIO_ACTIVE_HIGH
  62                          &gpio6 4 GPIO_ACTIVE_HIGH>;
  63
  64                 phy: ethernet-phy@0 {
  65                         pinctrl-0 = <&pinctrl_rmii_phy_irq>;
  66                         pinctrl-names = "default";
  67                         reg = <0>;
  68                         interrupt-parent = <&gpio3>;
  69                         interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
  70                 };
  71         };
  72
  73         reg_28p0v: regulator-28p0v {
  74                 compatible = "regulator-fixed";
  75                 regulator-name = "28V_IN";
  76                 regulator-min-microvolt = <28000000>;
  77                 regulator-max-microvolt = <28000000>;
  78                 regulator-always-on;
  79         };
  80
  81         reg_12p0v: regulator-12p0v {
  82                 compatible = "regulator-fixed";
  83                 vin-supply = <&reg_28p0v>;
  84                 regulator-name = "12V_MAIN";
  85                 regulator-min-microvolt = <12000000>;
  86                 regulator-max-microvolt = <12000000>;
  87                 regulator-always-on;
  88         };
  89
  90         reg_5p0v_main: regulator-5p0v-main {
  91                 compatible = "regulator-fixed";
  92                 vin-supply = <&reg_12p0v>;
  93                 regulator-name = "5V_MAIN";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-always-on;
  97         };
  98
  99         reg_5p0v_user_usb: regulator-5p0v-user-usb {
 100                 compatible = "regulator-fixed";
 101                 pinctrl-names = "default";
 102                 pinctrl-0 = <&pinctrl_reg_user_usb>;
 103                 vin-supply = <&reg_5p0v_main>;
 104                 regulator-name = "5V_USER_USB";
 105                 regulator-min-microvolt = <5000000>;
 106                 regulator-max-microvolt = <5000000>;
 107                 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>;
 108                 startup-delay-us = <1000>;
 109         };
 110
 111         reg_3p3v_pmic: regulator-3p3v-pmic {
 112                 compatible = "regulator-fixed";
 113                 vin-supply = <&reg_12p0v>;
 114                 regulator-name = "PMIC_3V3";
 115                 regulator-min-microvolt = <3300000>;
 116                 regulator-max-microvolt = <3300000>;
 117                 regulator-always-on;
 118         };
 119
 120         reg_3p3v: regulator-3p3v {
 121                 compatible = "regulator-fixed";
 122                 vin-supply = <&reg_3p3v_pmic>;
 123                 regulator-name = "GEN_3V3";
 124                 regulator-min-microvolt = <3300000>;
 125                 regulator-max-microvolt = <3300000>;
 126                 regulator-always-on;
 127         };
 128
 129         reg_3p3v_sd: regulator-3p3v-sd {
 130                 compatible = "regulator-fixed";
 131                 pinctrl-names = "default";
 132                 pinctrl-0 = <&pinctrl_reg_3p3v_sd>;
 133                 vin-supply = <&reg_3p3v>;
 134                 regulator-name = "3V3_SD";
 135                 regulator-min-microvolt = <3300000>;
 136                 regulator-max-microvolt = <3300000>;
 137                 gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
 138                 startup-delay-us = <1000>;
 139                 enable-active-high;
 140                 regulator-always-on;
 141         };
 142
 143         reg_3p3v_display: regulator-3p3v-display {
 144                 compatible = "regulator-fixed";
 145                 vin-supply = <&reg_12p0v>;
 146                 regulator-name = "3V3_DISPLAY";
 147                 regulator-min-microvolt = <3300000>;
 148                 regulator-max-microvolt = <3300000>;
 149                 regulator-always-on;
 150         };
 151
 152         reg_3p3v_ssd: regulator-3p3v-ssd {
 153                 compatible = "regulator-fixed";
 154                 vin-supply = <&reg_12p0v>;
 155                 regulator-name = "3V3_SSD";
 156                 regulator-min-microvolt = <3300000>;
 157                 regulator-max-microvolt = <3300000>;
 158                 regulator-always-on;
 159         };
 160
 161         sound1 {
 162                 compatible = "simple-audio-card";
 163                 simple-audio-card,name = "Front";
 164                 simple-audio-card,format = "i2s";
 165                 simple-audio-card,bitclock-master = <&sound1_codec>;
 166                 simple-audio-card,frame-master = <&sound1_codec>;
 167                 simple-audio-card,widgets =
 168                         "Headphone", "Headphone Jack";
 169                 simple-audio-card,routing =
 170                         "Headphone Jack", "HPLEFT",
 171                         "Headphone Jack", "HPRIGHT",
 172                         "LEFTIN", "HPL",
 173                         "RIGHTIN", "HPR";
 174                 simple-audio-card,aux-devs = <&hpa1>;
 175
 176                 sound1_cpu: simple-audio-card,cpu {
 177                         sound-dai = <&ssi2>;
 178                 };
 179
 180                 sound1_codec: simple-audio-card,codec {
 181                         sound-dai = <&codec1>;
 182                         clocks = <&cs2000>;
 183                 };
 184         };
 185
 186         sound2 {
 187                 compatible = "simple-audio-card";
 188                 simple-audio-card,name = "Back";
 189                 simple-audio-card,format = "i2s";
 190                 simple-audio-card,bitclock-master = <&sound2_codec>;
 191                 simple-audio-card,frame-master = <&sound2_codec>;
 192                 simple-audio-card,widgets =
 193                         "Headphone", "Headphone Jack";
 194                 simple-audio-card,routing =
 195                         "Headphone Jack", "HPLEFT",
 196                         "Headphone Jack", "HPRIGHT",
 197                         "LEFTIN", "HPL",
 198                         "RIGHTIN", "HPR";
 199                 simple-audio-card,aux-devs = <&hpa2>;
 200
 201                 sound2_cpu: simple-audio-card,cpu {
 202                         sound-dai = <&ssi1>;
 203                 };
 204
 205                 sound2_codec: simple-audio-card,codec {
 206                         sound-dai = <&codec2>;
 207                         clocks = <&cs2000>;
 208                 };
 209         };
 210
 211         panel {
 212                 power-supply = <&reg_3p3v_display>;
 213                 status = "disabled";
 214
 215                 port {
 216                         panel_in: endpoint {
 217                                 remote-endpoint = <&lvds0_out>;
 218                         };
 219                 };
 220         };
 221
 222         disp0: disp0 {
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 compatible = "fsl,imx-parallel-display";
 226                 pinctrl-names = "default";
 227                 pinctrl-0 = <&pinctrl_disp0>;
 228                 status = "disabled";
 229
 230                 port@0 {
 231                         reg = <0>;
 232
 233                         disp0_in_0: endpoint {
 234                                 remote-endpoint = <&ipu1_di0_disp0>;
 235                         };
 236                 };
 237
 238                 port@1 {
 239                         reg = <1>;
 240
 241                         disp0_out: endpoint {
 242                                 remote-endpoint = <&tc358767_in>;
 243                         };
 244                 };
 245         };
 246
 247         cs2000_ref: cs2000-ref {
 248                 compatible = "fixed-clock";
 249                 #clock-cells = <0>;
 250                 clock-frequency = <24576000>;
 251         };
 252
 253         cs2000_in_dummy: cs2000-in-dummy {
 254                 compatible = "fixed-clock";
 255                 #clock-cells = <0>;
 256                 clock-frequency = <0>;
 257         };
 258
 259         edp_refclk: edp-refclk {
 260                 compatible = "fixed-clock";
 261                 #clock-cells = <0>;
 262                 clock-frequency = <19200000>;
 263         };
 264 };
 265
 266 &cpu0 {
 267         fsl,soc-operating-points = <
 268                 /* ARM kHz  SOC-PU uV */
 269                 1200000 1300000
 270                 996000  1275000
 271                 852000  1275000
 272                 792000  1200000
 273                 396000  1200000
 274         >;
 275 };
 276
 277 &reg_arm {
 278         vin-supply = <&sw1a_reg>;
 279 };
 280
 281 &reg_pu {
 282         vin-supply = <&sw1c_reg>;
 283 };
 284
 285 &reg_soc {
 286         vin-supply = <&sw1c_reg>;
 287 };
 288
 289 &ldb {
 290         lvds-channel@0 {
 291                 port@4 {
 292                         reg = <4>;
 293
 294                         lvds0_out: endpoint {
 295                                 remote-endpoint = <&panel_in>;
 296                         };
 297                 };
 298         };
 299 };
 300
 301 &uart1 {
 302         pinctrl-names = "default";
 303         pinctrl-0 = <&pinctrl_uart1>;
 304         status = "okay";
 305 };
 306
 307 &uart3 {
 308         pinctrl-names = "default";
 309         pinctrl-0 = <&pinctrl_uart3>;
 310         uart-has-rtscts;
 311         linux,rs485-enabled-at-boot-time;
 312         status = "okay";
 313 };
 314
 315 &uart4 {
 316         pinctrl-names = "default";
 317         pinctrl-0 = <&pinctrl_uart4>;
 318         status = "okay";
 319
 320         rave-sp {
 321                 compatible = "zii,rave-sp-rdu2";
 322                 current-speed = <1000000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <1>;
 325
 326                 watchdog {
 327                         compatible = "zii,rave-sp-watchdog";
 328                 };
 329
 330                 eeprom@a3 {
 331                         compatible = "zii,rave-sp-eeprom";
 332                         reg = <0xa3 0x4000>;
 333                         #address-cells = <1>;
 334                         #size-cells = <1>;
 335                         zii,eeprom-name = "dds-eeprom";
 336                 };
 337
 338                 eeprom@a4 {
 339                         compatible = "zii,rave-sp-eeprom";
 340                         reg = <0xa4 0x4000>;
 341                         #address-cells = <1>;
 342                         #size-cells = <1>;
 343                         zii,eeprom-name = "main-eeprom";
 344                 };
 345         };
 346 };
 347
 348 &ecspi1 {
 349         pinctrl-names = "default";
 350         pinctrl-0 = <&pinctrl_ecspi1>;
 351         cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
 352         status = "okay";
 353
 354         flash@0 {
 355                 compatible = "st,m25p128", "jedec,spi-nor";
 356                 spi-max-frequency = <20000000>;
 357                 reg = <0>;
 358         };
 359 };
 360
 361 &i2c1 {
 362         pinctrl-names = "default";
 363         pinctrl-0 = <&pinctrl_i2c1>;
 364         clock-frequency = <100000>;
 365         status = "okay";
 366
 367         codec2: codec@18 {
 368                 compatible = "ti,tlv320dac3100";
 369                 pinctrl-names = "default";
 370                 pinctrl-0 = <&pinctrl_codec2>;
 371                 reg = <0x18>;
 372                 #sound-dai-cells = <0>;
 373                 HPVDD-supply = <&reg_3p3v>;
 374                 SPRVDD-supply = <&reg_3p3v>;
 375                 SPLVDD-supply = <&reg_3p3v>;
 376                 AVDD-supply = <&reg_3p3v>;
 377                 IOVDD-supply = <&reg_3p3v>;
 378                 DVDD-supply = <&vgen4_reg>;
 379                 gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 380         };
 381
 382         accel@1c {
 383                 pinctrl-names = "default";
 384                 pinctrl-0 = <&pinctrl_accel>;
 385                 compatible = "fsl,mma8451";
 386                 reg = <0x1c>;
 387                 interrupt-parent = <&gpio1>;
 388                 interrupt-names = "int1", "int2";
 389                 interrupts = <18 IRQ_TYPE_LEVEL_LOW>, <20 IRQ_TYPE_LEVEL_LOW>;
 390         };
 391
 392         hpa2: amp@60 {
 393                 compatible = "ti,tpa6130a2";
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&pinctrl_tpa2>;
 396                 reg = <0x60>;
 397                 power-gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
 398                 Vdd-supply = <&reg_5p0v_main>;
 399         };
 400
 401         edp-bridge@68 {
 402                 compatible = "toshiba,tc358767";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&pinctrl_tc358767>;
 405                 reg = <0x68>;
 406                 shutdown-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 407                 clock-names = "ref";
 408                 clocks = <&edp_refclk>;
 409                 status = "disabled";
 410
 411                 ports {
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414
 415                         port@1 {
 416                                 reg = <1>;
 417
 418                                 tc358767_in: endpoint {
 419                                         remote-endpoint = <&disp0_out>;
 420                                 };
 421                         };
 422                 };
 423         };
 424 };
 425
 426 &i2c2 {
 427         pinctrl-names = "default";
 428         pinctrl-0 = <&pinctrl_i2c2>;
 429         clock-frequency = <100000>;
 430         status = "okay";
 431
 432         pmic@8 {
 433                 compatible = "fsl,pfuze100";
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&pinctrl_pfuze100_irq>;
 436                 reg = <0x08>;
 437                 interrupt-parent = <&gpio7>;
 438                 interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
 439
 440                 regulators {
 441                         sw1a_reg: sw1ab {
 442                                 regulator-min-microvolt = <300000>;
 443                                 regulator-max-microvolt = <1875000>;
 444                                 regulator-boot-on;
 445                                 regulator-always-on;
 446                                 regulator-ramp-delay = <6250>;
 447                         };
 448
 449                         sw1c_reg: sw1c {
 450                                 regulator-min-microvolt = <300000>;
 451                                 regulator-max-microvolt = <1875000>;
 452                                 regulator-boot-on;
 453                                 regulator-always-on;
 454                                 regulator-ramp-delay = <6250>;
 455                         };
 456
 457                         sw2_reg: sw2 {
 458                                 regulator-min-microvolt = <800000>;
 459                                 regulator-max-microvolt = <3000000>;
 460                                 regulator-boot-on;
 461                                 regulator-always-on;
 462                         };
 463
 464                         sw3a_reg: sw3a {
 465                                 regulator-min-microvolt = <400000>;
 466                                 regulator-max-microvolt = <1500000>;
 467                                 regulator-boot-on;
 468                                 regulator-always-on;
 469                         };
 470
 471                         sw3b_reg: sw3b {
 472                                 regulator-min-microvolt = <400000>;
 473                                 regulator-max-microvolt = <1500000>;
 474                                 regulator-boot-on;
 475                                 regulator-always-on;
 476                         };
 477
 478                         sw4_reg: sw4 {
 479                                 regulator-min-microvolt = <800000>;
 480                                 regulator-max-microvolt = <1800000>;
 481                                 regulator-boot-on;
 482                                 regulator-always-on;
 483                         };
 484
 485                         snvs_reg: vsnvs {
 486                                 regulator-min-microvolt = <1000000>;
 487                                 regulator-max-microvolt = <3000000>;
 488                                 regulator-boot-on;
 489                                 regulator-always-on;
 490                         };
 491
 492                         vref_reg: vrefddr {
 493                                 regulator-boot-on;
 494                                 regulator-always-on;
 495                         };
 496
 497                         vgen2_reg: vgen2 {
 498                                 regulator-min-microvolt = <1000000>;
 499                                 regulator-max-microvolt = <1500000>;
 500                                 regulator-always-on;
 501                         };
 502
 503                         vgen4_reg: vgen4 {
 504                                 regulator-min-microvolt = <1200000>;
 505                                 regulator-max-microvolt = <1800000>;
 506                                 regulator-always-on;
 507                         };
 508
 509                         vgen5_reg: vgen5 {
 510                                 regulator-min-microvolt = <1800000>;
 511                                 regulator-max-microvolt = <2500000>;
 512                                 regulator-always-on;
 513                         };
 514
 515                         vgen6_reg: vgen6 {
 516                                 regulator-min-microvolt = <1800000>;
 517                                 regulator-max-microvolt = <2800000>;
 518                                 regulator-always-on;
 519                         };
 520                 };
 521         };
 522
 523         temp-sense@48 {
 524                 compatible = "national,lm75";
 525                 reg = <0x48>;
 526         };
 527
 528         cs2000: clkgen@4e {
 529                 compatible = "cirrus,cs2000-cp";
 530                 reg = <0x4e>;
 531                 #clock-cells = <0>;
 532                 clock-names = "clk_in", "ref_clk";
 533                 clocks = <&cs2000_in_dummy>, <&cs2000_ref>;
 534                 assigned-clocks = <&cs2000>;
 535                 assigned-clock-rates = <24000000>;
 536         };
 537
 538         eeprom@54 {
 539                 compatible = "atmel,24c128";
 540                 reg = <0x54>;
 541         };
 542
 543         ds1341: rtc@68 {
 544                 compatible = "dallas,ds1341";
 545                 reg = <0x68>;
 546         };
 547 };
 548
 549 &i2c3 {
 550         pinctrl-names = "default";
 551         pinctrl-0 = <&pinctrl_i2c3>;
 552         clock-frequency = <400000>;
 553         status = "okay";
 554
 555         codec1: codec@18 {
 556                 compatible = "ti,tlv320dac3100";
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&pinctrl_codec1>;
 559                 reg = <0x18>;
 560                 #sound-dai-cells = <0>;
 561                 HPVDD-supply = <&reg_3p3v>;
 562                 SPRVDD-supply = <&reg_3p3v>;
 563                 SPLVDD-supply = <&reg_3p3v>;
 564                 AVDD-supply = <&reg_3p3v>;
 565                 IOVDD-supply = <&reg_3p3v>;
 566                 DVDD-supply = <&vgen4_reg>;
 567                 gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>;
 568         };
 569
 570         touchscreen@20 {
 571                 compatible = "syna,rmi4-i2c";
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&pinctrl_ts>;
 574                 reg = <0x20>;
 575                 interrupt-parent = <&gpio1>;
 576                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 577                 vdd-supply = <&reg_5p0v_main>;
 578                 vio-supply = <&reg_3p3v>;
 579
 580                 #address-cells = <1>;
 581                 #size-cells = <0>;
 582
 583                 rmi4-f01@1 {
 584                         reg = <0x1>;
 585                         syna,nosleep-mode = <2>;
 586                 };
 587
 588                 rmi4-f11@11 {
 589                         reg = <0x11>;
 590                         touchscreen-inverted-x;
 591                         touchscreen-swapped-x-y;
 592                         syna,sensor-type = <1>;
 593                 };
 594
 595                 rmi4-f12@12 {
 596                         reg = <0x12>;
 597                         touchscreen-inverted-x;
 598                         touchscreen-swapped-x-y;
 599                         syna,sensor-type = <1>;
 600                 };
 601         };
 602
 603         touchscreen@2a {
 604                 compatible = "eeti,egalax_ts";
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&pinctrl_ts>;
 607                 reg = <0x2a>;
 608                 interrupt-parent = <&gpio1>;
 609                 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
 610                 wakeup-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
 611                 status = "disabled";
 612         };
 613
 614         hpa1: amp@60 {
 615                 compatible = "ti,tpa6130a2";
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&pinctrl_tpa1>;
 618                 reg = <0x60>;
 619                 power-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 620                 Vdd-supply = <&reg_5p0v_main>;
 621         };
 622 };
 623
 624 &ipu1_di0_disp0 {
 625         remote-endpoint = <&disp0_in_0>;
 626 };
 627
 628 &pcie {
 629         pinctrl-names = "default";
 630         pinctrl-0 = <&pinctrl_pcie>;
 631         reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
 632         status = "okay";
 633
 634         host@0 {
 635                 reg = <0 0 0 0 0>;
 636
 637                 #address-cells = <3>;
 638                 #size-cells = <2>;
 639
 640                 i210: i210@0 {
 641                         reg = <0 0 0 0 0>;
 642                 };
 643         };
 644 };
 645
 646 &usdhc2 {
 647         pinctrl-names = "default";
 648         pinctrl-0 = <&pinctrl_usdhc2>;
 649         bus-width = <4>;
 650         cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
 651         wp-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
 652         vmmc-supply = <&reg_3p3v_sd>;
 653         vqmmc-supply = <&reg_3p3v>;
 654         no-1-8-v;
 655         no-sdio;
 656         status = "okay";
 657 };
 658
 659 &usdhc3 {
 660         pinctrl-names = "default";
 661         pinctrl-0 = <&pinctrl_usdhc3>;
 662         bus-width = <4>;
 663         cd-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
 664         wp-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
 665         vmmc-supply = <&reg_3p3v_sd>;
 666         vqmmc-supply = <&reg_3p3v>;
 667         no-1-8-v;
 668         no-sdio;
 669         status = "okay";
 670 };
 671
 672 &usdhc4 {
 673         pinctrl-names = "default";
 674         pinctrl-0 = <&pinctrl_usdhc4>;
 675         bus-width = <8>;
 676         vmmc-supply = <&reg_3p3v>;
 677         vqmmc-supply = <&reg_3p3v>;
 678         no-1-8-v;
 679         non-removable;
 680         no-sdio;
 681         no-sd;
 682         status = "okay";
 683 };
 684
 685 &sata {
 686         target-supply = <&reg_3p3v_ssd>;
 687         status = "okay";
 688 };
 689
 690 &fec {
 691         pinctrl-names = "default";
 692         pinctrl-0 = <&pinctrl_enet>;
 693         phy-mode = "rmii";
 694         phy-handle = <&phy>;
 695         phy-reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
 696         phy-reset-duration = <100>;
 697         phy-supply = <&reg_3p3v>;
 698         status = "okay";
 699
 700         mdio {
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 status = "okay";
 704
 705                 switch: switch@0 {
 706                         compatible = "marvell,mv88e6085";
 707                         pinctrl-0 = <&pinctrl_switch_irq>;
 708                         pinctrl-names = "default";
 709                         reg = <0>;
 710                         dsa,member = <0 0>;
 711                         eeprom-length = <512>;
 712                         interrupt-parent = <&gpio6>;
 713                         interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
 714                         interrupt-controller;
 715                         #interrupt-cells = <2>;
 716
 717                         ports {
 718                                 #address-cells = <1>;
 719                                 #size-cells = <0>;
 720
 721                                 port@0 {
 722                                         reg = <0>;
 723                                         label = "gigabit_proc";
 724                                         phy-handle = <&switchphy0>;
 725                                 };
 726
 727                                 port@1 {
 728                                         reg = <1>;
 729                                         label = "netaux";
 730                                         phy-handle = <&switchphy1>;
 731                                 };
 732
 733                                 port@2 {
 734                                         reg = <2>;
 735                                         label = "cpu";
 736                                         ethernet = <&fec>;
 737
 738                                         fixed-link {
 739                                                 speed = <100>;
 740                                                 full-duplex;
 741                                         };
 742                                 };
 743
 744                                 port@3 {
 745                                         reg = <3>;
 746                                         label = "netright";
 747                                         phy-handle = <&switchphy3>;
 748                                 };
 749
 750                                 port@4 {
 751                                         reg = <4>;
 752                                         label = "netleft";
 753                                         phy-handle = <&switchphy4>;
 754                                 };
 755                         };
 756
 757                         mdio {
 758                                 #address-cells = <1>;
 759                                 #size-cells = <0>;
 760
 761                                 switchphy0: switchphy@0 {
 762                                         reg = <0>;
 763                                         interrupt-parent = <&switch>;
 764                                         interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
 765                                 };
 766
 767                                 switchphy1: switchphy@1 {
 768                                         reg = <1>;
 769                                         interrupt-parent = <&switch>;
 770                                         interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
 771                                 };
 772
 773                                 switchphy2: switchphy@2 {
 774                                         reg = <2>;
 775                                         interrupt-parent = <&switch>;
 776                                         interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
 777                                 };
 778
 779                                 switchphy3: switchphy@3 {
 780                                         reg = <3>;
 781                                         interrupt-parent = <&switch>;
 782                                         interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
 783                                 };
 784
 785                                 switchphy4: switchphy@4 {
 786                                         reg = <4>;
 787                                         interrupt-parent = <&switch>;
 788                                         interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
 789                                 };
 790                         };
 791                 };
 792         };
 793 };
 794
 795 &usbh1 {
 796         vbus-supply = <&reg_5p0v_main>;
 797         disable-over-current;
 798         status = "okay";
 799 };
 800
 801 &usbotg {
 802         vbus-supply = <&reg_5p0v_user_usb>;
 803         disable-over-current;
 804         dr_mode = "host";
 805         status = "okay";
 806 };
 807
 808 &ssi1 {
 809         status = "okay";
 810 };
 811
 812 &ssi2 {
 813         status = "okay";
 814 };
 815
 816 &audmux {
 817         pinctrl-names = "default";
 818         pinctrl-0 = <&pinctrl_audmux>;
 819         status = "okay";
 820
 821         ssi1 {
 822                 fsl,audmux-port = <0>;
 823                 fsl,port-config = <
 824                         (IMX_AUDMUX_V2_PTCR_SYN |
 825                          IMX_AUDMUX_V2_PTCR_TFSEL(2) |
 826                          IMX_AUDMUX_V2_PTCR_TCSEL(2) |
 827                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 828                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 829                         IMX_AUDMUX_V2_PDCR_RXDSEL(2)
 830                 >;
 831         };
 832
 833         aud3 {
 834                 fsl,audmux-port = <2>;
 835                 fsl,port-config = <
 836                         IMX_AUDMUX_V2_PTCR_SYN
 837                         IMX_AUDMUX_V2_PDCR_RXDSEL(0)
 838                 >;
 839         };
 840
 841         ssi2 {
 842                 fsl,audmux-port = <1>;
 843                 fsl,port-config = <
 844                         (IMX_AUDMUX_V2_PTCR_SYN |
 845                          IMX_AUDMUX_V2_PTCR_TFSEL(4) |
 846                          IMX_AUDMUX_V2_PTCR_TCSEL(4) |
 847                          IMX_AUDMUX_V2_PTCR_TFSDIR |
 848                          IMX_AUDMUX_V2_PTCR_TCLKDIR)
 849                         IMX_AUDMUX_V2_PDCR_RXDSEL(4)
 850                 >;
 851         };
 852
 853         aud5 {
 854                 fsl,audmux-port = <4>;
 855                 fsl,port-config = <
 856                         IMX_AUDMUX_V2_PTCR_SYN
 857                         IMX_AUDMUX_V2_PDCR_RXDSEL(1)
 858                 >;
 859         };
 860 };
 861
 862 &wdog1 {
 863         status = "disabled";
 864 };
 865
 866 &iomuxc {
 867         pinctrl_accel: accelgrp {
 868                 fsl,pins = <
 869                         MX6QDL_PAD_SD1_CMD__GPIO1_IO18          0x4001b000
 870                         MX6QDL_PAD_SD1_CLK__GPIO1_IO20          0x4001b000
 871                 >;
 872         };
 873
 874         pinctrl_audmux: audmuxgrp {
 875                 fsl,pins = <
 876                         MX6QDL_PAD_KEY_COL0__AUD5_TXC           0x130b0
 877                         MX6QDL_PAD_KEY_ROW0__AUD5_TXD           0x130b0
 878                         MX6QDL_PAD_KEY_COL1__AUD5_TXFS          0x130b0
 879                         MX6QDL_PAD_CSI0_DAT4__AUD3_TXC          0x130b0
 880                         MX6QDL_PAD_CSI0_DAT5__AUD3_TXD          0x130b0
 881                         MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS         0x130b0
 882                 >;
 883         };
 884
 885         pinctrl_codec1: dac1grp {
 886                 fsl,pins = <
 887                         MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x40000038
 888                 >;
 889         };
 890
 891         pinctrl_codec2: dac2grp {
 892                 fsl,pins = <
 893                         MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x40000038
 894                 >;
 895         };
 896
 897         pinctrl_disp0: disp0grp {
 898                 fsl,pins = <
 899                         MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x100f9
 900                         MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x100f9
 901                         MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x100f9
 902                         MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x100f9
 903                         MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x100f9
 904                         MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x100f9
 905                         MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x100f9
 906                         MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x100f9
 907                         MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x100f9
 908                         MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x100f9
 909                         MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x100f9
 910                         MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x100f9
 911                         MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x100f9
 912                         MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x100f9
 913                         MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x100f9
 914                         MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x100f9
 915                         MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x100f9
 916                         MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x100f9
 917                         MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x100f9
 918                         MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x100f9
 919                         MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x100f9
 920                         MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x100f9
 921                         MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18  0x100f9
 922                         MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19  0x100f9
 923                         MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20  0x100f9
 924                         MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21  0x100f9
 925                         MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22  0x100f9
 926                         MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23  0x100f9
 927                 >;
 928         };
 929
 930         pinctrl_ecspi1: ecspi1grp {
 931                 fsl,pins = <
 932                         MX6QDL_PAD_EIM_D17__ECSPI1_MISO         0x100b1
 933                         MX6QDL_PAD_EIM_D18__ECSPI1_MOSI         0x100b1
 934                         MX6QDL_PAD_EIM_D16__ECSPI1_SCLK         0x100b1
 935                         MX6QDL_PAD_EIM_EB2__GPIO2_IO30          0x1b0b1
 936                 >;
 937         };
 938
 939         pinctrl_enet: enetgrp {
 940                 fsl,pins = <
 941                         MX6QDL_PAD_ENET_MDC__ENET_MDC           0x000b1
 942                         MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x100b1
 943                         MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN      0x100f5
 944                         MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN       0x100f5
 945                         MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0     0x100c0
 946                         MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1     0x100c0
 947                         MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0     0x100f5
 948                         MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1     0x100f5
 949                         MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x40010040
 950                         MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER       0x100b0
 951                         MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23     0x1b0b0
 952                 >;
 953         };
 954
 955         pinctrl_i2c1: i2c1grp {
 956                 fsl,pins = <
 957                         MX6QDL_PAD_CSI0_DAT8__I2C1_SDA          0x4001b8b1
 958                         MX6QDL_PAD_CSI0_DAT9__I2C1_SCL          0x4001b8b1
 959                 >;
 960         };
 961
 962         pinctrl_i2c2: i2c2grp {
 963                 fsl,pins = <
 964                         MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 965                         MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 966                 >;
 967         };
 968
 969         pinctrl_i2c3: i2c3grp {
 970                 fsl,pins = <
 971                         MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 972                         MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 973                 >;
 974         };
 975
 976         pinctrl_mdio1: bitbangmdiogrp {
 977                 fsl,pins = <
 978                         /* Bitbang MDIO for DEB Switch */
 979                         MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05       0x4001b030
 980                         MX6QDL_PAD_CSI0_DAT18__GPIO6_IO04       0x40018830
 981                 >;
 982         };
 983
 984         pinctrl_pcie: pciegrp {
 985                 fsl,pins = <
 986                         MX6QDL_PAD_GPIO_17__GPIO7_IO12          0x10038
 987                 >;
 988         };
 989
 990         pinctrl_pfuze100_irq: pfuze100grp {
 991                 fsl,pins = <
 992                         MX6QDL_PAD_GPIO_18__GPIO7_IO13          0x40010000
 993                 >;
 994         };
 995
 996         pinctrl_reg_3p3v_sd: mmcsupply1grp {
 997                 fsl,pins = <
 998                         MX6QDL_PAD_SD3_RST__GPIO7_IO08          0x858
 999                 >;
1000         };
1001
1002         pinctrl_reg_user_usb: usbotggrp {
1003                 fsl,pins = <
1004                         MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x40000038
1005                 >;
1006         };
1007
1008         pinctrl_rmii_phy_irq: phygrp {
1009                 fsl,pins = <
1010                         MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x40010000
1011                 >;
1012         };
1013
1014         pinctrl_switch_irq: switchgrp {
1015                 fsl,pins = <
1016                         MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03       0x4001b000
1017                 >;
1018         };
1019
1020         pinctrl_tc358767: tc358767grp {
1021                 fsl,pins = <
1022                         MX6QDL_PAD_GPIO_9__GPIO1_IO09           0x10
1023                 >;
1024         };
1025
1026         pinctrl_tpa1: tpa6130-1grp {
1027                 fsl,pins = <
1028                         MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x40000038
1029                 >;
1030         };
1031
1032         pinctrl_tpa2: tpa6130-2grp {
1033                 fsl,pins = <
1034                         MX6QDL_PAD_GPIO_5__GPIO1_IO05           0x40000038
1035                 >;
1036         };
1037
1038         pinctrl_ts: tsgrp {
1039                 fsl,pins = <
1040                         MX6QDL_PAD_GPIO_8__GPIO1_IO08           0x1b0b0
1041                         MX6QDL_PAD_GPIO_7__GPIO1_IO07           0x1b0b0
1042                 >;
1043         };
1044
1045         pinctrl_uart1: uart1grp {
1046                 fsl,pins = <
1047                         MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA    0x1b0b1
1048                         MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA    0x1b0b1
1049                 >;
1050         };
1051
1052         pinctrl_uart3: uart3grp {
1053                 fsl,pins = <
1054                         MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
1055                         MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
1056                         MX6QDL_PAD_EIM_D31__UART3_RTS_B         0x1b0b1
1057                 >;
1058         };
1059
1060         pinctrl_uart4: uart4grp {
1061                 fsl,pins = <
1062                         MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA    0x1b0b1
1063                         MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA    0x1b0b1
1064                 >;
1065         };
1066
1067         pinctrl_usdhc2: usdhc2grp {
1068                 fsl,pins = <
1069                         MX6QDL_PAD_SD2_CMD__SD2_CMD             0x10059
1070                         MX6QDL_PAD_SD2_CLK__SD2_CLK             0x10069
1071                         MX6QDL_PAD_SD2_DAT0__SD2_DATA0          0x17059
1072                         MX6QDL_PAD_SD2_DAT1__SD2_DATA1          0x17059
1073                         MX6QDL_PAD_SD2_DAT2__SD2_DATA2          0x17059
1074                         MX6QDL_PAD_SD2_DAT3__SD2_DATA3          0x17059
1075                         MX6QDL_PAD_NANDF_D3__GPIO2_IO03         0x40010040
1076                         MX6QDL_PAD_NANDF_D2__GPIO2_IO02         0x40010040
1077                 >;
1078         };
1079
1080         pinctrl_usdhc3: usdhc3grp {
1081                 fsl,pins = <
1082                         MX6QDL_PAD_SD3_CMD__SD3_CMD             0x10059
1083                         MX6QDL_PAD_SD3_CLK__SD3_CLK             0x10069
1084                         MX6QDL_PAD_SD3_DAT0__SD3_DATA0          0x17059
1085                         MX6QDL_PAD_SD3_DAT1__SD3_DATA1          0x17059
1086                         MX6QDL_PAD_SD3_DAT2__SD3_DATA2          0x17059
1087                         MX6QDL_PAD_SD3_DAT3__SD3_DATA3          0x17059
1088                         MX6QDL_PAD_NANDF_D1__GPIO2_IO01         0x40010040
1089                         MX6QDL_PAD_NANDF_D0__GPIO2_IO00         0x40010040
1090
1091                 >;
1092         };
1093
1094         pinctrl_usdhc4: usdhc4grp {
1095                 fsl,pins = <
1096                         MX6QDL_PAD_SD4_CMD__SD4_CMD             0x17059
1097                         MX6QDL_PAD_SD4_CLK__SD4_CLK             0x10059
1098                         MX6QDL_PAD_SD4_DAT0__SD4_DATA0          0x17059
1099                         MX6QDL_PAD_SD4_DAT1__SD4_DATA1          0x17059
1100                         MX6QDL_PAD_SD4_DAT2__SD4_DATA2          0x17059
1101                         MX6QDL_PAD_SD4_DAT3__SD4_DATA3          0x17059
1102                         MX6QDL_PAD_SD4_DAT4__SD4_DATA4          0x17059
1103                         MX6QDL_PAD_SD4_DAT5__SD4_DATA5          0x17059
1104                         MX6QDL_PAD_SD4_DAT6__SD4_DATA6          0x17059
1105                         MX6QDL_PAD_SD4_DAT7__SD4_DATA7          0x17059
1106                         MX6QDL_PAD_NANDF_ALE__SD4_RESET         0x1b0b1
1107                 >;
1108         };
1109 };