arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Device Tree Source for OMAP34XX/OMAP36XX clock data
   4  *
   5  * Copyright (C) 2013 Texas Instruments, Inc.
   6  */
   7 &cm_clocks {
   8         security_l4_ick2: security_l4_ick2 {
   9                 #clock-cells = <0>;
  10                 compatible = "fixed-factor-clock";
  11                 clocks = <&l4_ick>;
  12                 clock-mult = <1>;
  13                 clock-div = <1>;
  14         };
  15
  16         clock@a14 {
  17                 compatible = "ti,clksel";
  18                 reg = <0xa14>;
  19                 #clock-cells = <2>;
  20                 #address-cells = <0>;
  21
  22                 aes1_ick: clock-aes1-ick {
  23                         #clock-cells = <0>;
  24                         compatible = "ti,omap3-interface-clock";
  25                         clock-output-names = "aes1_ick";
  26                         clocks = <&security_l4_ick2>;
  27                         ti,bit-shift = <3>;
  28                 };
  29
  30                 rng_ick: clock-rng-ick {
  31                         #clock-cells = <0>;
  32                         compatible = "ti,omap3-interface-clock";
  33                         clock-output-names = "rng_ick";
  34                         clocks = <&security_l4_ick2>;
  35                         ti,bit-shift = <2>;
  36                 };
  37
  38                 sha11_ick: clock-sha11-ick {
  39                         #clock-cells = <0>;
  40                         compatible = "ti,omap3-interface-clock";
  41                         clock-output-names = "sha11_ick";
  42                         clocks = <&security_l4_ick2>;
  43                         ti,bit-shift = <1>;
  44                 };
  45
  46                 des1_ick: clock-des1-ick {
  47                         #clock-cells = <0>;
  48                         compatible = "ti,omap3-interface-clock";
  49                         clock-output-names = "des1_ick";
  50                         clocks = <&security_l4_ick2>;
  51                         ti,bit-shift = <0>;
  52                 };
  53
  54                 pka_ick: clock-pka-ick {
  55                         #clock-cells = <0>;
  56                         compatible = "ti,omap3-interface-clock";
  57                         clock-output-names = "pka_ick";
  58                         clocks = <&security_l3_ick>;
  59                         ti,bit-shift = <4>;
  60                 };
  61         };
  62
  63         cam_mclk: cam_mclk@f00 {
  64                 #clock-cells = <0>;
  65                 compatible = "ti,gate-clock";
  66                 clocks = <&dpll4_m5x2_ck>;
  67                 ti,bit-shift = <0>;
  68                 reg = <0x0f00>;
  69                 ti,set-rate-parent;
  70         };
  71
  72         cam_ick: cam_ick@f10 {
  73                 #clock-cells = <0>;
  74                 compatible = "ti,omap3-no-wait-interface-clock";
  75                 clocks = <&l4_ick>;
  76                 reg = <0x0f10>;
  77                 ti,bit-shift = <0>;
  78         };
  79
  80         csi2_96m_fck: csi2_96m_fck@f00 {
  81                 #clock-cells = <0>;
  82                 compatible = "ti,gate-clock";
  83                 clocks = <&core_96m_fck>;
  84                 reg = <0x0f00>;
  85                 ti,bit-shift = <1>;
  86         };
  87
  88         security_l3_ick: security_l3_ick {
  89                 #clock-cells = <0>;
  90                 compatible = "fixed-factor-clock";
  91                 clocks = <&l3_ick>;
  92                 clock-mult = <1>;
  93                 clock-div = <1>;
  94         };
  95
  96         clock@a10 {
  97                 compatible = "ti,clksel";
  98                 reg = <0xa10>;
  99                 #clock-cells = <2>;
 100                 #address-cells = <0>;
 101
 102                 icr_ick: clock-icr-ick {
 103                         #clock-cells = <0>;
 104                         compatible = "ti,omap3-interface-clock";
 105                         clock-output-names = "icr_ick";
 106                         clocks = <&core_l4_ick>;
 107                         ti,bit-shift = <29>;
 108                 };
 109
 110                 des2_ick: clock-des2-ick {
 111                         #clock-cells = <0>;
 112                         compatible = "ti,omap3-interface-clock";
 113                         clock-output-names = "des2_ick";
 114                         clocks = <&core_l4_ick>;
 115                         ti,bit-shift = <26>;
 116                 };
 117
 118                 mspro_ick: clock-mspro-ick {
 119                         #clock-cells = <0>;
 120                         compatible = "ti,omap3-interface-clock";
 121                         clock-output-names = "mspro_ick";
 122                         clocks = <&core_l4_ick>;
 123                         ti,bit-shift = <23>;
 124                 };
 125
 126                 mailboxes_ick: clock-mailboxes-ick {
 127                         #clock-cells = <0>;
 128                         compatible = "ti,omap3-interface-clock";
 129                         clock-output-names = "mailboxes_ick";
 130                         clocks = <&core_l4_ick>;
 131                         ti,bit-shift = <7>;
 132                 };
 133
 134                 sad2d_ick: clock-sad2d-ick {
 135                         #clock-cells = <0>;
 136                         compatible = "ti,omap3-interface-clock";
 137                         clock-output-names = "sad2d_ick";
 138                         clocks = <&l3_ick>;
 139                         ti,bit-shift = <3>;
 140                 };
 141         };
 142
 143         ssi_l4_ick: ssi_l4_ick {
 144                 #clock-cells = <0>;
 145                 compatible = "fixed-factor-clock";
 146                 clocks = <&l4_ick>;
 147                 clock-mult = <1>;
 148                 clock-div = <1>;
 149         };
 150
 151         clock@c00 {
 152                 compatible = "ti,clksel";
 153                 reg = <0xc00>;
 154                 #clock-cells = <2>;
 155                 #address-cells = <0>;
 156
 157                 sr1_fck: clock-sr1-fck {
 158                         #clock-cells = <0>;
 159                         compatible = "ti,wait-gate-clock";
 160                         clock-output-names = "sr1_fck";
 161                         clocks = <&sys_ck>;
 162                         ti,bit-shift = <6>;
 163                 };
 164
 165                 sr2_fck: clock-sr2-fck {
 166                         #clock-cells = <0>;
 167                         compatible = "ti,wait-gate-clock";
 168                         clock-output-names = "sr2_fck";
 169                         clocks = <&sys_ck>;
 170                         ti,bit-shift = <7>;
 171                 };
 172         };
 173
 174         sr_l4_ick: sr_l4_ick {
 175                 #clock-cells = <0>;
 176                 compatible = "fixed-factor-clock";
 177                 clocks = <&l4_ick>;
 178                 clock-mult = <1>;
 179                 clock-div = <1>;
 180         };
 181
 182         dpll2_fck: dpll2_fck@40 {
 183                 #clock-cells = <0>;
 184                 compatible = "ti,divider-clock";
 185                 clocks = <&core_ck>;
 186                 ti,bit-shift = <19>;
 187                 ti,max-div = <7>;
 188                 reg = <0x0040>;
 189                 ti,index-starts-at-one;
 190         };
 191
 192         dpll2_ck: dpll2_ck@4 {
 193                 #clock-cells = <0>;
 194                 compatible = "ti,omap3-dpll-clock";
 195                 clocks = <&sys_ck>, <&dpll2_fck>;
 196                 reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
 197                 ti,low-power-stop;
 198                 ti,lock;
 199                 ti,low-power-bypass;
 200         };
 201
 202         dpll2_m2_ck: dpll2_m2_ck@44 {
 203                 #clock-cells = <0>;
 204                 compatible = "ti,divider-clock";
 205                 clocks = <&dpll2_ck>;
 206                 ti,max-div = <31>;
 207                 reg = <0x0044>;
 208                 ti,index-starts-at-one;
 209         };
 210
 211         iva2_ck: iva2_ck@0 {
 212                 #clock-cells = <0>;
 213                 compatible = "ti,wait-gate-clock";
 214                 clocks = <&dpll2_m2_ck>;
 215                 reg = <0x0000>;
 216                 ti,bit-shift = <0>;
 217         };
 218
 219         clock@a00 {
 220                 compatible = "ti,clksel";
 221                 reg = <0xa00>;
 222                 #clock-cells = <2>;
 223                 #address-cells = <0>;
 224
 225                 modem_fck: clock-modem-fck {
 226                         #clock-cells = <0>;
 227                         compatible = "ti,omap3-interface-clock";
 228                         clock-output-names = "modem_fck";
 229                         clocks = <&sys_ck>;
 230                         ti,bit-shift = <31>;
 231                 };
 232
 233                 mspro_fck: clock-mspro-fck {
 234                         #clock-cells = <0>;
 235                         compatible = "ti,wait-gate-clock";
 236                         clock-output-names = "mspro_fck";
 237                         clocks = <&core_96m_fck>;
 238                         ti,bit-shift = <23>;
 239                 };
 240         };
 241
 242         /* CM_ICLKEN3_CORE */
 243         clock@a18 {
 244                 compatible = "ti,clksel";
 245                 reg = <0xa18>;
 246                 #clock-cells = <2>;
 247                 #address-cells = <0>;
 248
 249                 mad2d_ick: clock-mad2d-ick {
 250                         #clock-cells = <0>;
 251                         compatible = "ti,omap3-interface-clock";
 252                         clock-output-names = "mad2d_ick";
 253                         clocks = <&l3_ick>;
 254                         ti,bit-shift = <3>;
 255                 };
 256         };
 257
 258 };
 259
 260 &cm_clockdomains {
 261         cam_clkdm: cam_clkdm {
 262                 compatible = "ti,clockdomain";
 263                 clocks = <&cam_ick>, <&csi2_96m_fck>;
 264         };
 265
 266         iva2_clkdm: iva2_clkdm {
 267                 compatible = "ti,clockdomain";
 268                 clocks = <&iva2_ck>;
 269         };
 270
 271         dpll2_clkdm: dpll2_clkdm {
 272                 compatible = "ti,clockdomain";
 273                 clocks = <&dpll2_ck>;
 274         };
 275
 276         wkup_clkdm: wkup_clkdm {
 277                 compatible = "ti,clockdomain";
 278                 clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
 279                          <&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
 280                          <&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
 281         };
 282
 283         d2d_clkdm: d2d_clkdm {
 284                 compatible = "ti,clockdomain";
 285                 clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
 286         };
 287
 288         core_l4_clkdm: core_l4_clkdm {
 289                 compatible = "ti,clockdomain";
 290                 clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
 291                          <&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
 292                          <&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
 293                          <&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
 294                          <&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
 295                          <&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
 296                          <&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
 297                          <&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
 298                          <&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
 299                          <&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
 300                          <&rng_ick>, <&mspro_fck>;
 301         };
 302 };