arch/arm/boot/dts/omap5.dtsi

   1 /*
   2  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  * Based on "omap4.dtsi"
   8  */
   9
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/interrupt-controller/arm-gic.h>
  12 #include <dt-bindings/pinctrl/omap.h>
  13
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         compatible = "ti,omap5";
  21         interrupt-parent = <&gic>;
  22
  23         aliases {
  24                 i2c0 = &i2c1;
  25                 i2c1 = &i2c2;
  26                 i2c2 = &i2c3;
  27                 i2c3 = &i2c4;
  28                 i2c4 = &i2c5;
  29                 serial0 = &uart1;
  30                 serial1 = &uart2;
  31                 serial2 = &uart3;
  32                 serial3 = &uart4;
  33                 serial4 = &uart5;
  34                 serial5 = &uart6;
  35         };
  36
  37         cpus {
  38                 #address-cells = <1>;
  39                 #size-cells = <0>;
  40
  41                 cpu0: cpu@0 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x0>;
  45
  46                         operating-points = <
  47                                 /* kHz    uV */
  48                                 1000000 1060000
  49                                 1500000 1250000
  50                         >;
  51
  52                         clocks = <&dpll_mpu_ck>;
  53                         clock-names = "cpu";
  54
  55                         clock-latency = <300000>; /* From omap-cpufreq driver */
  56
  57                         /* cooling options */
  58                         cooling-min-level = <0>;
  59                         cooling-max-level = <2>;
  60                         #cooling-cells = <2>; /* min followed by max */
  61                 };
  62                 cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <0x1>;
  66                 };
  67         };
  68
  69         thermal-zones {
  70                 #include "omap4-cpu-thermal.dtsi"
  71                 #include "omap5-gpu-thermal.dtsi"
  72                 #include "omap5-core-thermal.dtsi"
  73         };
  74
  75         timer {
  76                 compatible = "arm,armv7-timer";
  77                 /* PPI secure/nonsecure IRQ */
  78                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  79                              <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  80                              <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
  81                              <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
  82         };
  83
  84         pmu {
  85                 compatible = "arm,cortex-a15-pmu";
  86                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
  88         };
  89
  90         gic: interrupt-controller@48211000 {
  91                 compatible = "arm,cortex-a15-gic";
  92                 interrupt-controller;
  93                 #interrupt-cells = <3>;
  94                 reg = <0x48211000 0x1000>,
  95                       <0x48212000 0x1000>,
  96                       <0x48214000 0x2000>,
  97                       <0x48216000 0x2000>;
  98         };
  99
 100         /*
 101          * The soc node represents the soc top level view. It is used for IPs
 102          * that are not memory mapped in the MPU view or for the MPU itself.
 103          */
 104         soc {
 105                 compatible = "ti,omap-infra";
 106                 mpu {
 107                         compatible = "ti,omap4-mpu";
 108                         ti,hwmods = "mpu";
 109                         sram = <&ocmcram>;
 110                 };
 111         };
 112
 113         /*
 114          * XXX: Use a flat representation of the OMAP3 interconnect.
 115          * The real OMAP interconnect network is quite complex.
 116          * Since it will not bring real advantage to represent that in DT for
 117          * the moment, just use a fake OCP bus entry to represent the whole bus
 118          * hierarchy.
 119          */
 120         ocp {
 121                 compatible = "ti,omap4-l3-noc", "simple-bus";
 122                 #address-cells = <1>;
 123                 #size-cells = <1>;
 124                 ranges;
 125                 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
 126                 reg = <0x44000000 0x2000>,
 127                       <0x44800000 0x3000>,
 128                       <0x45000000 0x4000>;
 129                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 130                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 131
 132                 prm: prm@4ae06000 {
 133                         compatible = "ti,omap5-prm";
 134                         reg = <0x4ae06000 0x3000>;
 135                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 136
 137                         prm_clocks: clocks {
 138                                 #address-cells = <1>;
 139                                 #size-cells = <0>;
 140                         };
 141
 142                         prm_clockdomains: clockdomains {
 143                         };
 144                 };
 145
 146                 cm_core_aon: cm_core_aon@4a004000 {
 147                         compatible = "ti,omap5-cm-core-aon";
 148                         reg = <0x4a004000 0x2000>;
 149
 150                         cm_core_aon_clocks: clocks {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153                         };
 154
 155                         cm_core_aon_clockdomains: clockdomains {
 156                         };
 157                 };
 158
 159                 scrm: scrm@4ae0a000 {
 160                         compatible = "ti,omap5-scrm";
 161                         reg = <0x4ae0a000 0x2000>;
 162
 163                         scrm_clocks: clocks {
 164                                 #address-cells = <1>;
 165                                 #size-cells = <0>;
 166                         };
 167
 168                         scrm_clockdomains: clockdomains {
 169                         };
 170                 };
 171
 172                 cm_core: cm_core@4a008000 {
 173                         compatible = "ti,omap5-cm-core";
 174                         reg = <0x4a008000 0x3000>;
 175
 176                         cm_core_clocks: clocks {
 177                                 #address-cells = <1>;
 178                                 #size-cells = <0>;
 179                         };
 180
 181                         cm_core_clockdomains: clockdomains {
 182                         };
 183                 };
 184
 185                 counter32k: counter@4ae04000 {
 186                         compatible = "ti,omap-counter32k";
 187                         reg = <0x4ae04000 0x40>;
 188                         ti,hwmods = "counter_32k";
 189                 };
 190
 191                 omap5_pmx_core: pinmux@4a002840 {
 192                         compatible = "ti,omap4-padconf", "pinctrl-single";
 193                         reg = <0x4a002840 0x01b6>;
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         pinctrl-single,register-width = <16>;
 197                         pinctrl-single,function-mask = <0x7fff>;
 198                 };
 199                 omap5_pmx_wkup: pinmux@4ae0c840 {
 200                         compatible = "ti,omap4-padconf", "pinctrl-single";
 201                         reg = <0x4ae0c840 0x0038>;
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204                         pinctrl-single,register-width = <16>;
 205                         pinctrl-single,function-mask = <0x7fff>;
 206                 };
 207
 208                 omap5_padconf_global: tisyscon@4a002da0 {
 209                         compatible = "syscon";
 210                         reg = <0x4A002da0 0xec>;
 211                 };
 212
 213                 pbias_regulator: pbias_regulator {
 214                         compatible = "ti,pbias-omap";
 215                         reg = <0x60 0x4>;
 216                         syscon = <&omap5_padconf_global>;
 217                         pbias_mmc_reg: pbias_mmc_omap5 {
 218                                 regulator-name = "pbias_mmc_omap5";
 219                                 regulator-min-microvolt = <1800000>;
 220                                 regulator-max-microvolt = <3000000>;
 221                         };
 222                 };
 223
 224                 ocmcram: ocmcram@40300000 {
 225                         compatible = "mmio-sram";
 226                         reg = <0x40300000 0x20000>; /* 128k */
 227                 };
 228
 229                 sdma: dma-controller@4a056000 {
 230                         compatible = "ti,omap4430-sdma";
 231                         reg = <0x4a056000 0x1000>;
 232                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
 233                                      <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
 234                                      <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
 235                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 236                         #dma-cells = <1>;
 237                         #dma-channels = <32>;
 238                         #dma-requests = <127>;
 239                 };
 240
 241                 gpio1: gpio@4ae10000 {
 242                         compatible = "ti,omap4-gpio";
 243                         reg = <0x4ae10000 0x200>;
 244                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 245                         ti,hwmods = "gpio1";
 246                         ti,gpio-always-on;
 247                         gpio-controller;
 248                         #gpio-cells = <2>;
 249                         interrupt-controller;
 250                         #interrupt-cells = <2>;
 251                 };
 252
 253                 gpio2: gpio@48055000 {
 254                         compatible = "ti,omap4-gpio";
 255                         reg = <0x48055000 0x200>;
 256                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 257                         ti,hwmods = "gpio2";
 258                         gpio-controller;
 259                         #gpio-cells = <2>;
 260                         interrupt-controller;
 261                         #interrupt-cells = <2>;
 262                 };
 263
 264                 gpio3: gpio@48057000 {
 265                         compatible = "ti,omap4-gpio";
 266                         reg = <0x48057000 0x200>;
 267                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 268                         ti,hwmods = "gpio3";
 269                         gpio-controller;
 270                         #gpio-cells = <2>;
 271                         interrupt-controller;
 272                         #interrupt-cells = <2>;
 273                 };
 274
 275                 gpio4: gpio@48059000 {
 276                         compatible = "ti,omap4-gpio";
 277                         reg = <0x48059000 0x200>;
 278                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 279                         ti,hwmods = "gpio4";
 280                         gpio-controller;
 281                         #gpio-cells = <2>;
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                 };
 285
 286                 gpio5: gpio@4805b000 {
 287                         compatible = "ti,omap4-gpio";
 288                         reg = <0x4805b000 0x200>;
 289                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 290                         ti,hwmods = "gpio5";
 291                         gpio-controller;
 292                         #gpio-cells = <2>;
 293                         interrupt-controller;
 294                         #interrupt-cells = <2>;
 295                 };
 296
 297                 gpio6: gpio@4805d000 {
 298                         compatible = "ti,omap4-gpio";
 299                         reg = <0x4805d000 0x200>;
 300                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 301                         ti,hwmods = "gpio6";
 302                         gpio-controller;
 303                         #gpio-cells = <2>;
 304                         interrupt-controller;
 305                         #interrupt-cells = <2>;
 306                 };
 307
 308                 gpio7: gpio@48051000 {
 309                         compatible = "ti,omap4-gpio";
 310                         reg = <0x48051000 0x200>;
 311                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 312                         ti,hwmods = "gpio7";
 313                         gpio-controller;
 314                         #gpio-cells = <2>;
 315                         interrupt-controller;
 316                         #interrupt-cells = <2>;
 317                 };
 318
 319                 gpio8: gpio@48053000 {
 320                         compatible = "ti,omap4-gpio";
 321                         reg = <0x48053000 0x200>;
 322                         interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 323                         ti,hwmods = "gpio8";
 324                         gpio-controller;
 325                         #gpio-cells = <2>;
 326                         interrupt-controller;
 327                         #interrupt-cells = <2>;
 328                 };
 329
 330                 gpmc: gpmc@50000000 {
 331                         compatible = "ti,omap4430-gpmc";
 332                         reg = <0x50000000 0x1000>;
 333                         #address-cells = <2>;
 334                         #size-cells = <1>;
 335                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 336                         gpmc,num-cs = <8>;
 337                         gpmc,num-waitpins = <4>;
 338                         ti,hwmods = "gpmc";
 339                         clocks = <&l3_iclk_div>;
 340                         clock-names = "fck";
 341                 };
 342
 343                 i2c1: i2c@48070000 {
 344                         compatible = "ti,omap4-i2c";
 345                         reg = <0x48070000 0x100>;
 346                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 347                         #address-cells = <1>;
 348                         #size-cells = <0>;
 349                         ti,hwmods = "i2c1";
 350                 };
 351
 352                 i2c2: i2c@48072000 {
 353                         compatible = "ti,omap4-i2c";
 354                         reg = <0x48072000 0x100>;
 355                         interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         ti,hwmods = "i2c2";
 359                 };
 360
 361                 i2c3: i2c@48060000 {
 362                         compatible = "ti,omap4-i2c";
 363                         reg = <0x48060000 0x100>;
 364                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 365                         #address-cells = <1>;
 366                         #size-cells = <0>;
 367                         ti,hwmods = "i2c3";
 368                 };
 369
 370                 i2c4: i2c@4807a000 {
 371                         compatible = "ti,omap4-i2c";
 372                         reg = <0x4807a000 0x100>;
 373                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         ti,hwmods = "i2c4";
 377                 };
 378
 379                 i2c5: i2c@4807c000 {
 380                         compatible = "ti,omap4-i2c";
 381                         reg = <0x4807c000 0x100>;
 382                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 383                         #address-cells = <1>;
 384                         #size-cells = <0>;
 385                         ti,hwmods = "i2c5";
 386                 };
 387
 388                 hwspinlock: spinlock@4a0f6000 {
 389                         compatible = "ti,omap4-hwspinlock";
 390                         reg = <0x4a0f6000 0x1000>;
 391                         ti,hwmods = "spinlock";
 392                         #hwlock-cells = <1>;
 393                 };
 394
 395                 mcspi1: spi@48098000 {
 396                         compatible = "ti,omap4-mcspi";
 397                         reg = <0x48098000 0x200>;
 398                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 399                         #address-cells = <1>;
 400                         #size-cells = <0>;
 401                         ti,hwmods = "mcspi1";
 402                         ti,spi-num-cs = <4>;
 403                         dmas = <&sdma 35>,
 404                                <&sdma 36>,
 405                                <&sdma 37>,
 406                                <&sdma 38>,
 407                                <&sdma 39>,
 408                                <&sdma 40>,
 409                                <&sdma 41>,
 410                                <&sdma 42>;
 411                         dma-names = "tx0", "rx0", "tx1", "rx1",
 412                                     "tx2", "rx2", "tx3", "rx3";
 413                 };
 414
 415                 mcspi2: spi@4809a000 {
 416                         compatible = "ti,omap4-mcspi";
 417                         reg = <0x4809a000 0x200>;
 418                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 419                         #address-cells = <1>;
 420                         #size-cells = <0>;
 421                         ti,hwmods = "mcspi2";
 422                         ti,spi-num-cs = <2>;
 423                         dmas = <&sdma 43>,
 424                                <&sdma 44>,
 425                                <&sdma 45>,
 426                                <&sdma 46>;
 427                         dma-names = "tx0", "rx0", "tx1", "rx1";
 428                 };
 429
 430                 mcspi3: spi@480b8000 {
 431                         compatible = "ti,omap4-mcspi";
 432                         reg = <0x480b8000 0x200>;
 433                         interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 434                         #address-cells = <1>;
 435                         #size-cells = <0>;
 436                         ti,hwmods = "mcspi3";
 437                         ti,spi-num-cs = <2>;
 438                         dmas = <&sdma 15>, <&sdma 16>;
 439                         dma-names = "tx0", "rx0";
 440                 };
 441
 442                 mcspi4: spi@480ba000 {
 443                         compatible = "ti,omap4-mcspi";
 444                         reg = <0x480ba000 0x200>;
 445                         interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
 446                         #address-cells = <1>;
 447                         #size-cells = <0>;
 448                         ti,hwmods = "mcspi4";
 449                         ti,spi-num-cs = <1>;
 450                         dmas = <&sdma 70>, <&sdma 71>;
 451                         dma-names = "tx0", "rx0";
 452                 };
 453
 454                 uart1: serial@4806a000 {
 455                         compatible = "ti,omap4-uart";
 456                         reg = <0x4806a000 0x100>;
 457                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 458                         ti,hwmods = "uart1";
 459                         clock-frequency = <48000000>;
 460                 };
 461
 462                 uart2: serial@4806c000 {
 463                         compatible = "ti,omap4-uart";
 464                         reg = <0x4806c000 0x100>;
 465                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 466                         ti,hwmods = "uart2";
 467                         clock-frequency = <48000000>;
 468                 };
 469
 470                 uart3: serial@48020000 {
 471                         compatible = "ti,omap4-uart";
 472                         reg = <0x48020000 0x100>;
 473                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 474                         ti,hwmods = "uart3";
 475                         clock-frequency = <48000000>;
 476                 };
 477
 478                 uart4: serial@4806e000 {
 479                         compatible = "ti,omap4-uart";
 480                         reg = <0x4806e000 0x100>;
 481                         interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 482                         ti,hwmods = "uart4";
 483                         clock-frequency = <48000000>;
 484                 };
 485
 486                 uart5: serial@48066000 {
 487                         compatible = "ti,omap4-uart";
 488                         reg = <0x48066000 0x100>;
 489                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 490                         ti,hwmods = "uart5";
 491                         clock-frequency = <48000000>;
 492                 };
 493
 494                 uart6: serial@48068000 {
 495                         compatible = "ti,omap4-uart";
 496                         reg = <0x48068000 0x100>;
 497                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 498                         ti,hwmods = "uart6";
 499                         clock-frequency = <48000000>;
 500                 };
 501
 502                 mmc1: mmc@4809c000 {
 503                         compatible = "ti,omap4-hsmmc";
 504                         reg = <0x4809c000 0x400>;
 505                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 506                         ti,hwmods = "mmc1";
 507                         ti,dual-volt;
 508                         ti,needs-special-reset;
 509                         dmas = <&sdma 61>, <&sdma 62>;
 510                         dma-names = "tx", "rx";
 511                         pbias-supply = <&pbias_mmc_reg>;
 512                 };
 513
 514                 mmc2: mmc@480b4000 {
 515                         compatible = "ti,omap4-hsmmc";
 516                         reg = <0x480b4000 0x400>;
 517                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 518                         ti,hwmods = "mmc2";
 519                         ti,needs-special-reset;
 520                         dmas = <&sdma 47>, <&sdma 48>;
 521                         dma-names = "tx", "rx";
 522                 };
 523
 524                 mmc3: mmc@480ad000 {
 525                         compatible = "ti,omap4-hsmmc";
 526                         reg = <0x480ad000 0x400>;
 527                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 528                         ti,hwmods = "mmc3";
 529                         ti,needs-special-reset;
 530                         dmas = <&sdma 77>, <&sdma 78>;
 531                         dma-names = "tx", "rx";
 532                 };
 533
 534                 mmc4: mmc@480d1000 {
 535                         compatible = "ti,omap4-hsmmc";
 536                         reg = <0x480d1000 0x400>;
 537                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 538                         ti,hwmods = "mmc4";
 539                         ti,needs-special-reset;
 540                         dmas = <&sdma 57>, <&sdma 58>;
 541                         dma-names = "tx", "rx";
 542                 };
 543
 544                 mmc5: mmc@480d5000 {
 545                         compatible = "ti,omap4-hsmmc";
 546                         reg = <0x480d5000 0x400>;
 547                         interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 548                         ti,hwmods = "mmc5";
 549                         ti,needs-special-reset;
 550                         dmas = <&sdma 59>, <&sdma 60>;
 551                         dma-names = "tx", "rx";
 552                 };
 553
 554                 mmu_dsp: mmu@4a066000 {
 555                         compatible = "ti,omap4-iommu";
 556                         reg = <0x4a066000 0x100>;
 557                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 558                         ti,hwmods = "mmu_dsp";
 559                 };
 560
 561                 mmu_ipu: mmu@55082000 {
 562                         compatible = "ti,omap4-iommu";
 563                         reg = <0x55082000 0x100>;
 564                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 565                         ti,hwmods = "mmu_ipu";
 566                         ti,iommu-bus-err-back;
 567                 };
 568
 569                 keypad: keypad@4ae1c000 {
 570                         compatible = "ti,omap4-keypad";
 571                         reg = <0x4ae1c000 0x400>;
 572                         ti,hwmods = "kbd";
 573                 };
 574
 575                 mcpdm: mcpdm@40132000 {
 576                         compatible = "ti,omap4-mcpdm";
 577                         reg = <0x40132000 0x7f>, /* MPU private access */
 578                               <0x49032000 0x7f>; /* L3 Interconnect */
 579                         reg-names = "mpu", "dma";
 580                         interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
 581                         ti,hwmods = "mcpdm";
 582                         dmas = <&sdma 65>,
 583                                <&sdma 66>;
 584                         dma-names = "up_link", "dn_link";
 585                         status = "disabled";
 586                 };
 587
 588                 dmic: dmic@4012e000 {
 589                         compatible = "ti,omap4-dmic";
 590                         reg = <0x4012e000 0x7f>, /* MPU private access */
 591                               <0x4902e000 0x7f>; /* L3 Interconnect */
 592                         reg-names = "mpu", "dma";
 593                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 594                         ti,hwmods = "dmic";
 595                         dmas = <&sdma 67>;
 596                         dma-names = "up_link";
 597                         status = "disabled";
 598                 };
 599
 600                 mcbsp1: mcbsp@40122000 {
 601                         compatible = "ti,omap4-mcbsp";
 602                         reg = <0x40122000 0xff>, /* MPU private access */
 603                               <0x49022000 0xff>; /* L3 Interconnect */
 604                         reg-names = "mpu", "dma";
 605                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 606                         interrupt-names = "common";
 607                         ti,buffer-size = <128>;
 608                         ti,hwmods = "mcbsp1";
 609                         dmas = <&sdma 33>,
 610                                <&sdma 34>;
 611                         dma-names = "tx", "rx";
 612                         status = "disabled";
 613                 };
 614
 615                 mcbsp2: mcbsp@40124000 {
 616                         compatible = "ti,omap4-mcbsp";
 617                         reg = <0x40124000 0xff>, /* MPU private access */
 618                               <0x49024000 0xff>; /* L3 Interconnect */
 619                         reg-names = "mpu", "dma";
 620                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 621                         interrupt-names = "common";
 622                         ti,buffer-size = <128>;
 623                         ti,hwmods = "mcbsp2";
 624                         dmas = <&sdma 17>,
 625                                <&sdma 18>;
 626                         dma-names = "tx", "rx";
 627                         status = "disabled";
 628                 };
 629
 630                 mcbsp3: mcbsp@40126000 {
 631                         compatible = "ti,omap4-mcbsp";
 632                         reg = <0x40126000 0xff>, /* MPU private access */
 633                               <0x49026000 0xff>; /* L3 Interconnect */
 634                         reg-names = "mpu", "dma";
 635                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 636                         interrupt-names = "common";
 637                         ti,buffer-size = <128>;
 638                         ti,hwmods = "mcbsp3";
 639                         dmas = <&sdma 19>,
 640                                <&sdma 20>;
 641                         dma-names = "tx", "rx";
 642                         status = "disabled";
 643                 };
 644
 645                 mailbox: mailbox@4a0f4000 {
 646                         compatible = "ti,omap4-mailbox";
 647                         reg = <0x4a0f4000 0x200>;
 648                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 649                         ti,hwmods = "mailbox";
 650                         ti,mbox-num-users = <3>;
 651                         ti,mbox-num-fifos = <8>;
 652                 };
 653
 654                 timer1: timer@4ae18000 {
 655                         compatible = "ti,omap5430-timer";
 656                         reg = <0x4ae18000 0x80>;
 657                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 658                         ti,hwmods = "timer1";
 659                         ti,timer-alwon;
 660                 };
 661
 662                 timer2: timer@48032000 {
 663                         compatible = "ti,omap5430-timer";
 664                         reg = <0x48032000 0x80>;
 665                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 666                         ti,hwmods = "timer2";
 667                 };
 668
 669                 timer3: timer@48034000 {
 670                         compatible = "ti,omap5430-timer";
 671                         reg = <0x48034000 0x80>;
 672                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 673                         ti,hwmods = "timer3";
 674                 };
 675
 676                 timer4: timer@48036000 {
 677                         compatible = "ti,omap5430-timer";
 678                         reg = <0x48036000 0x80>;
 679                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 680                         ti,hwmods = "timer4";
 681                 };
 682
 683                 timer5: timer@40138000 {
 684                         compatible = "ti,omap5430-timer";
 685                         reg = <0x40138000 0x80>,
 686                               <0x49038000 0x80>;
 687                         interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 688                         ti,hwmods = "timer5";
 689                         ti,timer-dsp;
 690                         ti,timer-pwm;
 691                 };
 692
 693                 timer6: timer@4013a000 {
 694                         compatible = "ti,omap5430-timer";
 695                         reg = <0x4013a000 0x80>,
 696                               <0x4903a000 0x80>;
 697                         interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 698                         ti,hwmods = "timer6";
 699                         ti,timer-dsp;
 700                         ti,timer-pwm;
 701                 };
 702
 703                 timer7: timer@4013c000 {
 704                         compatible = "ti,omap5430-timer";
 705                         reg = <0x4013c000 0x80>,
 706                               <0x4903c000 0x80>;
 707                         interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 708                         ti,hwmods = "timer7";
 709                         ti,timer-dsp;
 710                 };
 711
 712                 timer8: timer@4013e000 {
 713                         compatible = "ti,omap5430-timer";
 714                         reg = <0x4013e000 0x80>,
 715                               <0x4903e000 0x80>;
 716                         interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 717                         ti,hwmods = "timer8";
 718                         ti,timer-dsp;
 719                         ti,timer-pwm;
 720                 };
 721
 722                 timer9: timer@4803e000 {
 723                         compatible = "ti,omap5430-timer";
 724                         reg = <0x4803e000 0x80>;
 725                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 726                         ti,hwmods = "timer9";
 727                         ti,timer-pwm;
 728                 };
 729
 730                 timer10: timer@48086000 {
 731                         compatible = "ti,omap5430-timer";
 732                         reg = <0x48086000 0x80>;
 733                         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 734                         ti,hwmods = "timer10";
 735                         ti,timer-pwm;
 736                 };
 737
 738                 timer11: timer@48088000 {
 739                         compatible = "ti,omap5430-timer";
 740                         reg = <0x48088000 0x80>;
 741                         interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
 742                         ti,hwmods = "timer11";
 743                         ti,timer-pwm;
 744                 };
 745
 746                 wdt2: wdt@4ae14000 {
 747                         compatible = "ti,omap5-wdt", "ti,omap3-wdt";
 748                         reg = <0x4ae14000 0x80>;
 749                         interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 750                         ti,hwmods = "wd_timer2";
 751                 };
 752
 753                 dmm@4e000000 {
 754                         compatible = "ti,omap5-dmm";
 755                         reg = <0x4e000000 0x800>;
 756                         interrupts = <0 113 0x4>;
 757                         ti,hwmods = "dmm";
 758                 };
 759
 760                 emif1: emif@4c000000 {
 761                         compatible      = "ti,emif-4d5";
 762                         ti,hwmods       = "emif1";
 763                         ti,no-idle-on-init;
 764                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 765                         reg = <0x4c000000 0x400>;
 766                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 767                         hw-caps-read-idle-ctrl;
 768                         hw-caps-ll-interface;
 769                         hw-caps-temp-alert;
 770                 };
 771
 772                 emif2: emif@4d000000 {
 773                         compatible      = "ti,emif-4d5";
 774                         ti,hwmods       = "emif2";
 775                         ti,no-idle-on-init;
 776                         phy-type        = <2>; /* DDR PHY type: Intelli PHY */
 777                         reg = <0x4d000000 0x400>;
 778                         interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 779                         hw-caps-read-idle-ctrl;
 780                         hw-caps-ll-interface;
 781                         hw-caps-temp-alert;
 782                 };
 783
 784                 omap_control_usb2phy: control-phy@4a002300 {
 785                         compatible = "ti,control-phy-usb2";
 786                         reg = <0x4a002300 0x4>;
 787                         reg-names = "power";
 788                 };
 789
 790                 omap_control_usb3phy: control-phy@4a002370 {
 791                         compatible = "ti,control-phy-pipe3";
 792                         reg = <0x4a002370 0x4>;
 793                         reg-names = "power";
 794                 };
 795
 796                 usb3: omap_dwc3@4a020000 {
 797                         compatible = "ti,dwc3";
 798                         ti,hwmods = "usb_otg_ss";
 799                         reg = <0x4a020000 0x10000>;
 800                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 801                         #address-cells = <1>;
 802                         #size-cells = <1>;
 803                         utmi-mode = <2>;
 804                         ranges;
 805                         dwc3@4a030000 {
 806                                 compatible = "snps,dwc3";
 807                                 reg = <0x4a030000 0x10000>;
 808                                 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
 809                                 phys = <&usb2_phy>, <&usb3_phy>;
 810                                 phy-names = "usb2-phy", "usb3-phy";
 811                                 dr_mode = "peripheral";
 812                                 tx-fifo-resize;
 813                         };
 814                 };
 815
 816                 ocp2scp@4a080000 {
 817                         compatible = "ti,omap-ocp2scp";
 818                         #address-cells = <1>;
 819                         #size-cells = <1>;
 820                         reg = <0x4a080000 0x20>;
 821                         ranges;
 822                         ti,hwmods = "ocp2scp1";
 823                         usb2_phy: usb2phy@4a084000 {
 824                                 compatible = "ti,omap-usb2";
 825                                 reg = <0x4a084000 0x7c>;
 826                                 ctrl-module = <&omap_control_usb2phy>;
 827                                 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
 828                                 clock-names = "wkupclk", "refclk";
 829                                 #phy-cells = <0>;
 830                         };
 831
 832                         usb3_phy: usb3phy@4a084400 {
 833                                 compatible = "ti,omap-usb3";
 834                                 reg = <0x4a084400 0x80>,
 835                                       <0x4a084800 0x64>,
 836                                       <0x4a084c00 0x40>;
 837                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 838                                 ctrl-module = <&omap_control_usb3phy>;
 839                                 clocks = <&usb_phy_cm_clk32k>,
 840                                          <&sys_clkin>,
 841                                          <&usb_otg_ss_refclk960m>;
 842                                 clock-names =   "wkupclk",
 843                                                 "sysclk",
 844                                                 "refclk";
 845                                 #phy-cells = <0>;
 846                         };
 847                 };
 848
 849                 usbhstll: usbhstll@4a062000 {
 850                         compatible = "ti,usbhs-tll";
 851                         reg = <0x4a062000 0x1000>;
 852                         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
 853                         ti,hwmods = "usb_tll_hs";
 854                 };
 855
 856                 usbhshost: usbhshost@4a064000 {
 857                         compatible = "ti,usbhs-host";
 858                         reg = <0x4a064000 0x800>;
 859                         ti,hwmods = "usb_host_hs";
 860                         #address-cells = <1>;
 861                         #size-cells = <1>;
 862                         ranges;
 863                         clocks = <&l3init_60m_fclk>,
 864                                  <&xclk60mhsp1_ck>,
 865                                  <&xclk60mhsp2_ck>;
 866                         clock-names = "refclk_60m_int",
 867                                       "refclk_60m_ext_p1",
 868                                       "refclk_60m_ext_p2";
 869
 870                         usbhsohci: ohci@4a064800 {
 871                                 compatible = "ti,ohci-omap3";
 872                                 reg = <0x4a064800 0x400>;
 873                                 interrupt-parent = <&gic>;
 874                                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
 875                         };
 876
 877                         usbhsehci: ehci@4a064c00 {
 878                                 compatible = "ti,ehci-omap";
 879                                 reg = <0x4a064c00 0x400>;
 880                                 interrupt-parent = <&gic>;
 881                                 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 882                         };
 883                 };
 884
 885                 bandgap: bandgap@4a0021e0 {
 886                         reg = <0x4a0021e0 0xc
 887                                0x4a00232c 0xc
 888                                0x4a002380 0x2c
 889                                0x4a0023C0 0x3c>;
 890                         interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
 891                         compatible = "ti,omap5430-bandgap";
 892
 893                         #thermal-sensor-cells = <1>;
 894                 };
 895
 896                 omap_control_sata: control-phy@4a002374 {
 897                         compatible = "ti,control-phy-pipe3";
 898                         reg = <0x4a002374 0x4>;
 899                         reg-names = "power";
 900                         clocks = <&sys_clkin>;
 901                         clock-names = "sysclk";
 902                 };
 903
 904                 /* OCP2SCP3 */
 905                 ocp2scp@4a090000 {
 906                         compatible = "ti,omap-ocp2scp";
 907                         #address-cells = <1>;
 908                         #size-cells = <1>;
 909                         reg = <0x4a090000 0x20>;
 910                         ranges;
 911                         ti,hwmods = "ocp2scp3";
 912                         sata_phy: phy@4a096000 {
 913                                 compatible = "ti,phy-pipe3-sata";
 914                                 reg = <0x4A096000 0x80>, /* phy_rx */
 915                                       <0x4A096400 0x64>, /* phy_tx */
 916                                       <0x4A096800 0x40>; /* pll_ctrl */
 917                                 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
 918                                 ctrl-module = <&omap_control_sata>;
 919                                 clocks = <&sys_clkin>;
 920                                 clock-names = "sysclk";
 921                                 #phy-cells = <0>;
 922                         };
 923                 };
 924
 925                 sata: sata@4a141100 {
 926                         compatible = "snps,dwc-ahci";
 927                         reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
 928                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 929                         phys = <&sata_phy>;
 930                         phy-names = "sata-phy";
 931                         clocks = <&sata_ref_clk>;
 932                         ti,hwmods = "sata";
 933                 };
 934
 935                 dss: dss@58000000 {
 936                         compatible = "ti,omap5-dss";
 937                         reg = <0x58000000 0x80>;
 938                         status = "disabled";
 939                         ti,hwmods = "dss_core";
 940                         clocks = <&dss_dss_clk>;
 941                         clock-names = "fck";
 942                         #address-cells = <1>;
 943                         #size-cells = <1>;
 944                         ranges;
 945
 946                         dispc@58001000 {
 947                                 compatible = "ti,omap5-dispc";
 948                                 reg = <0x58001000 0x1000>;
 949                                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 950                                 ti,hwmods = "dss_dispc";
 951                                 clocks = <&dss_dss_clk>;
 952                                 clock-names = "fck";
 953                         };
 954
 955                         dsi1: encoder@58004000 {
 956                                 compatible = "ti,omap5-dsi";
 957                                 reg = <0x58004000 0x200>,
 958                                       <0x58004200 0x40>,
 959                                       <0x58004300 0x40>;
 960                                 reg-names = "proto", "phy", "pll";
 961                                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 962                                 status = "disabled";
 963                                 ti,hwmods = "dss_dsi1";
 964                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 965                                 clock-names = "fck", "sys_clk";
 966                         };
 967
 968                         dsi2: encoder@58005000 {
 969                                 compatible = "ti,omap5-dsi";
 970                                 reg = <0x58009000 0x200>,
 971                                       <0x58009200 0x40>,
 972                                       <0x58009300 0x40>;
 973                                 reg-names = "proto", "phy", "pll";
 974                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 975                                 status = "disabled";
 976                                 ti,hwmods = "dss_dsi2";
 977                                 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
 978                                 clock-names = "fck", "sys_clk";
 979                         };
 980
 981                         hdmi: encoder@58060000 {
 982                                 compatible = "ti,omap5-hdmi";
 983                                 reg = <0x58040000 0x200>,
 984                                       <0x58040200 0x80>,
 985                                       <0x58040300 0x80>,
 986                                       <0x58060000 0x19000>;
 987                                 reg-names = "wp", "pll", "phy", "core";
 988                                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 989                                 status = "disabled";
 990                                 ti,hwmods = "dss_hdmi";
 991                                 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
 992                                 clock-names = "fck", "sys_clk";
 993                                 dmas = <&sdma 76>;
 994                                 dma-names = "audio_tx";
 995                         };
 996                 };
 997
 998                 abb_mpu: regulator-abb-mpu {
 999                         compatible = "ti,abb-v2";
1000                         regulator-name = "abb_mpu";
1001                         #address-cells = <0>;
1002                         #size-cells = <0>;
1003                         clocks = <&sys_clkin>;
1004                         ti,settling-time = <50>;
1005                         ti,clock-cycles = <16>;
1006
1007                         reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1008                               <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1009                         reg-names = "base-address", "int-address",
1010                                     "efuse-address", "ldo-address";
1011                         ti,tranxdone-status-mask = <0x80>;
1012                         /* LDOVBBMPU_MUX_CTRL */
1013                         ti,ldovbb-override-mask = <0x400>;
1014                         /* LDOVBBMPU_VSET_OUT */
1015                         ti,ldovbb-vset-mask = <0x1F>;
1016
1017                         /*
1018                          * NOTE: only FBB mode used but actual vset will
1019                          * determine final biasing
1020                          */
1021                         ti,abb_info = <
1022                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1023                         1060000         0       0x0     0 0x02000000 0x01F00000
1024                         1250000         0       0x4     0 0x02000000 0x01F00000
1025                         >;
1026                 };
1027
1028                 abb_mm: regulator-abb-mm {
1029                         compatible = "ti,abb-v2";
1030                         regulator-name = "abb_mm";
1031                         #address-cells = <0>;
1032                         #size-cells = <0>;
1033                         clocks = <&sys_clkin>;
1034                         ti,settling-time = <50>;
1035                         ti,clock-cycles = <16>;
1036
1037                         reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1038                               <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1039                         reg-names = "base-address", "int-address",
1040                                     "efuse-address", "ldo-address";
1041                         ti,tranxdone-status-mask = <0x80000000>;
1042                         /* LDOVBBMM_MUX_CTRL */
1043                         ti,ldovbb-override-mask = <0x400>;
1044                         /* LDOVBBMM_VSET_OUT */
1045                         ti,ldovbb-vset-mask = <0x1F>;
1046
1047                         /*
1048                          * NOTE: only FBB mode used but actual vset will
1049                          * determine final biasing
1050                          */
1051                         ti,abb_info = <
1052                         /*uV            ABB     efuse   rbb_m fbb_m     vset_m*/
1053                         1025000         0       0x0     0 0x02000000 0x01F00000
1054                         1120000         0       0x4     0 0x02000000 0x01F00000
1055                         >;
1056                 };
1057         };
1058 };
1059
1060 /include/ "omap54xx-clocks.dtsi"