arch/arm/boot/dts/qcom/msm8996-vidc.dtsi

   1 /* Copyright (c) 2014-2015, 2017, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14
  15 &soc {
  16         msm_vidc: qcom,vidc@c00000 {
  17                 compatible = "qcom,msm-vidc";
  18                 status = "ok";
  19                 reg = <0xC00000 0xff000>;
  20                 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
  21                 qcom,hfi = "venus";
  22                 qcom,hfi-version = "3xx";
  23                 qcom,reg-presets = <0x80010 0xffffffff>,
  24                         <0x80018 0x00001556>,
  25                         <0x8001C 0x00001556>;
  26                 qcom,qdss-presets = <0x08180000 0x2000>,
  27                         <0x08182000 0x2000>,
  28                         <0x08184000 0x2000>,
  29                         <0x08186000 0x2000>,
  30                         <0x08188000 0x2000>,
  31                         <0x0818A000 0x2000>,
  32                         <0x0818C000 0x2000>,
  33                         <0x0818E000 0x2000>;
  34                 qcom,max-hw-load = <2563200>; /* Full 4k @ 60 + 1080p @ 60 */
  35                 qcom,power-conf = <8294400>; /* WxH - 3840*2160 */
  36                 qcom,firmware-name = "venus";
  37                 qcom,imem-size = <524288>; /* 512 kB */
  38                 qcom,never-unload-fw;
  39                 qcom,sw-power-collapse;
  40                 qcom,max-secure-instances = <5>;
  41                 qcom,load-freq-tbl =
  42                         /* Encoders */
  43                         <972000 490000000 0x55555555>, /* 4k UHD @ 30 */
  44                         <489600 320000000 0x55555555>, /* 1080p @ 60 */
  45                         <244800 150000000 0x55555555>, /* 1080p @ 30 */
  46                         <108000  75000000 0x55555555>, /* 720p @ 30 */
  47
  48                         /* Decoders */
  49                         <1944000 490000000 0xffffffff>, /* 4k UHD @ 60 */
  50                         < 972000 320000000 0xffffffff>, /* 4k UHD @ 30 */
  51                         < 489600 150000000 0xffffffff>, /* 1080p @ 60 */
  52                         < 244800  75000000 0xffffffff>; /* 1080p @ 30 */
  53
  54                 qcom,dcvs-tbl =
  55                         <972000 972000 19944000 0x3f00000c>, /* UHD 30 */
  56                         <489600 489600   972000 0x3f00000c>, /* 1080p 60 */
  57                         <244800 244800   489600 0x3f00000c>, /* 1080p 30 */
  58                         <829440 489600   972000 0x04000004>; /* DCI 24 */
  59
  60                 qcom,dcvs-limit =
  61                         <32400 30>, /* Encoder UHD */
  62                         <14400 30>; /* Decoder WQHD */
  63
  64                 /* Table lists <video_core_freq imem_ab> pairs.
  65                  * imem_ab value determines the imem clock frequency for the
  66                  * corresponding video core frequency.
  67                  */
  68                 qcom,imem-ab-tbl =
  69                         <75000000  1500000>, /* imem @ svs2 freq 75 Mhz */
  70                         <150000000 1500000>, /* imem @ svs2 freq 75 Mhz */
  71                         <320000000 2500000>, /* imem @ svs freq 171 Mhz */
  72                         <490000000 6000000>; /* imem @ noimal freq 320 Mhz */
  73
  74                 /* Regulators */
  75                 /* Note: don't change the order of the regulators below as they
  76                  * correspond to the order in which the driver enables them.
  77                  */
  78                 mmagic-venus-supply = <&gdsc_mmagic_video>;
  79                 venus-supply = <&gdsc_venus>;
  80                 venus-core0-supply = <&gdsc_venus_core0>;
  81                 venus-core1-supply = <&gdsc_venus_core1>;
  82
  83                 /* Clocks */
  84                 clock-names = "smmu_ahb_clk", "smmu_axi_clk",
  85                         "mmagic_video_axi", "core_clk", "iface_clk",
  86                         "bus_clk", "maxi_clk", "core0_clk", "core1_clk";
  87                 clocks = <&clock_mmss clk_smmu_video_ahb_clk>,
  88                        <&clock_mmss clk_smmu_video_axi_clk>,
  89                        <&clock_mmss clk_mmagic_video_axi_clk>,
  90                        <&clock_mmss clk_video_core_clk>,
  91                        <&clock_mmss clk_video_ahb_clk>,
  92                        <&clock_mmss clk_video_axi_clk>,
  93                        <&clock_mmss clk_video_maxi_clk>,
  94                        <&clock_mmss clk_video_subcore0_clk>,
  95                        <&clock_mmss clk_video_subcore1_clk>;
  96                 qcom,clock-configs = <0x0 0x0 0x0 0x1 0x0 0x0 0x0 0x1 0x1>;
  97
  98                 /* Buses */
  99                 bus_cnoc {
 100                         compatible = "qcom,msm-vidc,bus";
 101                         label = "cnoc";
 102                         qcom,bus-master = <MSM_BUS_MASTER_AMPSS_M0>;
 103                         qcom,bus-slave = <MSM_BUS_SLAVE_VENUS_CFG>;
 104                         qcom,bus-governor = "performance";
 105                         qcom,bus-range-kbps = <1 1>;
 106                 };
 107
 108                 venus_bus_ddr {
 109                         compatible = "qcom,msm-vidc,bus";
 110                         label = "venus-ddr";
 111                         qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 112                         qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
 113                         qcom,bus-governor = "msm-vidc-ddr";
 114                         qcom,bus-range-kbps = <1000 3388000>;
 115                 };
 116
 117                 venus_bus_vmem {
 118                         compatible = "qcom,msm-vidc,bus";
 119                         label = "venus-vmem";
 120                         qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0_OCMEM>;
 121                         qcom,bus-slave = <MSM_BUS_SLAVE_VMEM>;
 122                         qcom,bus-governor = "msm-vidc-vmem+";
 123                         qcom,bus-range-kbps = <1000 6776000>;
 124                 };
 125
 126                 arm9_bus_ddr {
 127                         compatible = "qcom,msm-vidc,bus";
 128                         label = "venus-arm9-ddr";
 129                         qcom,bus-master = <MSM_BUS_MASTER_VIDEO_P0>;
 130                         qcom,bus-slave = <MSM_BUS_SLAVE_EBI_CH0>;
 131                         qcom,bus-governor = "performance";
 132                         qcom,bus-range-kbps = <1 1>;
 133                 };
 134
 135                 /* MMUs */
 136                 non_secure_cb {
 137                         compatible = "qcom,msm-vidc,context-bank";
 138                         label = "venus_ns";
 139                         iommus = <&venus_smmu 0x00>,
 140                                 <&venus_smmu 0x01>,
 141                                 <&venus_smmu 0x0a>,
 142                                 <&venus_smmu 0x07>,
 143                                 <&venus_smmu 0x0e>,
 144                                 <&venus_smmu 0x0f>,
 145                                 <&venus_smmu 0x08>,
 146                                 <&venus_smmu 0x09>,
 147                                 <&venus_smmu 0x0b>,
 148                                 <&venus_smmu 0x0c>,
 149                                 <&venus_smmu 0x0d>,
 150                                 <&venus_smmu 0x10>,
 151                                 <&venus_smmu 0x11>,
 152                                 <&venus_smmu 0x21>,
 153                                 <&venus_smmu 0x28>,
 154                                 <&venus_smmu 0x29>,
 155                                 <&venus_smmu 0x2b>,
 156                                 <&venus_smmu 0x2c>,
 157                                 <&venus_smmu 0x2d>,
 158                                 <&venus_smmu 0x31>;
 159                         buffer-types = <0xfff>;
 160                         virtual-addr-pool = <0x70800000 0x8F800000>;
 161                 };
 162
 163                 firmware_cb {
 164                         compatible = "qcom,msm-vidc,context-bank";
 165                         qcom,fw-context-bank;
 166                         iommus = <&venus_smmu 0x180>,
 167                                 <&venus_smmu 0x186>;
 168                 };
 169
 170                 secure_bitstream_cb {
 171                         compatible = "qcom,msm-vidc,context-bank";
 172                         label = "venus_sec_bitstream";
 173                         iommus = <&venus_smmu 0x100>,
 174                                 <&venus_smmu 0x102>,
 175                                 <&venus_smmu 0x109>,
 176                                 <&venus_smmu 0x10a>,
 177                                 <&venus_smmu 0x10b>,
 178                                 <&venus_smmu 0x10e>,
 179                                 <&venus_smmu 0x126>,
 180                                 <&venus_smmu 0x129>,
 181                                 <&venus_smmu 0x12b>;
 182                         buffer-types = <0x241>;
 183                         virtual-addr-pool = <0x4b000000 0x25800000>;
 184                         qcom,secure-context-bank;
 185                 };
 186
 187                 venus_secure_pixel_cb: secure_pixel_cb {
 188                         compatible = "qcom,msm-vidc,context-bank";
 189                         label = "venus_sec_pixel";
 190                         iommus = <&venus_smmu 0x104>,
 191                                 <&venus_smmu 0x10c>,
 192                                 <&venus_smmu 0x110>,
 193                                 <&venus_smmu 0x12c>;
 194                         buffer-types = <0x106>;
 195                         virtual-addr-pool = <0x25800000 0x25800000>;
 196                         qcom,secure-context-bank;
 197                 };
 198
 199                 venus_secure_non_pixel_cb: secure_non_pixel_cb {
 200                         compatible = "qcom,msm-vidc,context-bank";
 201                         label = "venus_sec_non_pixel";
 202                         iommus = <&venus_smmu 0x105>,
 203                                 <&venus_smmu 0x107>,
 204                                 <&venus_smmu 0x108>,
 205                                 <&venus_smmu 0x10d>,
 206                                 <&venus_smmu 0x10f>,
 207                                 <&venus_smmu 0x125>,
 208                                 <&venus_smmu 0x128>,
 209                                 <&venus_smmu 0x12d>,
 210                                 <&venus_smmu 0x140>;
 211                         buffer-types = <0x480>;
 212                         virtual-addr-pool = <0x1000000 0x24800000>;
 213                         qcom,secure-context-bank;
 214                 };
 215         };
 216
 217         vmem: qcom,vmem@880000 {
 218                 compatible = "qcom,msm-vmem";
 219                 interrupts = <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
 220
 221                 reg = <0x880000 0x800>,
 222                     <0x6800000 0x80000>;
 223                 reg-names = "reg-base", "mem-base";
 224
 225                 vdd-supply = <&gdsc_mmagic_video>;
 226                 clocks = <&clock_mmss clk_vmem_ahb_clk>,
 227                        <&clock_mmss clk_vmem_maxi_clk>;
 228                 clock-names = "ahb", "maxi";
 229                 clock-config = <0x0 0x0 0x0 0x1>;
 230
 231                 qcom,msm-bus,name = "vmem";
 232                 qcom,msm-bus,num-cases = <2>;
 233                 qcom,msm-bus,num-paths = <1>;
 234                 qcom,msm-bus,vectors-KBps =
 235                 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG   0   0>,
 236                 <MSM_BUS_MASTER_AMPSS_M0 MSM_BUS_SLAVE_VMEM_CFG 500 800>;
 237
 238                 qcom,bank-size = <131072>; /* 128 kB */
 239         };
 240 };