arch/arm/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include "skeleton64.dtsi"
  14 #include <dt-bindings/clock/msm-clocks-8996.h>
  15 #include <dt-bindings/interrupt-controller/arm-gic.h>
  16
  17 / {
  18         model = "Qualcomm Technologies, Inc. MSM 8996";
  19         compatible = "qcom,msm8996";
  20         qcom,msm-id = <246 0x0>;
  21         qcom,pmic-id = <0x20009 0x2000A 0x0 0x0>;
  22         interrupt-parent = <&intc>;
  23
  24         chosen {
  25                 bootargs = "fpsimd.fpsimd_settings=1 app_setting.use_app_setting=1 app_setting.use_32bit_app_setting=1";
  26         };
  27
  28         aliases {
  29                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  30                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  31                 smd7 = &smdtty_data1;
  32                 smd8 = &smdtty_data4;
  33                 smd11 = &smdtty_data11;
  34                 smd21 = &smdtty_data21;
  35                 smd36 = &smdtty_loopback;
  36                 pci-domain0 = &pcie0;
  37                 pci-domain1 = &pcie1;
  38                 pci-domain2 = &pcie2;
  39                 i2c6 = &i2c_6;
  40                 i2c7 = &i2c_7;
  41                 i2c8 = &i2c_8;
  42                 i2c12 = &i2c_12;
  43                 spi0 = &spi_0;
  44                 serial0 = &uartblsp2dm1;
  45         };
  46
  47         chosen {
  48                 stdout-path = "serial0";
  49                 bootargs = "sched_enable_hmp=1 sched_enable_power_aware=1 rcupdate.rcu_expedited=1";
  50         };
  51
  52         psci {
  53                 compatible = "arm,psci-1.0";
  54                 method = "smc";
  55         };
  56
  57         cpus {
  58                 #address-cells = <2>;
  59                 #size-cells = <0>;
  60
  61                 CPU0: cpu@0 {
  62                         device_type = "cpu";
  63                         compatible = "qcom,kryo";
  64                         reg = <0x0 0x0>;
  65                         qcom,limits-info = <&mitigation_profile0>;
  66                         enable-method = "psci";
  67                         qcom,ea = <&ea0>;
  68                         next-level-cache = <&L2_0>;
  69                         L2_0: l2-cache {
  70                               compatible = "cache";
  71                               cache-level = <2>;
  72                               qcom,dump-size = <0x88000>;
  73                         };
  74                         L1_D_0: l1-dcache {
  75                                 compatible = "cache";
  76                                 qcom,dump-size = <0x7800>;
  77                         };
  78                         L1_TLB_0: l1-tlb {
  79                                 qcom,dump-size = <0x2800>;
  80                         };
  81                 };
  82
  83                 CPU1: cpu@1 {
  84                         device_type = "cpu";
  85                         compatible = "qcom,kryo";
  86                         reg = <0x0 0x1>;
  87                         qcom,limits-info = <&mitigation_profile1>;
  88                         enable-method = "psci";
  89                         qcom,ea = <&ea1>;
  90                         next-level-cache = <&L2_0>;
  91                         L1_D_1: l1-dcache {
  92                                 compatible = "cache";
  93                                 qcom,dump-size = <0x7800>;
  94                         };
  95                         L1_TLB_1: l1-tlb {
  96                                 qcom,dump-size = <0x2800>;
  97                         };
  98                 };
  99
 100                 CPU2: cpu@100 {
 101                         device_type = "cpu";
 102                         compatible = "qcom,kryo";
 103                         reg = <0x0 0x100>;
 104                         qcom,limits-info = <&mitigation_profile2>;
 105                         enable-method = "psci";
 106                         qcom,ea = <&ea2>;
 107                         next-level-cache = <&L2_1>;
 108                         L2_1: l2-cache {
 109                               compatible = "cache";
 110                               cache-level = <2>;
 111                               qcom,dump-size = <0x110000>;
 112                         };
 113                         L1_D_100: l1-dcache {
 114                                 compatible = "cache";
 115                                 qcom,dump-size = <0x7800>;
 116                         };
 117                         L1_TLB_100: l1-tlb {
 118                                 qcom,dump-size = <0x2800>;
 119                         };
 120                 };
 121
 122                 CPU3: cpu@101 {
 123                         device_type = "cpu";
 124                         compatible = "qcom,kryo";
 125                         reg = <0x0 0x101>;
 126                         enable-method = "psci";
 127                         qcom,limits-info = <&mitigation_profile3>;
 128                         qcom,ea = <&ea3>;
 129                         next-level-cache = <&L2_1>;
 130                         L1_D_101: l1-dcache {
 131                                 compatible = "cache";
 132                                 qcom,dump-size = <0x7800>;
 133                         };
 134                         L1_TLB_101: l1-tlb {
 135                                 qcom,dump-size = <0x2800>;
 136                         };
 137                 };
 138
 139                 cpu-map {
 140                         cluster0 {
 141                                 core0 {
 142                                         cpu = <&CPU0>;
 143                                 };
 144
 145                                 core1 {
 146                                         cpu = <&CPU1>;
 147                                 };
 148                         };
 149
 150                         cluster1 {
 151                                 core0 {
 152                                         cpu = <&CPU2>;
 153                                 };
 154
 155                                 core1 {
 156                                         cpu = <&CPU3>;
 157                                 };
 158                         };
 159                 };
 160         };
 161
 162        clocks {
 163                xo_board {
 164                        compatible = "fixed-clock";
 165                        #clock-cells = <0>;
 166                        clock-frequency = <19200000>;
 167                        clock-output-names = "xo_board";
 168                 };
 169                sleep_clk {
 170                        compatible = "fixed-clock";
 171                        #clock-cells = <0>;
 172                        clock-frequency = <32764>;
 173                        clock-output-names = "sleep_clk";
 174                 };
 175         };
 176
 177         soc: soc { };
 178
 179         firmware: firmware {
 180                 android {
 181                         compatible = "android,firmware";
 182                         fstab {
 183                                 compatible = "android,fstab";
 184                                 vendor {
 185                                         compatible = "android,vendor";
 186                                         dev = "/dev/block/platform/soc/7464900.sdhci/by-name/vendor";
 187                                         type = "ext4";
 188                                         mnt_flags = "ro,barrier=1,discard";
 189                                         fsmgr_flags = "wait";
 190                                         status = "ok";
 191                                 };
 192                                 system {
 193                                         compatible = "android,system";
 194                                         dev = "/dev/block/platform/soc/7464900.sdhci/by-name/system";
 195                                         type = "ext4";
 196                                         mnt_flags = "ro,barrier=1,discard";
 197                                         fsmgr_flags = "wait";
 198                                         status = "ok";
 199                                 };
 200                         };
 201                 };
 202         };
 203
 204         reserved-memory {
 205                 #address-cells = <2>;
 206                 #size-cells = <2>;
 207                 ranges;
 208
 209                 removed_regions: removed_regions@85800000 {
 210                         compatible = "removed-dma-pool";
 211                         no-map;
 212                         reg = <0 0x85800000 0 0x3000000>;
 213                 };
 214
 215                 peripheral_mem: peripheral_region@8ea00000 {
 216                         compatible = "removed-dma-pool";
 217                         no-map;
 218                         reg = <0 0x8ea00000 0 0x2b00000>;
 219                 };
 220
 221                 adsp_mem: adsp_region {
 222                         compatible = "shared-dma-pool";
 223                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 224                         reusable;
 225                         alignment = <0 0x100000>;
 226                         size = <0 0x400000>;
 227                 };
 228
 229                 qseecom_mem: qseecom_region {
 230                         compatible = "shared-dma-pool";
 231                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 232                         reusable;
 233                         alignment = <0 0x400000>;
 234                         size = <0 0x1400000>;
 235                 };
 236
 237                 secure_display_memory: secure_region {
 238                         compatible = "shared-dma-pool";
 239                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 240                         reusable;
 241                         alignment = <0 0x200000>;
 242                         size = <0 0x5c00000>;
 243                 };
 244
 245                 modem_mem: modem_region@88800000 {
 246                         compatible = "removed-dma-pool";
 247                         no-map;
 248                         reg = <0 0x88800000 0 0x6200000>;
 249                 };
 250
 251                 dfps_data_mem: dfps_data_mem@83400000 {
 252                        reg = <0 0x83400000 0 0x1000>;
 253                        label = "dfps_data_mem";
 254                 };
 255
 256                 cont_splash_mem: cont_splash_mem@83401000 {
 257                         reg = <0 0x83401000 0 0x23FF000>;
 258                         label = "cont_splash_mem";
 259                 };
 260
 261                 cont_splash_mem_hdmi: cont_splash_mem_hdmi@bdd00000 {
 262                         reg = <0 0xbdd00000 0 0x23ff000>;
 263                         label = "cont_splash_mem_hdmi";
 264                 };
 265         };
 266 };
 267
 268 #include "msm8996-ion.dtsi"
 269 #include "msm8996-mdss.dtsi"
 270 #include "msm8996-mdss-pll.dtsi"
 271 #include "msm8996-smp2p.dtsi"
 272 #include "msm8996-ipcrouter.dtsi"
 273 #include "msm-gdsc-8996.dtsi"
 274 #include "msm8996-bus.dtsi"
 275 #include "msm-rdbg.dtsi"
 276 #include "msm8996-blsp.dtsi"
 277
 278 &soc {
 279         #address-cells = <1>;
 280         #size-cells = <1>;
 281         ranges = <0 0 0 0xffffffff>;
 282         compatible = "simple-bus";
 283
 284         spmi_bus: qcom,spmi@400f000 {
 285                 compatible = "qcom,spmi-pmic-arb";
 286                 reg = <0x400f000 0xc00>,
 287                       <0x4400000 0x800000>,
 288                       <0x4c00000 0x800000>,
 289                       <0x5800000 0x200000>,
 290                       <0x400a000 0x002100>;
 291                 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 292                 interrupt-names = "periph_irq";
 293                 interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
 294                 qcom,ee = <0>;
 295                 qcom,channel = <0>;
 296                 #address-cells = <2>;
 297                 #size-cells = <0>;
 298                 interrupt-controller;
 299                 #interrupt-cells = <4>;
 300                 cell-index = <0>;
 301         };
 302
 303         apc_apm: apm@099e0000 {
 304                 compatible = "qcom,msm-apm";
 305                 reg = <0x099e0000 0x1000>,
 306                         <0x09820000 0x10000>,
 307                         <0x06400050 0x8>,
 308                         <0x06480050 0x8>,
 309                         <0x09981068 0x8>,
 310                         <0x09991068 0x8>,
 311                         <0x099b1068 0x8>,
 312                         <0x099c1068 0x8>,
 313                         <0x099a1068 0x8>,
 314                         <0x099d1068 0x8>;
 315                 reg-names = "pm-apcc-glb",
 316                                 "apcs-csr",
 317                                 "apc0-pll-ctl",
 318                                 "apc1-pll-ctl",
 319                                 "apc0-cpu0-spm",
 320                                 "apc0-cpu1-spm",
 321                                 "apc1-cpu0-spm",
 322                                 "apc1-cpu1-spm",
 323                                 "apc0-l2-spm",
 324                                 "apc1-l2-spm";
 325                 qcom,clock-source-override;
 326         };
 327
 328         intc: interrupt-controller@09bc0000 {
 329                 compatible = "arm,gic-v3";
 330                 reg = <0x9bc0000 0x10000>,       /* GICD */
 331                       <0x9c00000 0x100000>;      /* GICR * 4 */
 332                 #interrupt-cells = <3>;
 333                 #address-cells = <1>;
 334                 #size-cells = <1>;
 335                 ranges;
 336                 interrupt-controller;
 337                 #redistributor-regions = <1>;
 338                 redistributor-stride = <0x0 0x40000>;
 339
 340                 interrupts = <1 9 4>;
 341
 342                 gic-its@09BE0000 {
 343                         compatible = "arm,gic-v3-its";
 344                         msi-contoller;
 345                         reg = <0x9be0000 0x20000>;
 346                 };
 347         };
 348
 349         timer {
 350                 compatible = "arm,armv8-timer";
 351                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 352                                 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 353                                 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 354                                 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 355                 clock-frequency = <19200000>;
 356         };
 357
 358         restart@4ab000 {
 359                 compatible = "qcom,pshold";
 360                 reg = <0x4ab000 0x4>,
 361                       <0x7b3000 0x4>;
 362                 reg-names = "pshold-base", "tcsr-boot-misc-detect";
 363         };
 364
 365         qcom,sps {
 366                 compatible = "qcom,msm_sps_4k";
 367                 qcom,device-type = <3>;
 368                 qcom,pipe-attr-ee;
 369         };
 370
 371         uartblsp2dm1: serial@075b0000 {
 372                 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 373                 reg = <0x75b0000 0x1000>;
 374                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
 376                          <&clock_gcc clk_gcc_blsp2_ahb_clk>;
 377                 clock-names = "core", "iface";
 378         };
 379
 380         uartblsp1dm1: serial@07570000 {
 381                 compatible = "qcom,msm-lsuart-v14";
 382                 reg = <0x7570000 0x1000>;
 383                 interrupts = <0 108 0>;
 384                 status = "disabled";
 385                 clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
 386                          <&clock_gcc clk_gcc_blsp1_ahb_clk>;
 387                 clock-names = "core_clk", "iface_clk";
 388         };
 389
 390         i2c_12: i2c@75ba000 {
 391                 compatible = "qcom,i2c-msm-v2";
 392                 #address-cells = <1>;
 393                 #size-cells = <0>;
 394                 reg-names = "qup_phys_addr";
 395                 reg = <0x75ba000 0x1000>;
 396                 interrupt-names = "qup_irq";
 397                 interrupts = <0 106 0>;
 398                 dmas = <&dma_blsp2 22 64 0x20000020 0x20>,
 399                         <&dma_blsp2 23 32 0x20000020 0x20>;
 400                 dma-names = "tx", "rx";
 401                 qcom,master-id = <84>;
 402                 qcom,clk-freq-out = <400000>;
 403                 qcom,clk-freq-in  = <19200000>;
 404                 clock-names = "iface_clk", "core_clk";
 405                 clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
 406                          <&clock_gcc clk_gcc_blsp2_qup6_i2c_apps_clk>;
 407                 qcom,i2c-dat = <&tlmm 87 0x00>;
 408                 qcom,i2c-clk = <&tlmm 88 0x00>;
 409                 pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
 410                 pinctrl-0 = <&i2c_12_active>;
 411                 pinctrl-1 = <&i2c_12_sleep>;
 412                 pinctrl-2 = <&i2c_12_bitbang>;
 413         };
 414
 415
 416         dma_blsp1: qcom,sps-dma@0x7544000{ /* BLSP1 */
 417                 #dma-cells = <4>;
 418                 compatible = "qcom,sps-dma";
 419                 reg = <0x7544000 0x2b000>;
 420                 interrupts = <0 238 0>;
 421                 qcom,summing-threshold = <0x10>;
 422         };
 423
 424         dma_blsp2: qcom,sps-dma@0x7584000{ /* BLSP2 */
 425                 #dma-cells = <4>;
 426                 compatible = "qcom,sps-dma";
 427                 reg = <0x7584000 0x2b000>;
 428                 interrupts = <0 239 0>;
 429                 qcom,summing-threshold = <0x10>;
 430         };
 431
 432         i2c_6: i2c@757a000 { /* BLSP1 QUP6 */
 433                 compatible = "qcom,i2c-msm-v2";
 434                 #address-cells = <1>;
 435                 #size-cells = <0>;
 436                 reg = <0x757a000  0x1000>;
 437                 reg-names = "qup_phys_addr";
 438                 interrupt-names = "qup_irq";
 439                 interrupts = <0 100 0>;
 440                 dmas = <&dma_blsp1 22 64 0x20000020 0x20>,
 441                         <&dma_blsp1 23 32 0x20000020 0x20>;
 442                 dma-names = "tx", "rx";
 443                 qcom,master-id = <86>;
 444                 qcom,clk-freq-out = <400000>;
 445                 qcom,clk-freq-in  = <19200000>;
 446                 clock-names = "iface_clk", "core_clk";
 447                 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
 448                          <&clock_gcc clk_gcc_blsp1_qup6_i2c_apps_clk>;
 449                 qcom,i2c-dat = <&tlmm 27 0x00>;
 450                 qcom,i2c-clk = <&tlmm 28 0x00>;
 451                 pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
 452                 pinctrl-0 = <&i2c_6_active>;
 453                 pinctrl-1 = <&i2c_6_sleep>;
 454                 pinctrl-2 = <&i2c_6_bitbang>;
 455         };
 456
 457         i2c_7: i2c@75b5000 { /* BLSP2 QUP1 */
 458                 compatible = "qcom,i2c-msm-v2";
 459                 #address-cells = <1>;
 460                 #size-cells = <0>;
 461                 reg-names = "qup_phys_addr";
 462                 reg = <0x75b5000 0x1000>;
 463                 interrupt-names = "qup_irq";
 464                 interrupts = <0 101 0>;
 465                 dmas = <&dma_blsp2 12 32 0x20000020 0x20>,
 466                         <&dma_blsp2 13 32 0x20000020 0x20>;
 467                 dma-names = "tx", "rx";
 468                 qcom,master-id = <84>;
 469                 qcom,clk-freq-out = <400000>;
 470                 qcom,clk-freq-in  = <19200000>;
 471                 clock-names = "iface_clk", "core_clk";
 472                 clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
 473                          <&clock_gcc clk_gcc_blsp2_qup1_i2c_apps_clk>;
 474                 qcom,i2c-dat = <&tlmm 55 0x00>;
 475                 qcom,i2c-clk = <&tlmm 56 0x00>;
 476                 pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
 477                 pinctrl-0 = <&i2c_7_active>;
 478                 pinctrl-1 = <&i2c_7_sleep>;
 479                 pinctrl-2 = <&i2c_7_bitbang>;
 480         };
 481
 482         i2c_8: i2c@75b6000 { /* BLSP2 QUP2 */
 483                 compatible = "qcom,i2c-msm-v2";
 484                 #address-cells = <1>;
 485                 #size-cells = <0>;
 486                 reg-names = "qup_phys_addr";
 487                 reg = <0x75b6000 0x1000>;
 488                 interrupt-names = "qup_irq";
 489                 interrupts = <0 102 0>;
 490                 dmas = <&dma_blsp2 14 32 0x20000020 0x20>,
 491                         <&dma_blsp2 15 32 0x20000020 0x20>;
 492                 dma-names = "tx", "rx";
 493                 qcom,master-id = <84>;
 494                 qcom,clk-freq-out = <400000>;
 495                 qcom,clk-freq-in  = <19200000>;
 496                 clock-names = "iface_clk", "core_clk";
 497                 clocks = <&clock_gcc clk_gcc_blsp2_ahb_clk>,
 498                         <&clock_gcc clk_gcc_blsp2_qup2_i2c_apps_clk>;
 499                 qcom,i2c-dat = <&tlmm 6 0x00>;
 500                 qcom,i2c-clk = <&tlmm 7 0x00>;
 501                 pinctrl-names = "i2c_active", "i2c_sleep", "i2c_bitbang";
 502                 pinctrl-0 = <&i2c_8_active>;
 503                 pinctrl-1 = <&i2c_8_sleep>;
 504                 pinctrl-2 = <&i2c_8_bitbang>;
 505         };
 506
 507         blsp1_uart2: uart@07570000 { /* BLSP1 UART2 */
 508                 compatible = "qcom,msm-hsuart-v14";
 509                 reg = <0x07570000 0x1000>,
 510                     <0x7544000 0x2b000>;
 511                 status = "disabled";
 512                 reg-names = "core_mem", "bam_mem";
 513                 interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
 514                 #address-cells = <0>;
 515                 interrupt-parent = <&blsp1_uart2>;
 516                 interrupts = <0 1 2>;
 517                 #interrupt-cells = <1>;
 518                 interrupt-map-mask = <0xffffffff>;
 519                 interrupt-map = <0 &intc 0 0 108 0
 520                             1 &intc 0 0 238 0
 521                             2 &tlmm 42 0>;
 522
 523                 qcom,inject-rx-on-wakeup;
 524                 qcom,rx-char-to-inject = <0xFD>;
 525
 526                 qcom,bam-tx-ep-pipe-index = <2>;
 527                 qcom,bam-rx-ep-pipe-index = <3>;
 528                 qcom,master-id = <86>;
 529                 clock-names = "core_clk", "iface_clk";
 530                 clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
 531                     <&clock_gcc clk_gcc_blsp1_ahb_clk>;
 532                 pinctrl-names = "sleep", "default";
 533                 pinctrl-0 = <&blsp1_uart2_sleep>;
 534                 pinctrl-1 = <&blsp1_uart2_active>;
 535
 536                 qcom,msm-bus,name = "buart2";
 537                 qcom,msm-bus,num-cases = <2>;
 538                 qcom,msm-bus,num-paths = <1>;
 539                 qcom,msm-bus,vectors-KBps =
 540                             <86 512 0 0>,
 541                             <86 512 500 800>;
 542         };
 543
 544         m4m_cache: qcom,m4m {
 545                 compatible = "devfreq-simple-dev";
 546                 clock-names = "devfreq_clk";
 547                 clocks = <&clock_cpu clk_cbf_clk>;
 548                 governor = "cpufreq";
 549                 freq-tbl-khz =
 550                         <  150000 >,
 551                         <  307200 >,
 552                         <  384000 >,
 553                         <  499200 >,
 554                         <  595200 >,
 555                         <  691200 >,
 556                         <  787200 >,
 557                         <  883200 >,
 558                         <  960000 >,
 559                         < 1036800 >;
 560         };
 561
 562         cpubw: qcom,cpubw {
 563                 compatible = "qcom,devbw";
 564                 governor = "performance";
 565                 qcom,src-dst-ports = <1 512>;
 566                 qcom,active-only;
 567                 qcom,bw-tbl =
 568                         <   762 /*  100 MHz */ >,
 569                         <  1144 /*  150 MHz */ >,
 570                         <  1525 /*  200 MHz */ >,
 571                         <  2288 /*  300 MHz */ >,
 572                         <  3143 /*  412 MHz */ >,
 573                         <  4173 /*  547 MHz */ >,
 574                         <  5195 /*  681 MHz */ >,
 575                         <  5859 /*  768 MHz */ >,
 576                         <  7759 /* 1017 MHz */ >,
 577                         <  9887 /* 1296 MHz */ >,
 578                         < 11863 /* 1555 MHz */ >,
 579                         < 13763 /* 1804 MHz */ >;
 580         };
 581
 582         qcom,cpu-bwmon {
 583                 compatible = "qcom,bimc-bwmon3";
 584                 reg = <0x00408000 0x300>, <0x00401000 0x200>;
 585                 reg-names = "base", "global_base";
 586                 interrupts = <0 183 4>;
 587                 qcom,mport = <0>;
 588                 qcom,target-dev = <&cpubw>;
 589         };
 590
 591         mincpubw: qcom,mincpubw {
 592                 compatible = "qcom,devbw";
 593                 governor = "powersave";
 594                 qcom,src-dst-ports = <1 512>;
 595                 qcom,active-only;
 596                 qcom,bw-tbl =
 597                         <   762 /*  100 MHz */ >,
 598                         <  1144 /*  150 MHz */ >,
 599                         <  1525 /*  200 MHz */ >,
 600                         <  2288 /*  300 MHz */ >,
 601                         <  3143 /*  412 MHz */ >,
 602                         <  4173 /*  547 MHz */ >,
 603                         <  5195 /*  681 MHz */ >,
 604                         <  5859 /*  768 MHz */ >,
 605                         <  7759 /* 1017 MHz */ >,
 606                         <  9887 /* 1296 MHz */ >,
 607                         < 11863 /* 1555 MHz */ >,
 608                         < 13763 /* 1804 MHz */ >;
 609         };
 610
 611         memlat_cpu0: qcom,memlat-cpu0 {
 612                 compatible = "qcom,devbw";
 613                 governor = "powersave";
 614                 qcom,src-dst-ports = <1 512>;
 615                 qcom,active-only;
 616                 qcom,bw-tbl =
 617                         <  1525 /* 200 MHz */ >,
 618                         <  2288 /* 300 MHz */ >,
 619                         <  3509 /* 460 MHz */ >,
 620                         <  4066 /* 533 MHz */ >,
 621                         <  5126 /* 672 MHz */ >,
 622                         <  5928 /* 777 MHz */ >,
 623                         <  7904 /* 1036 MHz */ >,
 624                         <  9887 /* 1296 MHz */ >,
 625                         < 11863 /* 1555 MHz */ >,
 626                         < 13763 /* 1804 MHz */ >;
 627         };
 628
 629         memlat_cpu2: qcom,memlat-cpu2 {
 630                 compatible = "qcom,devbw";
 631                 governor = "powersave";
 632                 qcom,src-dst-ports = <1 512>;
 633                 qcom,active-only;
 634                 qcom,bw-tbl =
 635                         <  1525 /* 200 MHz */ >,
 636                         <  2288 /* 300 MHz */ >,
 637                         <  3509 /* 460 MHz */ >,
 638                         <  4066 /* 533 MHz */ >,
 639                         <  5126 /* 672 MHz */ >,
 640                         <  5928 /* 777 MHz */ >,
 641                         <  7904 /* 1036 MHz */ >,
 642                         <  9887 /* 1296 MHz */ >,
 643                         < 11863 /* 1555 MHz */ >,
 644                         < 13763 /* 1804 MHz */ >;
 645         };
 646
 647         qcom,arm-memlat-mon-0 {
 648                 compatible = "qcom,arm-memlat-mon";
 649                 qcom,cpulist =  <&CPU0 &CPU1>;
 650                 qcom,target-dev = <&memlat_cpu0>;
 651                 status = "disabled";
 652         };
 653
 654         qcom,arm-memlat-mon-2 {
 655                 compatible = "qcom,arm-memlat-mon";
 656                 qcom,cpulist =  <&CPU2 &CPU3>;
 657                 qcom,target-dev = <&memlat_cpu2>;
 658                 status = "disabled";
 659         };
 660
 661         devfreq_cpufreq: devfreq-cpufreq {
 662                 cpubw-cpufreq {
 663                         target-dev = <&cpubw>;
 664                         cpu-to-dev-map-0 =
 665                                 < 1459200 1525 >;
 666                         cpu-to-dev-map-2 =
 667                                 < 1593600 1525 >;
 668                 };
 669
 670                 m4m-cpufreq {
 671                         target-dev = <&m4m_cache>;
 672                         cpu-to-dev-map-0 =
 673                                 <  345600  307200 >,
 674                                 <  403200  384000 >,
 675                                 <  576000  499200 >,
 676                                 <  633600  595200 >,
 677                                 <  729600  691200 >,
 678                                 <  806400  787200 >,
 679                                 <  883200  883200 >,
 680                                 <  960000  960000 >,
 681                                 < 1459200 1036000 >;
 682                         cpu-to-dev-map-2 =
 683                                 <  345600  307200 >,
 684                                 <  403200  384000 >,
 685                                 <  576000  499200 >,
 686                                 <  633600  595200 >,
 687                                 <  729600  691200 >,
 688                                 <  806400  787200 >,
 689                                 <  883200  883200 >,
 690                                 <  960000  960000 >,
 691                                 < 1593600 1036000 >;
 692                 };
 693
 694                 mincpubw-cpufreq {
 695                         target-dev = <&mincpubw>;
 696                         cpu-to-dev-map-0 =
 697                                 < 1420800 1525 >;
 698                         cpu-to-dev-map-2 =
 699                                 < 1420800 1525 >,
 700                                 < 1593600 5195 >;
 701                 };
 702         };
 703
 704         msm_cpufreq: qcom,msm-cpufreq {
 705                 compatible = "qcom,msm-cpufreq";
 706                 clock-names = "l2_clk", "cpu0_clk", "cpu1_clk", "cpu2_clk",
 707                                 "cpu3_clk";
 708                 clocks = <&clock_cpu clk_cbf_clk>,
 709                          <&clock_cpu clk_pwrcl_clk>,
 710                          <&clock_cpu clk_pwrcl_clk>,
 711                          <&clock_cpu clk_perfcl_clk>,
 712                          <&clock_cpu clk_perfcl_clk>;
 713
 714                 qcom,governor-per-policy;
 715
 716                 qcom,cpufreq-table-0 =
 717                         <  307200 >,
 718                         <  345600 >,
 719                         <  403200 >,
 720                         <  480000 >,
 721                         <  576000 >,
 722                         <  633600 >,
 723                         <  729600 >,
 724                         <  806400 >,
 725                         <  883200 >,
 726                         <  960000 >,
 727                         < 1017600 >,
 728                         < 1113600 >,
 729                         < 1190400 >,
 730                         < 1267200 >,
 731                         < 1344000 >,
 732                         < 1420800 >,
 733                         < 1459200 >;
 734
 735                 qcom,cpufreq-table-2 =
 736                         <  307200 >,
 737                         <  345600 >,
 738                         <  403200 >,
 739                         <  480000 >,
 740                         <  576000 >,
 741                         <  633600 >,
 742                         <  729600 >,
 743                         <  806400 >,
 744                         <  883200 >,
 745                         <  960000 >,
 746                         < 1017600 >,
 747                         < 1113600 >,
 748                         < 1190400 >,
 749                         < 1267200 >,
 750                         < 1344000 >,
 751                         < 1420800 >,
 752                         < 1497600 >,
 753                         < 1593600 >;
 754         };
 755
 756         clock_cpu: qcom,cpu-clock-8996@ {
 757                 compatible = "qcom,cpu-clock-8996";
 758                 reg = <0x06400000 0x1000>,
 759                       <0x06480000 0x1000>,
 760                       <0x09A20000 0x1000>,
 761                       <0x06400000 0x1000>,
 762                       <0x06480000 0x1000>,
 763                       <0x09A11000 0x1000>,
 764                       <0x00074130    0x8>,
 765                       <0x09820000 0x1000>;
 766                 reg-names = "pwrcl_pll", "perfcl_pll", "cbf_pll", "pwrcl_mux", "perfcl_mux", "cbf_mux", "efuse", "debug";
 767                 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
 768                 vdd-perfcl-supply = <&apc1_vreg>;
 769                 vdd-cbf-supply = <&apc0_cbf_vreg>;
 770                 vdd-dig-supply = <&pm8994_s2_corner_ao>;
 771                 cbf-dev = <&m4m_cache>;
 772                 /* please look at msm8996-v3.dtsi for the v3 plan */
 773                 qcom,pwrcl-speedbin0-v0 =
 774                         <          0  0 >,
 775                         <  307200000  3 >,
 776                         <  345600000  4 >,
 777                         <  403200000  5 >,
 778                         <  480000000  6 >,
 779                         <  576000000  7 >,
 780                         <  633600000  8 >,
 781                         <  729600000  9 >,
 782                         <  806400000 10 >,
 783                         <  883200000 11 >,
 784                         <  960000000 12 >,
 785                         < 1017600000 13 >,
 786                         < 1113600000 14 >,
 787                         < 1190400000 15 >,
 788                         < 1267200000 16 >,
 789                         < 1344000000 17 >,
 790                         < 1420800000 18 >,
 791                         < 1459200000 19 >;
 792                 qcom,perfcl-speedbin0-v0 =
 793                         <          0  0 >,
 794                         <  307200000  1 >,
 795                         <  345600000  2 >,
 796                         <  403200000  3 >,
 797                         <  480000000  4 >,
 798                         <  576000000  5 >,
 799                         <  633600000  6 >,
 800                         <  729600000  7 >,
 801                         <  806400000  8 >,
 802                         <  883200000  9 >,
 803                         <  960000000 10 >,
 804                         < 1017600000 11 >,
 805                         < 1113600000 12 >,
 806                         < 1190400000 13 >,
 807                         < 1267200000 14 >,
 808                         < 1344000000 15 >,
 809                         < 1420800000 16 >,
 810                         < 1497600000 17 >,
 811                         < 1593600000 18 >;
 812                 qcom,cbf-speedbin0-v0 =
 813                         <          0  0 >,
 814                         <  307200000  2 >,
 815                         <  384000000  3 >,
 816                         <  499200000  4 >,
 817                         <  595200000  5 >,
 818                         <  691200000  6 >,
 819                         <  787200000  7 >,
 820                         <  883200000  8 >,
 821                         <  960000000  9 >,
 822                         < 1036800000 10 >;
 823                 clock-names = "xo_ao", "aux_clk";
 824                 clocks = <&clock_gcc clk_cxo_clk_src_ao>,
 825                          <&clock_gcc clk_gpll0_ao>;
 826                 #clock-cells = <1>;
 827         };
 828
 829         clock_gcc: qcom,gcc@300000 {
 830                 compatible = "qcom,gcc-8996";
 831                 reg = <0x300000 0x8f014>;
 832                 reg-names = "cc_base";
 833                 vdd_dig-supply = <&pm8994_s1_corner>;
 834                 #clock-cells = <1>;
 835                 #reset-cells = <1>;
 836         };
 837
 838         clock_mmss: qcom,mmsscc@8c0000 {
 839                 compatible = "qcom,mmsscc-8996";
 840                 reg = <0x8c0000 0xb00c>,
 841                         <0x74130 0x8>;
 842                 reg-names = "cc_base", "efuse";
 843                 vdd_dig-supply = <&pm8994_s1_corner>;
 844                 mmpll4_dig-supply = <&pm8994_s1_corner>;
 845                 mmpll4_analog-supply = <&pm8994_l12>;
 846                 qcom,vfe0_clk_src-opp-store-vcorner = <&vfe0>;
 847                 qcom,vfe1_clk_src-opp-store-vcorner = <&vfe1>;
 848                 qcom,cpp_clk_src-opp-store-vcorner = <&cpp>;
 849                 clock-names = "xo", "gpll0", "gpll0_div",
 850                                 "pclk0_src", "pclk1_src",
 851                                 "byte0_src", "byte1_src",
 852                                 "extpclk_src";
 853                 clocks = <&clock_gcc clk_cxo_clk_src>,
 854                          <&clock_gcc clk_gpll0_out_main>,
 855                          <&clock_gcc clk_gcc_mmss_gpll0_div_clk>,
 856                          <&mdss_dsi0_pll clk_dsi0pll_pixel_clk_mux>,
 857                          <&mdss_dsi1_pll clk_dsi1pll_pixel_clk_mux>,
 858                          <&mdss_dsi0_pll clk_dsi0pll_byte_clk_mux>,
 859                          <&mdss_dsi1_pll clk_dsi1pll_byte_clk_mux>,
 860                         <&mdss_hdmi_pll clk_hdmi_vco_clk>;
 861                 #clock-cells = <1>;
 862                 #reset-cells = <1>;
 863         };
 864
 865         clock_gpu: qcom,gpucc@8c0000 {
 866                 compatible = "qcom,gpucc-8996";
 867                 reg = <0x8c0000 0xb00c>;
 868                 reg-names = "cc_base";
 869                 vdd_gfx-supply = <&gfx_vreg>;
 870                 qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>;
 871                 vdd_mx-supply = <&pm8994_s2_corner>;
 872                 vdd_gpu_mx-supply = <&pm8994_s2_corner>;
 873                 qcom,gfxfreq-speedbin0 =
 874                         <          0  0  0 >,
 875                         <   19200000  3  4 >,
 876                         <   60000000  3  4 >,
 877                         <  120000000  3  4 >,
 878                         <  205000000  3  4 >,
 879                         <  360000000  4  5 >,
 880                         <  480000000  5  7 >;
 881                 qcom,gfxfreq-mx-speedbin0 =
 882                         <          0  0 >,
 883                         <   19200000  4 >,
 884                         <   60000000  4 >,
 885                         <  120000000  4 >,
 886                         <  205000000  4 >,
 887                         <  360000000  5 >,
 888                         <  480000000  7 >;
 889                 #clock-cells = <1>;
 890         };
 891
 892         clock_debug: qcom,cc-debug@362000 {
 893                 compatible = "qcom,cc-debug-8996";
 894                 reg = <0x362000 0x4>;
 895                 reg-names = "cc_base";
 896                 clock-names = "debug_mmss_clk", "debug_gpu_clk", "debug_cpu_clk";
 897                 clocks = <&clock_mmss clk_mmss_gcc_dbg_clk>,
 898                          <&clock_gpu clk_gpu_gcc_dbg_clk>,
 899                          <&clock_cpu clk_cpu_debug_mux>;
 900                 #clock-cells = <1>;
 901         };
 902
 903         qcom,rmtfs_sharedmem@0 {
 904                 compatible = "qcom,sharedmem-uio";
 905                 reg = <0x0 0x00200000>;
 906                 reg-names = "rmtfs";
 907                 qcom,client-id = <0x00000001>;
 908         };
 909
 910         wcd9xxx_intc: wcd9xxx-irq {
 911                 compatible = "qcom,wcd9xxx-irq";
 912                 interrupt-controller;
 913                 #interrupt-cells = <1>;
 914                 interrupt-parent = <&tlmm>;
 915                 qcom,gpio-connect = <&tlmm 54 0>;
 916                 pinctrl-names = "default";
 917                 pinctrl-0 = <&wcd_intr_default>;
 918         };
 919
 920         clock_audio: audio_ext_clk {
 921                 compatible = "qcom,audio-ref-clk";
 922                 qcom,audio-ref-clk-gpio = <&pm8994_gpios 15 0>;
 923                 clock-names = "osr_clk";
 924                 clocks = <&clock_gcc clk_div_clk1>;
 925                 qcom,node_has_rpm_clock;
 926                 #clock-cells = <1>;
 927                 pinctrl-names = "sleep", "active";
 928                 pinctrl-0 = <&spkr_i2s_clk_sleep>;
 929                 pinctrl-1 = <&spkr_i2s_clk_active>;
 930         };
 931
 932         tspp: msm_tspp@075e7000 {
 933                 compatible = "qcom,msm_tspp";
 934                 reg = <0x075e7000 0x1000>, /* MSM_TSIF0_PHYS */
 935                       <0x075e8000 0x1000>, /* MSM_TSIF1_PHYS */
 936                       <0x075e9000 0x1000>, /* MSM_TSPP_PHYS  */
 937                       <0x075c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */
 938                 reg-names = "MSM_TSIF0_PHYS",
 939                         "MSM_TSIF1_PHYS",
 940                         "MSM_TSPP_PHYS",
 941                         "MSM_TSPP_BAM_PHYS";
 942                 interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */
 943                         <0 119 0>, /* TSIF0_IRQ */
 944                         <0 120 0>, /* TSIF1_IRQ */
 945                         <0 122 0>; /* TSIF_BAM_IRQ */
 946                 interrupt-names = "TSIF_TSPP_IRQ",
 947                         "TSIF0_IRQ",
 948                         "TSIF1_IRQ",
 949                         "TSIF_BAM_IRQ";
 950
 951                 clock-names = "iface_clk", "ref_clk";
 952                 clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>,
 953                         <&clock_gcc clk_gcc_tsif_ref_clk>;
 954
 955                 qcom,msm-bus,name = "tsif";
 956                 qcom,msm-bus,num-cases = <2>;
 957                 qcom,msm-bus,num-paths = <1>;
 958                 qcom,msm-bus,vectors-KBps =
 959                                 <82 512 0 0>, /* No vote */
 960                                 <82 512 12288 24576>; /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
 961
 962                 pinctrl-names = "disabled",
 963                         "tsif0-mode1", "tsif0-mode2",
 964                         "tsif1-mode1", "tsif1-mode2",
 965                         "dual-tsif-mode1", "dual-tsif-mode2";
 966
 967                 pinctrl-0 = <>;                         /* disabled */
 968                 pinctrl-1 = <&tsif0_signals_active>;    /* tsif0-mode1 */
 969                 pinctrl-2 = <&tsif0_signals_active
 970                         &tsif0_sync_active>;            /* tsif0-mode2 */
 971                 pinctrl-3 = <&tsif1_signals_active>;    /* tsif1-mode1 */
 972                 pinctrl-4 = <&tsif1_signals_active
 973                         &tsif1_sync_active>;            /* tsif1-mode2 */
 974                 pinctrl-5 = <&tsif0_signals_active
 975                         &tsif1_signals_active>;         /* dual-tsif-mode1 */
 976                 pinctrl-6 = <&tsif0_signals_active
 977                         &tsif0_sync_active
 978                         &tsif1_signals_active
 979                         &tsif1_sync_active>;            /* dual-tsif-mode2 */
 980         };
 981
 982         wcd_rst_gpio: msm_cdc_pinctrl@64 {
 983                 compatible = "qcom,msm-cdc-pinctrl";
 984                 qcom,cdc-rst-n-gpio = <&tlmm 64 0>;
 985                 pinctrl-names = "aud_active", "aud_sleep";
 986                 pinctrl-0 = <&cdc_reset_active>;
 987                 pinctrl-1 = <&cdc_reset_sleep>;
 988         };
 989
 990         slim_msm: slim@91c0000 {
 991                 cell-index = <1>;
 992                 compatible = "qcom,slim-ngd";
 993                 reg = <0x91c0000 0x2C000>,
 994                         <0x9184000 0x32000>;
 995                 reg-names = "slimbus_physical", "slimbus_bam_physical";
 996                 interrupts = <0 163 0>, <0 164 0>;
 997                 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
 998                 qcom,apps-ch-pipes = <0x60000000>;
 999                 qcom,ea-pc = <0x160>;
1000
1001                 msm_dai_slim {
1002                         compatible = "qcom,msm-dai-slim";
1003                         elemental-addr = [ff ff ff fe 17 02];
1004                 };
1005
1006                 tasha_codec {
1007                         compatible = "qcom,tasha-slim-pgd";
1008                         elemental-addr = [00 01 A0 01 17 02];
1009
1010                         interrupt-parent = <&wcd9xxx_intc>;
1011                         interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
1012                                       17 18 19 20 21 22 23 24 25 26 27 28 29
1013                                       30>;
1014
1015                         qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
1016
1017                         clock-names = "wcd_clk", "wcd_native_clk";
1018                         clocks = <&clock_audio clk_audio_pmi_clk>,
1019                                  <&clock_audio clk_audio_ap_clk2>;
1020
1021                         cdc-vdd-buck-supply = <&pm8994_s4>;
1022                         qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
1023                         qcom,cdc-vdd-buck-current = <650000>;
1024
1025                         cdc-buck-sido-supply = <&pm8994_s4>;
1026                         qcom,cdc-buck-sido-voltage = <1800000 1800000>;
1027                         qcom,cdc-buck-sido-current = <250000>;
1028
1029                         cdc-vdd-tx-h-supply = <&pm8994_s4>;
1030                         qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>;
1031                         qcom,cdc-vdd-tx-h-current = <25000>;
1032
1033                         cdc-vdd-rx-h-supply = <&pm8994_s4>;
1034                         qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>;
1035                         qcom,cdc-vdd-rx-h-current = <25000>;
1036
1037                         cdc-vddpx-1-supply = <&pm8994_s4>;
1038                         qcom,cdc-vddpx-1-voltage = <1800000 1800000>;
1039                         qcom,cdc-vddpx-1-current = <10000>;
1040
1041                         qcom,cdc-static-supplies = "cdc-vdd-buck",
1042                                                    "cdc-buck-sido",
1043                                                    "cdc-vdd-tx-h",
1044                                                    "cdc-vdd-rx-h",
1045                                                    "cdc-vddpx-1";
1046
1047                         qcom,cdc-micbias1-mv = <1800>;
1048                         qcom,cdc-micbias2-mv = <1800>;
1049                         qcom,cdc-micbias3-mv = <1800>;
1050                         qcom,cdc-micbias4-mv = <1800>;
1051
1052                         qcom,cdc-mclk-clk-rate = <9600000>;
1053                         qcom,cdc-slim-ifd = "tasha-slim-ifd";
1054                         qcom,cdc-slim-ifd-elemental-addr = [00 00 A0 01 17 02];
1055                         qcom,cdc-dmic-sample-rate = <4800000>;
1056                         qcom,cdc-mad-dmic-rate = <600000>;
1057                         qcom,cdc-ecpp-dmic-rate = <1200000>;
1058                         qcom,cdc-dmic-clk-drv-strength = <2>;
1059                 };
1060         };
1061
1062         sdhc_1: sdhci@7464900 {
1063                 compatible = "qcom,sdhci-msm";
1064                 reg = <0x7464900 0x500>, <0x7464000 0x800>, <0x7464E00 0x19C>;
1065                 reg-names = "hc_mem", "core_mem", "cmdq_mem";
1066
1067                 interrupts = <0 141 0>, <0 134 0>;
1068                 interrupt-names = "hc_irq", "pwr_irq";
1069
1070                 clock-names = "iface_clk", "core_clk", "ice_core_clk";
1071                 clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
1072                          <&clock_gcc clk_gcc_sdcc1_apps_clk>,
1073                          <&clock_gcc clk_gcc_sdcc1_ice_core_clk>;
1074
1075                 sdhc-msm-crypto = <&sdcc1_ice>;
1076                 qcom,large-address-bus;
1077                 qcom,bus-width = <8>;
1078
1079                 qcom,devfreq,freq-table = <20000000 200000000>;
1080
1081                 qcom,msm-bus,name = "sdhc1";
1082                 qcom,msm-bus,num-cases = <9>;
1083                 qcom,msm-bus,num-paths = <1>;
1084                 qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
1085                         <78 512 1600 3200>,       /* 400 KB/s*/
1086                         <78 512 80000 160000>,    /* 20 MB/s */
1087                         <78 512 100000 200000>,   /* 25 MB/s */
1088                         <78 512 200000 400000>,   /* 50 MB/s */
1089                         <78 512 400000 800000>,   /* 100 MB/s */
1090                         <78 512 400000 800000>,   /* 200 MB/s */
1091                         <78 512 400000 800000>,   /* 400 MB/s */
1092                         <78 512 2048000 4096000>; /* Max. bandwidth */
1093                 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1094                                                 100000000 200000000 400000000
1095                                                 4294967295>;
1096
1097                 qcom,pm-qos-cpu-groups = <0x03 0x0c>;
1098                 qcom,pm-qos-cmdq-latency-us = <70 70>, <70 70>;
1099                 qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>;
1100                 qcom,pm-qos-irq-type = "affine_cores";
1101                 qcom,pm-qos-irq-cpu = <0>;
1102                 qcom,pm-qos-irq-latency = <70 70>;
1103
1104                 non-removable;
1105                 status = "disabled";
1106         };
1107
1108         sdhc_2: sdhci@74A4900 {
1109                 compatible = "qcom,sdhci-msm";
1110                 reg = <0x74A4900 0x314>, <0x74A4000 0x800>;
1111                 reg-names = "hc_mem", "core_mem";
1112
1113                 interrupts = <0 125 0>, <0 221 0>;
1114                 interrupt-names = "hc_irq", "pwr_irq";
1115
1116                 clock-names = "iface_clk", "core_clk";
1117                 clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
1118                          <&clock_gcc clk_gcc_sdcc2_apps_clk>;
1119
1120                 qcom,large-address-bus;
1121                 qcom,bus-width = <4>;
1122
1123                 qcom,devfreq,freq-table = <20000000 200000000>;
1124
1125                 qcom,msm-bus,name = "sdhc2";
1126                 qcom,msm-bus,num-cases = <8>;
1127                 qcom,msm-bus,num-paths = <1>;
1128                 qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
1129                                 <81 512 1600 3200>,    /* 400 KB/s*/
1130                                 <81 512 80000 160000>, /* 20 MB/s */
1131                                 <81 512 100000 200000>, /* 25 MB/s */
1132                                 <81 512 200000 400000>, /* 50 MB/s */
1133                                 <81 512 400000 800000>, /* 100 MB/s */
1134                                 <81 512 800000 800000>, /* 200 MB/s */
1135                                 <81 512 2048000 4096000>; /* Max. bandwidth */
1136                 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1137                                                 100000000 200000000 4294967295>;
1138
1139                 qcom,pm-qos-cpu-groups = <0x03 0x0c>;
1140                 qcom,pm-qos-legacy-latency-us = <70 70>, <70 70>;
1141                 qcom,pm-qos-irq-type = "affine_cores";
1142                 qcom,pm-qos-irq-cpu = <0>;
1143                 qcom,pm-qos-irq-latency = <70 70>;
1144
1145                 status = "disabled";
1146         };
1147
1148         ufs_ice: ufsice@630000 {
1149                 compatible = "qcom,ice";
1150                 reg = <0x630000 0x8000>;
1151                 interrupt-names = "ufs_ice_nonsec_level_irq";
1152                 interrupts = <0 258 0>;
1153                 qcom,enable-ice-clk;
1154                 clock-names =   "ufs_core_clk_src",
1155                                 "ufs_core_clk",
1156                                 "bus_clk",
1157                                 "iface_clk",
1158                                 "ice_core_clk_src",
1159                                 "ice_core_clk";
1160                 clocks = <&clock_gcc clk_ufs_axi_clk_src>,
1161                          <&clock_gcc clk_gcc_ufs_axi_clk>,
1162                          <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
1163                          <&clock_gcc clk_gcc_ufs_ahb_clk>,
1164                          <&clock_gcc clk_ufs_ice_core_clk_src>,
1165                          <&clock_gcc clk_gcc_ufs_ice_core_clk>;
1166                 qcom,op-freq-hz = <0>, <0>, <0>,<0>,
1167                                  <300000000>, <0>;
1168                 vdd-hba-supply = <&gdsc_ufs>;
1169                 qcom,msm-bus,name = "ufs_ice_noc";
1170                 qcom,msm-bus,num-cases = <2>;
1171                 qcom,msm-bus,num-paths = <1>;
1172                 qcom,msm-bus,vectors-KBps =
1173                                 <1 650 0 0>,    /* No vote */
1174                                 <1 650 1000 0>; /* Max. bandwidth */
1175                 qcom,bus-vector-names = "MIN",
1176                                         "MAX";
1177                 qcom,instance-type = "ufs";
1178                 status = "disabled";
1179         };
1180
1181         sdcc1_ice: sdcc1ice@7443000 {
1182                 compatible = "qcom,ice";
1183                 reg = <0x7443000 0x8000>;
1184                 interrupt-names = "sdcc_ice_nonsec_level_irq";
1185                 interrupts = <0 461 0>;
1186                 qcom,enable-ice-clk;
1187                 clock-names = "ice_core_clk_src", "ice_core_clk",
1188                                 "bus_clk", "iface_clk";
1189                 clocks = <&clock_gcc clk_sdcc1_ice_core_clk_src>,
1190                          <&clock_gcc clk_gcc_sdcc1_ice_core_clk>,
1191                          <&clock_gcc clk_gcc_sdcc1_apps_clk>,
1192                          <&clock_gcc clk_gcc_sdcc1_ahb_clk>;
1193                 qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
1194                 qcom,msm-bus,name = "sdcc_ice_noc";
1195                 qcom,msm-bus,num-cases = <2>;
1196                 qcom,msm-bus,num-paths = <1>;
1197                 qcom,msm-bus,vectors-KBps =
1198                         <78 512 0 0>,    /* No vote */
1199                         <78 512 1000 0>; /* Max. bandwidth */
1200                 qcom,bus-vector-names = "MIN",
1201                                         "MAX";
1202                 qcom,instance-type = "sdcc";
1203                 status = "disabled";
1204         };
1205
1206         ufsphy1: ufsphy@627000 {
1207                 compatible = "qcom,ufs-phy-qmp-14nm";
1208                 reg = <0x627000 0xda8>;
1209                 reg-names = "phy_mem";
1210                 #phy-cells = <0>;
1211                 vdda-phy-supply = <&pm8994_l28>;
1212                 vdda-pll-supply = <&pm8994_l12>;
1213                 vdda-phy-max-microamp = <18380>;
1214                 vdda-pll-max-microamp = <9440>;
1215                 vddp-ref-clk-supply = <&pm8994_l25>;
1216                 vddp-ref-clk-max-microamp = <100>;
1217                 vddp-ref-clk-always-on;
1218                 clock-names = "ref_clk_src",
1219                         "ref_clk";
1220                 clocks = <&clock_gcc clk_ln_bb_clk>,
1221                         <&clock_gcc clk_gcc_ufs_clkref_clk>;
1222                 status = "disabled";
1223         };
1224
1225         ufs1: ufshc@624000 {
1226                 compatible = "qcom,ufshc";
1227                 reg = <0x624000 0x2500>;
1228                 interrupts = <0 265 0>;
1229                 phys = <&ufsphy1>;
1230                 phy-names = "ufsphy";
1231                 ufs-qcom-crypto = <&ufs_ice>;
1232                 vdd-hba-supply = <&gdsc_ufs>;
1233                 vdd-hba-fixed-regulator;
1234                 vcc-supply = <&pm8994_l20>;
1235                 vccq-supply = <&pm8994_l25>;
1236                 vccq2-supply = <&pm8994_s4>;
1237                 vcc-max-microamp = <600000>;
1238                 vccq-max-microamp = <450000>;
1239                 vccq2-max-microamp = <450000>;
1240
1241                 clock-names =
1242                         "core_clk_src",
1243                         "core_clk",
1244                         "bus_clk",
1245                         "bus_aggr_clk",
1246                         "iface_clk",
1247                         "core_clk_unipro_src",
1248                         "core_clk_unipro",
1249                         "core_clk_ice",
1250                         "ref_clk",
1251                         "tx_lane0_sync_clk",
1252                         "rx_lane0_sync_clk";
1253                 clocks =
1254                         <&clock_gcc clk_ufs_axi_clk_src>,
1255                         <&clock_gcc clk_gcc_ufs_axi_clk>,
1256                         <&clock_gcc clk_gcc_sys_noc_ufs_axi_clk>,
1257                         <&clock_gcc clk_gcc_aggre2_ufs_axi_clk>,
1258                         <&clock_gcc clk_gcc_ufs_ahb_clk>,
1259                         <&clock_gcc clk_ufs_ice_core_clk_src>,
1260                         <&clock_gcc clk_gcc_ufs_unipro_core_clk>,
1261                         <&clock_gcc clk_gcc_ufs_ice_core_clk>,
1262                         <&clock_gcc clk_ln_bb_clk>,
1263                         <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
1264                         <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;
1265                 freq-table-hz =
1266                         <100000000 200000000>,
1267                         <0 0>,
1268                         <0 0>,
1269                         <0 0>,
1270                         <0 0>,
1271                         <150000000 300000000>,
1272                         <0 0>,
1273                         <0 0>,
1274                         <0 0>,
1275                         <0 0>,
1276                         <0 0>;
1277
1278                 lanes-per-direction = <1>;
1279                 qcom,msm-bus,name = "ufs1";
1280                 qcom,msm-bus,num-cases = <12>;
1281                 qcom,msm-bus,num-paths = <2>;
1282                 qcom,msm-bus,vectors-KBps =
1283                 <95 512 0 0>, <1 650 0 0>,          /* No vote */
1284                 <95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */
1285                 <95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */
1286                 <95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */
1287                 <95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */
1288                 <95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */
1289                 <95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */
1290                 <95 512 511181 0>, <1 650 1000 0>,  /* HS G3 RA */
1291                 <95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */
1292                 <95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */
1293                 <95 512 596378 0>, <1 650 1000 0>,  /* HS G3 RB */
1294                 <95 512 4096000 0>, <1 650 1000 0>; /* Max. bandwidth */
1295                 qcom,bus-vector-names = "MIN",
1296                 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1297                 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1298                 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1299                 "MAX";
1300
1301                 resets = <&clock_gcc UFS_BCR>;
1302                 reset-names = "core_reset";
1303
1304                 /* PM QoS */
1305                 qcom,pm-qos-cpu-groups = <0x03 0x0C>;
1306                 qcom,pm-qos-cpu-group-latency-us = <70 70>;
1307                 qcom,pm-qos-default-cpu = <0>;
1308
1309                 non-removable;
1310                 status = "disabled";
1311         };
1312
1313         pcie0: qcom,pcie@00600000 {
1314                 compatible = "qcom,pci-msm";
1315                 cell-index = <0>;
1316
1317                 reg = <0x00600000 0x2000>,
1318                       <0x00034000 0x4000>,
1319                       <0x0c000000 0xf1d>,
1320                       <0x0c000f20 0xa8>,
1321                       <0x0c100000 0x100000>,
1322                       <0x0c200000 0x100000>,
1323                       <0x0c300000 0xd00000>;
1324
1325                 reg-names = "parf", "phy", "dm_core", "elbi",
1326                                 "conf", "io", "bars";
1327
1328                 #address-cells = <3>;
1329                 #size-cells = <2>;
1330                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1331                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1332                 interrupt-parent = <&pcie0>;
1333                 interrupts =    <0 1 2 3 4 5 6 7 8 9 10 11
1334                                 12 13 14 15 16 17 18 19 20
1335                                 21 22 23 24 25 26 27 28 29
1336                                 30 31 32 33 34 35 36 37 38
1337                                 39 40 41 42 43>;
1338                 #interrupt-cells = <1>;
1339                 interrupt-map-mask = <0x0 0x0 0x0 0xffffffff>;
1340                 interrupt-map = <0x0 0x0 0x0 0 &intc 0 0 405 0
1341                                 0x0 0x0 0x0 1 &intc 0 0 244 0
1342                                 0x0 0x0 0x0 2 &intc 0 0 245 0
1343                                 0x0 0x0 0x0 3 &intc 0 0 247 0
1344                                 0x0 0x0 0x0 4 &intc 0 0 248 0
1345                                 0x0 0x0 0x0 5 &intc 0 0 249 0
1346                                 0x0 0x0 0x0 6 &intc 0 0 250 0
1347                                 0x0 0x0 0x0 7 &intc 0 0 251 0
1348                                 0x0 0x0 0x0 8 &intc 0 0 252 0
1349                                 0x0 0x0 0x0 9 &intc 0 0 253 0
1350                                 0x0 0x0 0x0 10 &intc 0 0 254 0
1351                                 0x0 0x0 0x0 11 &intc 0 0 255 0
1352                                 0x0 0x0 0x0 12 &intc 0 0 512 0
1353                                 0x0 0x0 0x0 13 &intc 0 0 513 0
1354                                 0x0 0x0 0x0 14 &intc 0 0 514 0
1355                                 0x0 0x0 0x0 15 &intc 0 0 515 0
1356                                 0x0 0x0 0x0 16 &intc 0 0 516 0
1357                                 0x0 0x0 0x0 17 &intc 0 0 517 0
1358                                 0x0 0x0 0x0 18 &intc 0 0 518 0
1359                                 0x0 0x0 0x0 19 &intc 0 0 519 0
1360                                 0x0 0x0 0x0 20 &intc 0 0 520 0
1361                                 0x0 0x0 0x0 21 &intc 0 0 521 0
1362                                 0x0 0x0 0x0 22 &intc 0 0 522 0
1363                                 0x0 0x0 0x0 23 &intc 0 0 523 0
1364                                 0x0 0x0 0x0 24 &intc 0 0 524 0
1365                                 0x0 0x0 0x0 25 &intc 0 0 525 0
1366                                 0x0 0x0 0x0 26 &intc 0 0 526 0
1367                                 0x0 0x0 0x0 27 &intc 0 0 527 0
1368                                 0x0 0x0 0x0 28 &intc 0 0 528 0
1369                                 0x0 0x0 0x0 29 &intc 0 0 529 0
1370                                 0x0 0x0 0x0 30 &intc 0 0 530 0
1371                                 0x0 0x0 0x0 31 &intc 0 0 531 0
1372                                 0x0 0x0 0x0 32 &intc 0 0 532 0
1373                                 0x0 0x0 0x0 33 &intc 0 0 533 0
1374                                 0x0 0x0 0x0 34 &intc 0 0 534 0
1375                                 0x0 0x0 0x0 35 &intc 0 0 535 0
1376                                 0x0 0x0 0x0 36 &intc 0 0 536 0
1377                                 0x0 0x0 0x0 37 &intc 0 0 537 0
1378                                 0x0 0x0 0x0 38 &intc 0 0 538 0
1379                                 0x0 0x0 0x0 39 &intc 0 0 539 0
1380                                 0x0 0x0 0x0 40 &intc 0 0 540 0
1381                                 0x0 0x0 0x0 41 &intc 0 0 541 0
1382                                 0x0 0x0 0x0 42 &intc 0 0 542 0
1383                                 0x0 0x0 0x0 43 &intc 0 0 543 0>;
1384
1385                 interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
1386                                 "int_pls_pme", "int_pme_legacy", "int_pls_err",
1387                                 "int_aer_legacy", "int_pls_link_up",
1388                                 "int_pls_link_down", "int_bridge_flush_n",
1389                                 "msi_0", "msi_1", "msi_2", "msi_3",
1390                                 "msi_4", "msi_5", "msi_6", "msi_7",
1391                                 "msi_8", "msi_9", "msi_10", "msi_11",
1392                                 "msi_12", "msi_13", "msi_14", "msi_15",
1393                                 "msi_16", "msi_17", "msi_18", "msi_19",
1394                                 "msi_20", "msi_21", "msi_22", "msi_23",
1395                                 "msi_24", "msi_25", "msi_26", "msi_27",
1396                                 "msi_28", "msi_29", "msi_30", "msi_31";
1397
1398                 pinctrl-names = "default", "sleep";
1399                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1400                 pinctrl-1 = <&pcie0_clkreq_sleep
1401                         &pcie0_perst_default
1402                         &pcie0_wake_sleep>;
1403
1404                 perst-gpio = <&tlmm 35 0>;
1405                 wake-gpio = <&tlmm 37 0>;
1406
1407                 gdsc-smmu-supply = <&gdsc_aggre0_noc>;
1408                 gdsc-vdd-supply = <&gdsc_pcie_0>;
1409                 vreg-1.8-supply = <&pm8994_l12>;
1410                 vreg-0.9-supply = <&pm8994_l28>;
1411                 vreg-cx-supply = <&pm8994_s1_corner>;
1412
1413                 qcom,vreg-0.9-voltage-level = <925000 925000 24000>;
1414                 qcom,vreg-cx-voltage-level = <7 4 0>;
1415
1416                 qcom,l1-supported;
1417                 qcom,l1ss-supported;
1418                 qcom,aux-clk-sync;
1419
1420                 qcom,ep-latency = <10>;
1421
1422                 qcom,common-phy;
1423                 qcom,smmu-exist;
1424
1425                 iommus = <&anoc0_smmu>;
1426
1427                 qcom,boot-option = <0x1>;
1428
1429                 linux,pci-domain = <0>;
1430
1431                 qcom,msi-gicm-addr = <0x09BD0040>;
1432                 qcom,msi-gicm-base = <0x220>;
1433
1434                 qcom,msm-bus,name = "pcie0";
1435                 qcom,msm-bus,num-cases = <2>;
1436                 qcom,msm-bus,num-paths = <1>;
1437                 qcom,msm-bus,vectors-KBps =
1438                                 <45 512 0 0>,
1439                                 <45 512 500 800>;
1440
1441                 clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
1442                         <&clock_gcc clk_ln_bb_clk>,
1443                         <&clock_gcc clk_gcc_pcie_0_aux_clk>,
1444                         <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
1445                         <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
1446                         <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
1447                         <&clock_gcc clk_gcc_pcie_clkref_clk>,
1448                         <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
1449                         <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
1450                         <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
1451
1452                 clock-names =  "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk",
1453                         "pcie_0_cfg_ahb_clk", "pcie_0_mstr_axi_clk",
1454                         "pcie_0_slv_axi_clk", "pcie_0_ldo", "pcie_0_smmu_clk",
1455                         "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
1456
1457                 resets = <&clock_gcc PCIE_PHY_BCR>,
1458                         <&clock_gcc PCIE_PHY_COM_BCR>,
1459                         <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
1460                         <&clock_gcc PCIE_0_PHY_BCR>;
1461
1462                 reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
1463                         "pcie_phy_nocsr_com_phy_reset","pcie_0_phy_reset";
1464
1465                 max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
1466                                          <0>, <0>, <0>, <0>, <0>, <0>, <0>;
1467         };
1468
1469         pcie1: qcom,pcie@00608000 {
1470                 compatible = "qcom,pci-msm";
1471                 cell-index = <1>;
1472
1473                 reg = <0x00608000 0x2000>,
1474                       <0x00034000 0x4000>,
1475                       <0x0d000000 0xf1d>,
1476                       <0x0d000f20 0xa8>,
1477                       <0x0d100000 0x100000>,
1478                       <0x0d200000 0x100000>,
1479                       <0x0d300000 0xd00000>;
1480
1481                 reg-names = "parf", "phy", "dm_core", "elbi",
1482                                 "conf", "io", "bars";
1483
1484                 #address-cells = <3>;
1485                 #size-cells = <2>;
1486                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1487                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1488                 interrupt-parent = <&pcie1>;
1489                 interrupts =    <0 1 2 3 4 5 6 7 8 9 10 11
1490                                 12 13 14 15 16 17 18 19 20
1491                                 21 22 23 24 25 26 27 28 29
1492                                 30 31 32 33 34 35 36 37 38
1493                                 39 40 41 42 43>;
1494                 #interrupt-cells = <1>;
1495                 interrupt-map-mask = <0x0 0x0 0x0 0xffffffff>;
1496                 interrupt-map = <0x0 0x0 0x0 0 &intc 0 0 413 0
1497                                 0x0 0x0 0x0 1 &intc 0 0 272 0
1498                                 0x0 0x0 0x0 2 &intc 0 0 273 0
1499                                 0x0 0x0 0x0 3 &intc 0 0 274 0
1500                                 0x0 0x0 0x0 4 &intc 0 0 275 0
1501                                 0x0 0x0 0x0 5 &intc 0 0 276 0
1502                                 0x0 0x0 0x0 6 &intc 0 0 277 0
1503                                 0x0 0x0 0x0 7 &intc 0 0 278 0
1504                                 0x0 0x0 0x0 8 &intc 0 0 279 0
1505                                 0x0 0x0 0x0 9 &intc 0 0 280 0
1506                                 0x0 0x0 0x0 10 &intc 0 0 281 0
1507                                 0x0 0x0 0x0 11 &intc 0 0 282 0
1508                                 0x0 0x0 0x0 12 &intc 0 0 544 0
1509                                 0x0 0x0 0x0 13 &intc 0 0 545 0
1510                                 0x0 0x0 0x0 14 &intc 0 0 546 0
1511                                 0x0 0x0 0x0 15 &intc 0 0 547 0
1512                                 0x0 0x0 0x0 16 &intc 0 0 548 0
1513                                 0x0 0x0 0x0 17 &intc 0 0 549 0
1514                                 0x0 0x0 0x0 18 &intc 0 0 550 0
1515                                 0x0 0x0 0x0 19 &intc 0 0 551 0
1516                                 0x0 0x0 0x0 20 &intc 0 0 552 0
1517                                 0x0 0x0 0x0 21 &intc 0 0 553 0
1518                                 0x0 0x0 0x0 22 &intc 0 0 554 0
1519                                 0x0 0x0 0x0 23 &intc 0 0 555 0
1520                                 0x0 0x0 0x0 24 &intc 0 0 556 0
1521                                 0x0 0x0 0x0 25 &intc 0 0 557 0
1522                                 0x0 0x0 0x0 26 &intc 0 0 558 0
1523                                 0x0 0x0 0x0 27 &intc 0 0 559 0
1524                                 0x0 0x0 0x0 28 &intc 0 0 560 0
1525                                 0x0 0x0 0x0 29 &intc 0 0 561 0
1526                                 0x0 0x0 0x0 30 &intc 0 0 562 0
1527                                 0x0 0x0 0x0 31 &intc 0 0 563 0
1528                                 0x0 0x0 0x0 32 &intc 0 0 564 0
1529                                 0x0 0x0 0x0 33 &intc 0 0 565 0
1530                                 0x0 0x0 0x0 34 &intc 0 0 566 0
1531                                 0x0 0x0 0x0 35 &intc 0 0 567 0
1532                                 0x0 0x0 0x0 36 &intc 0 0 568 0
1533                                 0x0 0x0 0x0 37 &intc 0 0 569 0
1534                                 0x0 0x0 0x0 38 &intc 0 0 570 0
1535                                 0x0 0x0 0x0 39 &intc 0 0 571 0
1536                                 0x0 0x0 0x0 40 &intc 0 0 572 0
1537                                 0x0 0x0 0x0 41 &intc 0 0 573 0
1538                                 0x0 0x0 0x0 42 &intc 0 0 574 0
1539                                 0x0 0x0 0x0 43 &intc 0 0 575 0>;
1540
1541                 interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
1542                                 "int_pls_pme", "int_pme_legacy", "int_pls_err",
1543                                 "int_aer_legacy", "int_pls_link_up",
1544                                 "int_pls_link_down", "int_bridge_flush_n",
1545                                 "msi_0", "msi_1", "msi_2", "msi_3",
1546                                 "msi_4", "msi_5", "msi_6", "msi_7",
1547                                 "msi_8", "msi_9", "msi_10", "msi_11",
1548                                 "msi_12", "msi_13", "msi_14", "msi_15",
1549                                 "msi_16", "msi_17", "msi_18", "msi_19",
1550                                 "msi_20", "msi_21", "msi_22", "msi_23",
1551                                 "msi_24", "msi_25", "msi_26", "msi_27",
1552                                 "msi_28", "msi_29", "msi_30", "msi_31";
1553
1554                 pinctrl-names = "default", "sleep";
1555                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1556                 pinctrl-1 = <&pcie1_clkreq_sleep
1557                         &pcie1_perst_default
1558                         &pcie1_wake_sleep>;
1559
1560                 perst-gpio = <&tlmm 130 0>;
1561
1562                 gdsc-smmu-supply = <&gdsc_aggre0_noc>;
1563                 gdsc-vdd-supply = <&gdsc_pcie_1>;
1564                 vreg-1.8-supply = <&pm8994_l12>;
1565                 vreg-0.9-supply = <&pm8994_l28>;
1566                 vreg-cx-supply = <&pm8994_s1_corner>;
1567
1568                 qcom,vreg-0.9-voltage-level = <925000 925000 24000>;
1569                 qcom,vreg-cx-voltage-level = <7 5 0>;
1570
1571                 qcom,l1-supported;
1572                 qcom,l1ss-supported;
1573                 qcom,aux-clk-sync;
1574
1575                 qcom,common-phy;
1576                 qcom,smmu-exist;
1577
1578                 iommus = <&anoc0_smmu>;
1579
1580                 qcom,boot-option = <0x1>;
1581
1582                 qcom,ep-latency = <10>;
1583
1584                 linux,pci-domain = <1>;
1585
1586                 qcom,msm-bus,name = "pcie1";
1587                 qcom,msm-bus,num-cases = <2>;
1588                 qcom,msm-bus,num-paths = <1>;
1589                 qcom,msm-bus,vectors-KBps =
1590                                 <100 512 0 0>,
1591                                 <100 512 500 800>;
1592
1593                 clocks = <&clock_gcc clk_gcc_pcie_1_pipe_clk>,
1594                         <&clock_gcc clk_ln_bb_clk>,
1595                         <&clock_gcc clk_gcc_pcie_1_aux_clk>,
1596                         <&clock_gcc clk_gcc_pcie_1_cfg_ahb_clk>,
1597                         <&clock_gcc clk_gcc_pcie_1_mstr_axi_clk>,
1598                         <&clock_gcc clk_gcc_pcie_1_slv_axi_clk>,
1599                         <&clock_gcc clk_gcc_pcie_clkref_clk>,
1600                         <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
1601                         <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
1602                         <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
1603
1604                 clock-names =  "pcie_1_pipe_clk", "pcie_1_ref_clk_src", "pcie_1_aux_clk",
1605                         "pcie_1_cfg_ahb_clk", "pcie_1_mstr_axi_clk",
1606                         "pcie_1_slv_axi_clk", "pcie_1_ldo", "pcie_1_smmu_clk",
1607                         "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
1608
1609                 resets = <&clock_gcc PCIE_PHY_BCR>,
1610                         <&clock_gcc PCIE_PHY_COM_BCR>,
1611                         <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
1612                         <&clock_gcc PCIE_1_PHY_BCR>;
1613
1614                 reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
1615                         "pcie_phy_nocsr_com_phy_reset","pcie_1_phy_reset";
1616
1617                 max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
1618                                          <0>, <0>, <0>, <0>, <0>, <0>, <0>;
1619         };
1620
1621         pcie2: qcom,pcie@00610000 {
1622                 compatible = "qcom,pci-msm";
1623                 cell-index = <2>;
1624
1625                 reg = <0x00610000 0x2000>,
1626                       <0x00034000 0x4000>,
1627                       <0x0e000000 0xf1d>,
1628                       <0x0e000f20 0xa8>,
1629                       <0x0e100000 0x100000>,
1630                       <0x0e200000 0x100000>,
1631                       <0x0e300000 0x1d00000>;
1632
1633                 reg-names = "parf", "phy", "dm_core", "elbi",
1634                                 "conf", "io", "bars";
1635
1636                 #address-cells = <3>;
1637                 #size-cells = <2>;
1638                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1639                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1640                 interrupt-parent = <&pcie2>;
1641                 interrupts =    <0 1 2 3 4 5 6 7 8 9 10 11
1642                                 12 13 14 15 16 17 18 19 20
1643                                 21 22 23 24 25 26 27 28 29
1644                                 30 31 32 33 34 35 36 37 38
1645                                 39 40 41 42 43>;
1646                 #interrupt-cells = <1>;
1647                 interrupt-map-mask = <0x0 0x0 0x0 0xffffffff>;
1648                 interrupt-map = <0x0 0x0 0x0 0 &intc 0 0 421 0
1649                                 0x0 0x0 0x0 1 &intc 0 0 142 0
1650                                 0x0 0x0 0x0 2 &intc 0 0 143 0
1651                                 0x0 0x0 0x0 3 &intc 0 0 144 0
1652                                 0x0 0x0 0x0 4 &intc 0 0 145 0
1653                                 0x0 0x0 0x0 5 &intc 0 0 146 0
1654                                 0x0 0x0 0x0 6 &intc 0 0 147 0
1655                                 0x0 0x0 0x0 7 &intc 0 0 148 0
1656                                 0x0 0x0 0x0 8 &intc 0 0 149 0
1657                                 0x0 0x0 0x0 9 &intc 0 0 260 0
1658                                 0x0 0x0 0x0 10 &intc 0 0 261 0
1659                                 0x0 0x0 0x0 11 &intc 0 0 262 0
1660                                 0x0 0x0 0x0 12 &intc 0 0 576 0
1661                                 0x0 0x0 0x0 13 &intc 0 0 577 0
1662                                 0x0 0x0 0x0 14 &intc 0 0 578 0
1663                                 0x0 0x0 0x0 15 &intc 0 0 579 0
1664                                 0x0 0x0 0x0 16 &intc 0 0 580 0
1665                                 0x0 0x0 0x0 17 &intc 0 0 581 0
1666                                 0x0 0x0 0x0 18 &intc 0 0 582 0
1667                                 0x0 0x0 0x0 19 &intc 0 0 583 0
1668                                 0x0 0x0 0x0 20 &intc 0 0 584 0
1669                                 0x0 0x0 0x0 21 &intc 0 0 585 0
1670                                 0x0 0x0 0x0 22 &intc 0 0 586 0
1671                                 0x0 0x0 0x0 23 &intc 0 0 587 0
1672                                 0x0 0x0 0x0 24 &intc 0 0 588 0
1673                                 0x0 0x0 0x0 25 &intc 0 0 589 0
1674                                 0x0 0x0 0x0 26 &intc 0 0 590 0
1675                                 0x0 0x0 0x0 27 &intc 0 0 591 0
1676                                 0x0 0x0 0x0 28 &intc 0 0 592 0
1677                                 0x0 0x0 0x0 29 &intc 0 0 593 0
1678                                 0x0 0x0 0x0 30 &intc 0 0 594 0
1679                                 0x0 0x0 0x0 31 &intc 0 0 595 0
1680                                 0x0 0x0 0x0 32 &intc 0 0 596 0
1681                                 0x0 0x0 0x0 33 &intc 0 0 597 0
1682                                 0x0 0x0 0x0 34 &intc 0 0 598 0
1683                                 0x0 0x0 0x0 35 &intc 0 0 599 0
1684                                 0x0 0x0 0x0 36 &intc 0 0 600 0
1685                                 0x0 0x0 0x0 37 &intc 0 0 601 0
1686                                 0x0 0x0 0x0 38 &intc 0 0 602 0
1687                                 0x0 0x0 0x0 39 &intc 0 0 603 0
1688                                 0x0 0x0 0x0 40 &intc 0 0 604 0
1689                                 0x0 0x0 0x0 41 &intc 0 0 605 0
1690                                 0x0 0x0 0x0 42 &intc 0 0 606 0
1691                                 0x0 0x0 0x0 43 &intc 0 0 607 0>;
1692
1693                 interrupt-names = "int_msi", "int_a", "int_b", "int_c", "int_d",
1694                                 "int_pls_pme", "int_pme_legacy", "int_pls_err",
1695                                 "int_aer_legacy", "int_pls_link_up",
1696                                 "int_pls_link_down", "int_bridge_flush_n",
1697                                 "msi_0", "msi_1", "msi_2", "msi_3",
1698                                 "msi_4", "msi_5", "msi_6", "msi_7",
1699                                 "msi_8", "msi_9", "msi_10", "msi_11",
1700                                 "msi_12", "msi_13", "msi_14", "msi_15",
1701                                 "msi_16", "msi_17", "msi_18", "msi_19",
1702                                 "msi_20", "msi_21", "msi_22", "msi_23",
1703                                 "msi_24", "msi_25", "msi_26", "msi_27",
1704                                 "msi_28", "msi_29", "msi_30", "msi_31";
1705
1706                 pinctrl-names = "default", "sleep";
1707                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1708                 pinctrl-1 = <&pcie2_clkreq_sleep
1709                         &pcie2_perst_default
1710                         &pcie2_wake_sleep>;
1711
1712                 perst-gpio = <&tlmm 114 0>;
1713                 wake-gpio = <&tlmm 116 0>;
1714
1715                 gdsc-smmu-supply = <&gdsc_aggre0_noc>;
1716                 gdsc-vdd-supply = <&gdsc_pcie_2>;
1717                 vreg-1.8-supply = <&pm8994_l12>;
1718                 vreg-0.9-supply = <&pm8994_l28>;
1719                 vreg-cx-supply = <&pm8994_s1_corner>;
1720
1721                 qcom,vreg-0.9-voltage-level = <925000 925000 24000>;
1722                 qcom,vreg-cx-voltage-level = <7 5 0>;
1723
1724                 qcom,l1-supported;
1725                 qcom,l1ss-supported;
1726                 qcom,aux-clk-sync;
1727
1728                 qcom,common-phy;
1729                 qcom,smmu-exist;
1730
1731                 iommus = <&anoc0_smmu>;
1732
1733                 qcom,boot-option = <0x1>;
1734
1735                 qcom,ep-latency = <10>;
1736
1737                 linux,pci-domain = <2>;
1738
1739                 qcom,msi-gicm-addr = <0x09BD0040>;
1740                 qcom,msi-gicm-base = <0x260>;
1741
1742                 qcom,msm-bus,name = "pcie2";
1743                 qcom,msm-bus,num-cases = <2>;
1744                 qcom,msm-bus,num-paths = <1>;
1745                 qcom,msm-bus,vectors-KBps =
1746                                 <108 512 0 0>,
1747                                 <108 512 500 800>;
1748
1749                 clocks = <&clock_gcc clk_gcc_pcie_2_pipe_clk>,
1750                         <&clock_gcc clk_ln_bb_clk>,
1751                         <&clock_gcc clk_gcc_pcie_2_aux_clk>,
1752                         <&clock_gcc clk_gcc_pcie_2_cfg_ahb_clk>,
1753                         <&clock_gcc clk_gcc_pcie_2_mstr_axi_clk>,
1754                         <&clock_gcc clk_gcc_pcie_2_slv_axi_clk>,
1755                         <&clock_gcc clk_gcc_pcie_clkref_clk>,
1756                         <&clock_gcc clk_gcc_smmu_aggre0_axi_clk>,
1757                         <&clock_gcc clk_gcc_pcie_phy_cfg_ahb_clk>,
1758                         <&clock_gcc clk_gcc_pcie_phy_aux_clk>;
1759
1760                 clock-names =  "pcie_2_pipe_clk", "pcie_2_ref_clk_src", "pcie_2_aux_clk",
1761                         "pcie_2_cfg_ahb_clk", "pcie_2_mstr_axi_clk",
1762                         "pcie_2_slv_axi_clk", "pcie_2_ldo", "pcie_2_smmu_clk",
1763                         "pcie_phy_cfg_ahb_clk", "pcie_phy_aux_clk";
1764
1765                 resets = <&clock_gcc PCIE_PHY_BCR>,
1766                         <&clock_gcc PCIE_PHY_COM_BCR>,
1767                         <&clock_gcc PCIE_PHY_NOCSR_COM_PHY_BCR>,
1768                         <&clock_gcc PCIE_2_PHY_BCR>;
1769
1770                 reset-names = "pcie_phy_reset", "pcie_phy_com_reset",
1771                         "pcie_phy_nocsr_com_phy_reset","pcie_2_phy_reset";
1772
1773                 max-clock-frequency-hz = <0>, <0>, <1010526>, <0>, <0>, <0>, <0>,
1774                                          <0>, <0>, <0>, <0>, <0>, <0>, <0>;
1775         };
1776
1777         mhi: qcom,mhi {
1778                 compatible = "qcom,mhi";
1779                 status = "disabled";
1780         };
1781
1782         qcom,ipc-spinlock@740000 {
1783                 compatible = "qcom,ipc-spinlock-sfpb";
1784                 reg = <0x740000 0x8000>;
1785                 qcom,num-locks = <8>;
1786         };
1787
1788         qcom,smem@86000000 {
1789                 compatible = "qcom,smem";
1790                 reg = <0x86000000 0x200000>,
1791                         <0x9820010 0x4>,
1792                         <0x68000 0x8000>,
1793                         <0x7b4000 0x8>;
1794                 reg-names = "smem", "irq-reg-base", "aux-mem1",
1795                         "smem_targ_info_reg";
1796                 qcom,mpu-enabled;
1797
1798                 qcom,smd-modem {
1799                         compatible = "qcom,smd";
1800                         qcom,smd-edge = <0>;
1801                         qcom,smd-irq-offset = <0x0>;
1802                         qcom,smd-irq-bitmask = <0x1000>;
1803                         interrupts = <0 449 1>;
1804                         label = "modem";
1805                         qcom,not-loadable;
1806                 };
1807
1808                 qcom,smd-adsp {
1809                         compatible = "qcom,smd";
1810                         qcom,smd-edge = <1>;
1811                         qcom,smd-irq-offset = <0x0>;
1812                         qcom,smd-irq-bitmask = <0x100>;
1813                         interrupts = <0 156 1>;
1814                         label = "adsp";
1815                 };
1816
1817                 qcom,smd-dsps {
1818                         compatible = "qcom,smd";
1819                         qcom,smd-edge = <3>;
1820                         qcom,smd-irq-offset = <0x0>;
1821                         qcom,smd-irq-bitmask = <0x2000000>;
1822                         interrupts = <0 176 1>;
1823                         label = "dsps";
1824                 };
1825
1826                 qcom,smd-rpm {
1827                         compatible = "qcom,smd";
1828                         qcom,smd-edge = <15>;
1829                         qcom,smd-irq-offset = <0x0>;
1830                         qcom,smd-irq-bitmask = <0x1>;
1831                         interrupts = <0 168 1>;
1832                         label = "rpm";
1833                         qcom,irq-no-suspend;
1834                         qcom,not-loadable;
1835                 };
1836         };
1837
1838         wdog: qcom,wdt@9830000 {
1839                 compatible = "qcom,msm-watchdog";
1840                 reg = <0x9830000 0x1000>;
1841                 reg-names = "wdt-base";
1842                 interrupts = <0 28 0>, <0 29 0>;
1843                 qcom,bark-time = <11000>;
1844                 qcom,pet-time = <10000>;
1845                 qcom,ipi-ping;
1846                 qcom,wakeup-enable;
1847         };
1848
1849         qcom,msm-rtb {
1850                 compatible = "qcom,msm-rtb";
1851                 qcom,rtb-size = <0x100000>;
1852         };
1853
1854         qcom,mpm2-sleep-counter@4a3000 {
1855                 compatible = "qcom,mpm2-sleep-counter";
1856                 reg = <0x004a3000 0x1000>;
1857                 clock-frequency = <32768>;
1858         };
1859
1860         qcom,msm-imem@66bf000 {
1861                 compatible = "qcom,msm-imem";
1862                 reg = <0x66bf000 0x1000>; /* Address and size of IMEM */
1863                 ranges = <0x0 0x66bf000 0x1000>;
1864                 #address-cells = <1>;
1865                 #size-cells = <1>;
1866
1867                 mem_dump_table@10 {
1868                         compatible = "qcom,msm-imem-mem_dump_table";
1869                         reg = <0x10 8>;
1870                 };
1871
1872                 dload_type@18 {
1873                         compatible = "qcom,msm-imem-dload-type";
1874                         reg = <0x18 4>;
1875                 };
1876
1877                 restart_reason@65c {
1878                         compatible = "qcom,msm-imem-restart_reason";
1879                         reg = <0x65c 4>;
1880                 };
1881
1882                 boot_stats@6b0 {
1883                         compatible = "qcom,msm-imem-boot_stats";
1884                         reg = <0x6b0 32>;
1885                 };
1886
1887                 pil@94c {
1888                         compatible = "qcom,msm-imem-pil";
1889                         reg = <0x94c 200>;
1890                 };
1891         };
1892
1893         jtag_fuse: jtagfuse@7602c {
1894                 compatible = "qcom,jtag-fuse-v3";
1895                 reg = <0x7602c 0xc>;
1896                 reg-names = "fuse-base";
1897         };
1898
1899         rpm_bus: qcom,rpm-smd {
1900                  compatible = "qcom,rpm-glink";
1901                  qcom,glink-edge = "rpm";
1902                  rpm-channel-name = "rpm_requests";
1903          };
1904
1905         qcom,smdpkt {
1906                 compatible = "qcom,smdpkt";
1907
1908                 qcom,smdpkt-data5-cntl {
1909                         qcom,smdpkt-remote = "modem";
1910                         qcom,smdpkt-port-name = "DATA5_CNTL";
1911                         qcom,smdpkt-dev-name = "smdcntl0";
1912                 };
1913
1914                 qcom,smdpkt-data22 {
1915                         qcom,smdpkt-remote = "modem";
1916                         qcom,smdpkt-port-name = "DATA22";
1917                         qcom,smdpkt-dev-name = "smd22";
1918                 };
1919
1920                 qcom,smdpkt-data40-cntl {
1921                         qcom,smdpkt-remote = "modem";
1922                         qcom,smdpkt-port-name = "DATA40_CNTL";
1923                         qcom,smdpkt-dev-name = "smdcntl8";
1924                 };
1925
1926                 qcom,smdpkt-apr-apps2 {
1927                         qcom,smdpkt-remote = "adsp";
1928                         qcom,smdpkt-port-name = "apr_apps2";
1929                         qcom,smdpkt-dev-name = "apr_apps2";
1930                 };
1931
1932                 qcom,smdpkt-loopback {
1933                         qcom,smdpkt-remote = "modem";
1934                         qcom,smdpkt-port-name = "LOOPBACK";
1935                         qcom,smdpkt-dev-name = "smd_pkt_loopback";
1936                 };
1937         };
1938
1939         qcom,smdtty {
1940                 compatible = "qcom,smdtty";
1941
1942                 smdtty_data1: qcom,smdtty-data1 {
1943                         qcom,smdtty-remote = "modem";
1944                         qcom,smdtty-port-name = "DATA1";
1945                 };
1946
1947                 smdtty_data4: qcom,smdtty-data4 {
1948                         qcom,smdtty-remote = "modem";
1949                         qcom,smdtty-port-name = "DATA4";
1950                 };
1951
1952                 smdtty_data11: qcom,smdtty-data11 {
1953                         qcom,smdtty-remote = "modem";
1954                         qcom,smdtty-port-name = "DATA11";
1955                 };
1956
1957                 smdtty_data21: qcom,smdtty-data21 {
1958                         qcom,smdtty-remote = "modem";
1959                         qcom,smdtty-port-name = "DATA21";
1960                 };
1961
1962                 smdtty_loopback: smdtty-loopback {
1963                         qcom,smdtty-remote = "modem";
1964                         qcom,smdtty-port-name = "LOOPBACK";
1965                         qcom,smdtty-dev-name = "LOOPBACK_TTY";
1966                 };
1967         };
1968
1969         usb3: ssusb@6a00000{
1970                 compatible = "qcom,dwc-usb3-msm";
1971                 reg = <0x06a00000 0xfc000>,
1972                         <0x7416000 0x400>;
1973                 reg-names = "core_base",
1974                         "ahb2phy_base";
1975                 #address-cells = <1>;
1976                 #size-cells = <1>;
1977                 ranges;
1978
1979                 interrupts = <0 347 0>, <0 243 0>, <0 180 0>;
1980                 interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
1981
1982                 USB3_GDSC-supply = <&gdsc_usb30>;
1983                 vbus_dwc3-supply = <&smbcharger_charger_otg>;
1984                 qcom,usb-dbm = <&dbm_1p5>;
1985                 qcom,msm-bus,name = "usb3";
1986                 qcom,msm-bus,num-cases = <2>;
1987                 qcom,msm-bus,num-paths = <1>;
1988                 qcom,msm-bus,vectors-KBps =
1989                                         <61 512 0 0>,
1990                                         <61 512 240000 800000>;
1991
1992                 qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
1993
1994                 clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
1995                         <&clock_gcc clk_gcc_sys_noc_usb3_axi_clk>,
1996                         <&clock_gcc clk_gcc_aggre2_usb3_axi_clk>,
1997                         <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
1998                         <&clock_gcc clk_gcc_usb30_sleep_clk>,
1999                         <&clock_gcc clk_cxo_dwc3_clk>,
2000                         <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
2001
2002                 clock-names = "core_clk", "iface_clk", "bus_aggr_clk", "utmi_clk",
2003                                 "sleep_clk", "xo", "cfg_ahb_clk";
2004
2005                 qcom,core-clk-rate = <120000000>;
2006
2007                 resets = <&clock_gcc USB_30_BCR>;
2008                 reset-names = "core_reset";
2009
2010                 dwc3@6a00000 {
2011                         compatible = "snps,dwc3";
2012                         reg = <0x06a00000 0xc8d0>;
2013                         interrupt-parent = <&intc>;
2014                         interrupts = <0 131 0>;
2015                         usb-phy = <&qusb_phy0>, <&ssphy>;
2016                         tx-fifo-resize;
2017                         snps,usb3-u1u2-disable;
2018                         snps,nominal-elastic-buffer;
2019                         snps,is-utmi-l1-suspend;
2020                         snps,hird-threshold = /bits/ 8 <0x0>;
2021                 };
2022
2023                 qcom,usbbam@6b04000 {
2024                         compatible = "qcom,usb-bam-msm";
2025                         reg = <0x06b04000 0x1a934>;
2026                         interrupt-parent = <&intc>;
2027                         interrupts = <0 132 0>;
2028
2029                         qcom,bam-type = <0>;
2030                         qcom,usb-bam-fifo-baseaddr = <0x066bb000>;
2031                         qcom,usb-bam-num-pipes = <8>;
2032                         qcom,ignore-core-reset-ack;
2033                         qcom,disable-clk-gating;
2034                         qcom,usb-bam-override-threshold = <0x4001>;
2035                         qcom,usb-bam-max-mbps-highspeed = <400>;
2036                         qcom,usb-bam-max-mbps-superspeed = <3600>;
2037                         qcom,reset-bam-on-connect;
2038
2039                         qcom,pipe0 {
2040                                 label = "ssusb-ipa-out-0";
2041                                 qcom,usb-bam-mem-type = <1>;
2042                                 qcom,dir = <0>;
2043                                 qcom,pipe-num = <0>;
2044                                 qcom,peer-bam = <1>;
2045                                 qcom,src-bam-pipe-index = <1>;
2046                                 qcom,data-fifo-size = <0x8000>;
2047                                 qcom,descriptor-fifo-size = <0x2000>;
2048                         };
2049                         qcom,pipe1 {
2050                                 label = "ssusb-ipa-in-0";
2051                                 qcom,usb-bam-mem-type = <1>;
2052                                 qcom,dir = <1>;
2053                                 qcom,pipe-num = <0>;
2054                                 qcom,peer-bam = <1>;
2055                                 qcom,dst-bam-pipe-index = <0>;
2056                                 qcom,data-fifo-size = <0x8000>;
2057                                 qcom,descriptor-fifo-size = <0x2000>;
2058                         };
2059                         qcom,pipe2 {
2060                                 label = "ssusb-qdss-in-0";
2061                                 qcom,usb-bam-mem-type = <2>;
2062                                 qcom,dir = <1>;
2063                                 qcom,pipe-num = <0>;
2064                                 qcom,peer-bam = <0>;
2065                                 qcom,peer-bam-physical-address = <0x03084000>;
2066                                 qcom,src-bam-pipe-index = <0>;
2067                                 qcom,dst-bam-pipe-index = <2>;
2068                                 qcom,data-fifo-offset = <0x0>;
2069                                 qcom,data-fifo-size = <0x1800>;
2070                                 qcom,descriptor-fifo-offset = <0x1800>;
2071                                 qcom,descriptor-fifo-size = <0x800>;
2072                         };
2073                         qcom,pipe3 {
2074                                 label = "ssusb-dpl-ipa-in-1";
2075                                 qcom,usb-bam-mem-type = <1>;
2076                                 qcom,dir = <1>;
2077                                 qcom,pipe-num = <1>;
2078                                 qcom,peer-bam = <1>;
2079                                 qcom,dst-bam-pipe-index = <2>;
2080                                 qcom,data-fifo-size = <0x8000>;
2081                                 qcom,descriptor-fifo-size = <0x2000>;
2082                         };
2083                 };
2084         };
2085
2086         usb2s: hsusb@7600000 {
2087                 compatible = "qcom,dwc-usb3-msm";
2088                 reg = <0x07600000 0xfc000>,
2089                         <0x7416000 0x400>;
2090                 reg-names = "core_base",
2091                         "ahb2phy_base";
2092                 #address-cells = <1>;
2093                 #size-cells = <1>;
2094                 ranges;
2095                 status = "disabled";
2096
2097                 interrupts = <0 352 0>, <0 140 0>;
2098                 interrupt-names = "hs_phy_irq", "pwr_event_irq";
2099
2100                 qcom,msm-bus,name = "usb-hs";
2101                 qcom,msm-bus,num-cases = <2>;
2102                 qcom,msm-bus,num-paths = <1>;
2103                 qcom,msm-bus,vectors-KBps =
2104                                         <87 512 0 0>,
2105                                         <87 512 60000 960000>;
2106
2107                 clocks = <&clock_gcc clk_gcc_usb20_master_clk>,
2108                          <&clock_gcc clk_gcc_periph_noc_usb20_ahb_clk>,
2109                          <&clock_gcc clk_gcc_usb20_mock_utmi_clk>,
2110                          <&clock_gcc clk_gcc_usb20_sleep_clk>,
2111                          <&clock_gcc clk_cxo_dwc3_clk>,
2112                          <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>;
2113                 clock-names = "core_clk", "iface_clk", "utmi_clk", "sleep_clk",
2114                                 "xo", "cfg_ahb_clk";
2115                 qcom,core-clk-rate = <60000000>;
2116                 resets = <&clock_gcc USB_20_BCR>;
2117                 reset-names = "core_reset";
2118
2119                 dwc3@7600000 {
2120                         compatible = "snps,dwc3";
2121                         reg = <0x07600000 0xc8d0>;
2122                         interrupt-parent = <&intc>;
2123                         interrupts = <0 138 0>;
2124                         usb-phy = <&qusb_phy1>, <&usb_nop_phy>;
2125                         maximum-speed = "high-speed";
2126                         snps,nominal-elastic-buffer;
2127                         snps,is-utmi-l1-suspend;
2128                         snps,hird-threshold = /bits/ 8 <0x0>;
2129                 };
2130         };
2131
2132         android_usb@66bf0c8 {
2133                 compatible = "qcom,android-usb";
2134                 reg = <0x066bf0c8 0xc8>;
2135                 qcom,pm-qos-latency = <301 701 801>;
2136         };
2137
2138         qusb_phy0: qusb@7411000 {
2139                 compatible = "qcom,qusb2phy";
2140                 reg = <0x07411000 0x180>,
2141                         <0x0007024c 0x4>,
2142                         <0x00388018 0x4>;
2143                 reg-names = "qusb_phy_base",
2144                         "tune2_efuse_addr",
2145                         "ref_clk_addr";
2146                 vdd-supply = <&pm8994_s2_corner>;
2147                 vdda18-supply = <&pm8994_l12>;
2148                 vdda33-supply = <&pm8994_l24>;
2149                 qcom,vdd-voltage-level = <1 5 7>;
2150                 qcom,tune2-efuse-bit-pos = <21>;
2151                 qcom,tune2-efuse-num-bits = <4>;
2152                 qcom,qusb-phy-init-seq = <0xF8 0x80
2153                                         0xB3 0x84
2154                                         0x83 0x88
2155                                         0xC0 0x8C
2156                                         0x30 0x08
2157                                         0x79 0x0C
2158                                         0x21 0x10
2159                                         0x14 0x9C
2160                                         0x9F 0x1C
2161                                         0x00 0x18>;
2162                 phy_type= "utmi";
2163                 qcom,phy-clk-scheme = "cmos";
2164                 qcom,major-rev = <1>;
2165
2166                 clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
2167                          <&clock_gcc clk_ln_bb_clk>;
2168                 clock-names = "cfg_ahb_clk", "ref_clk_src";
2169
2170                 resets = <&clock_gcc QUSB2PHY_PRIM_BCR>;
2171                 reset-names = "phy_reset";
2172         };
2173
2174         qusb_phy1: qusb@7412000 {
2175                 compatible = "qcom,qusb2phy";
2176                 reg = <0x07412000 0x180>,
2177                         <0x0007024c 0x4>,
2178                         <0x00388014 0x4>;
2179                 reg-names = "qusb_phy_base",
2180                         "tune2_efuse_addr",
2181                         "ref_clk_addr";
2182                 vdd-supply = <&pm8994_s2_corner>;
2183                 vdda18-supply = <&pm8994_l12>;
2184                 vdda33-supply = <&pm8994_l24>;
2185                 qcom,vdd-voltage-level = <1 5 7>;
2186                 qcom,tune2-efuse-bit-pos = <25>;
2187                 qcom,tune2-efuse-num-bits = <4>;
2188                 qcom,qusb-phy-init-seq = <0xF8 0x80
2189                                         0xB3 0x84
2190                                         0x83 0x88
2191                                         0xC0 0x8C
2192                                         0x30 0x08
2193                                         0x79 0x0C
2194                                         0x21 0x10
2195                                         0x14 0x9C
2196                                         0x9F 0x1C
2197                                         0x00 0x18>;
2198                 phy_type = "utmi";
2199                 qcom,phy-clk-scheme = "cmos";
2200                 qcom,major-rev = <1>;
2201                 qcom,hold-reset;
2202
2203                 clocks = <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
2204                         <&clock_gcc clk_ln_bb_clk>;
2205                 clock-names = "cfg_ahb_clk", "ref_clk_src";
2206
2207                 resets = <&clock_gcc QUSB2PHY_SEC_BCR>;
2208                 reset-names = "phy_reset";
2209         };
2210
2211         ssphy: ssphy@7410000 {
2212                 compatible = "qcom,usb-ssphy-qmp-v2";
2213                 reg = <0x7410000 0x7a8>,
2214                       <0x007ab244 0x4>;
2215                 reg-names = "qmp_phy_base",
2216                             "vls_clamp_reg";
2217                 vdd-supply = <&pm8994_l28>;
2218                 core-supply = <&pm8994_l12>;
2219                 qcom,core-voltage-level = <0 1800000 1800000>;
2220                 qcom,vdd-voltage-level = <0 925000 925000>;
2221                 qcom,vbus-valid-override;
2222                 qcom,qmp-phy-init-seq =
2223                         /* <reg_offset, value, delay> */
2224                                 <0xac  0x14 0x00 /* common block settings */
2225                                  0x34  0x08 0x00
2226                                  0x174 0x30 0x00
2227                                  0x194 0x06 0x00
2228                                  0x19c 0x01 0x00
2229                                  0x178 0x00 0x00
2230                                  0x70  0x0f 0x00
2231                                  0x48  0x0f 0x00
2232                                  0x3c  0x04 0x00
2233                                  0xd0  0x82 0x00 /* pll and loop filter settings*/
2234                                  0xdc  0x55 0x00
2235                                  0xe0  0x55 0x00
2236                                  0xe4  0x03 0x00
2237                                  0x78  0x0b 0x00
2238                                  0x84  0x16 0x00
2239                                  0x90  0x28 0x00
2240                                  0x108 0x80 0x00
2241                                  0x124 0x00 0x00
2242                                  0x4c  0x15 0x00
2243                                  0x50  0x34 0x00
2244                                  0x18c 0x00 0x00
2245                                  0xcc  0x00 0x00
2246                                  0x128 0x00 0x00
2247                                  0x0c  0x0a 0x00
2248                                  0x10  0x01 0x00 /* ssc settings */
2249                                  0x1c  0x31 0x00
2250                                  0x20  0x01 0x00
2251                                  0x14  0x00 0x00
2252                                  0x18  0x00 0x00
2253                                  0x24  0xde 0x00
2254                                  0x28  0x07 0x00
2255                                  0x440 0x0b 0x00 /* Rx settings */
2256                                  0x41c 0x04 0x00
2257                                  0x4d8 0x02 0x00
2258                                  0x4dc 0x4c 0x00
2259                                  0x4e0 0xbb 0x00
2260                                  0x508 0x77 0x00
2261                                  0x50c 0x80 0x00
2262                                  0x514 0x03 0x00
2263                                  0x518 0x18 0x00
2264                                  0x51c 0x16 0x00
2265                                  0x268 0x45 0x00 /* Tx settings */
2266                                  0x2ac 0x12 0x00
2267                                  0x294 0x06 0x00
2268                                  0x6c4 0x03 0x00 /* FLL settings */
2269                                  0x6c0 0x02 0x00
2270                                  0x6c8 0x09 0x00
2271                                  0x6cc 0x42 0x00
2272                                  0x6d0 0x85 0x00
2273                                  0x680 0xd1 0x00 /* Lock Det settings */
2274                                  0x684 0x1f 0x00
2275                                  0x688 0x47 0x00
2276                                  0x664 0x08 0x00
2277                                  0xffffffff 0xffffffff 0x00>;
2278
2279                 qcom,qmp-phy-reg-offset =
2280                                 <0x77c /* USB3_PHY_PCS_STATUS */
2281                                  0x6d4 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
2282                                  0x6d8 /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
2283                                  0x604 /* USB3_PHY_POWER_DOWN_CONTROL */
2284                                  0x600 /* USB3_PHY_SW_RESET */
2285                                  0x608>; /* USB3_PHY_START */
2286
2287                 clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
2288                          <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
2289                          <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
2290                          <&clock_gcc clk_ln_bb_clk>,
2291                          <&clock_gcc clk_gcc_usb3_clkref_clk>;
2292
2293                 clock-names = "aux_clk", "pipe_clk", "cfg_ahb_clk",
2294                                 "ref_clk_src", "ref_clk";
2295
2296                 resets = <&clock_gcc USB3_PHY_BCR>,
2297                          <&clock_gcc USB3PHY_PHY_BCR>;
2298                 reset-names = "phy_reset", "phy_phy_reset";
2299         };
2300
2301         usb_nop_phy: usb_nop_phy {
2302                 compatible = "usb-nop-xceiv";
2303         };
2304
2305         dbm_1p5: dbm@6af8000 {
2306                 compatible = "qcom,usb-dbm-1p5";
2307                 reg = <0x06af8000 0x300>;
2308                 qcom,reset-ep-after-lpm-resume;
2309         };
2310
2311         usb_audio_qmi_dev {
2312                 compatible = "qcom,usb-audio-qmi-dev";
2313                 iommus = <&lpass_q6_smmu 12>;
2314                 qcom,usb-audio-stream-id = <12>;
2315                 qcom,usb-audio-intr-num = <1>;
2316         };
2317
2318         qcom,lpass@9300000 {
2319                 compatible = "qcom,pil-tz-generic";
2320                 reg = <0x9300000 0x00100>;
2321                 interrupts = <0 162 1>;
2322
2323                 vdd_cx-supply = <&pm8994_s1_corner>;
2324                 qcom,proxy-reg-names = "vdd_cx";
2325                 qcom,vdd_cx-uV-uA = <7 100000>;
2326
2327                 clocks = <&clock_gcc clk_cxo_pil_lpass_clk>;
2328                 clock-names = "xo";
2329                 qcom,proxy-clock-names = "xo";
2330
2331                 qcom,pas-id = <1>;
2332                 qcom,proxy-timeout-ms = <10000>;
2333                 qcom,smem-id = <423>;
2334                 qcom,sysmon-id = <1>;
2335                 qcom,ssctl-instance-id = <0x14>;
2336                 qcom,firmware-name = "adsp";
2337                 qcom,edge = "lpass";
2338                 memory-region = <&peripheral_mem>;
2339
2340                 /* GPIO inputs from lpass */
2341                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
2342                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
2343                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
2344                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
2345
2346                 /* GPIO output to lpass */
2347                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
2348         };
2349
2350         qcom,venus@ce0000 {
2351                 compatible = "qcom,pil-tz-generic";
2352                 reg = <0xce0000 0x4000>;
2353
2354                 vdd-supply = <&gdsc_venus>;
2355                 qcom,proxy-reg-names = "vdd";
2356
2357                 clocks = <&clock_mmss clk_video_core_clk>,
2358                         <&clock_mmss clk_video_ahb_clk>,
2359                         <&clock_mmss clk_video_axi_clk>,
2360                         <&clock_mmss clk_video_maxi_clk>;
2361                 clock-names = "core_clk", "iface_clk",
2362                                 "bus_clk", "maxi_clk";
2363                 qcom,proxy-clock-names = "core_clk", "iface_clk",
2364                                 "bus_clk", "maxi_clk";
2365
2366                 qcom,msm-bus,name = "pil-venus";
2367                 qcom,msm-bus,num-cases = <2>;
2368                 qcom,msm-bus,num-paths = <1>;
2369                 qcom,msm-bus,vectors-KBps =
2370                                 <63 512 0 0>,
2371                                 <63 512 0 304000>;
2372                 qcom,pas-id = <9>;
2373                 qcom,proxy-timeout-ms = <100>;
2374                 qcom,firmware-name = "venus";
2375                 memory-region = <&peripheral_mem>;
2376         };
2377
2378         qcom,cnss {
2379                 compatible = "qcom,cnss";
2380                 wlan-bootstrap-gpio = <&tlmm 46 0>;
2381                 vdd-wlan-en-supply = <&wlan_en_vreg>;
2382                 vdd-wlan-supply = <&rome_vreg>;
2383                 vdd-wlan-io-supply = <&pm8994_s4>;
2384                 vdd-wlan-xtal-supply = <&pm8994_l30>;
2385                 vdd-wlan-core-supply = <&pm8994_s3>;
2386                 wlan-ant-switch-supply = <&pm8994_l18_pin_ctrl>;
2387                 qcom,wlan-en-vreg-support;
2388                 qcom,notify-modem-status;
2389                 pinctrl-names = "bootstrap_active", "bootstrap_sleep";
2390                 pinctrl-0 = <&cnss_bootstrap_active>;
2391                 pinctrl-1 = <&cnss_bootstrap_sleep>;
2392                 qcom,wlan-rc-num = <0>;
2393                 qcom,wlan-ramdump-dynamic = <0x200000>;
2394
2395                 qcom,msm-bus,name = "msm-cnss";
2396                 qcom,msm-bus,num-cases = <4>;
2397                 qcom,msm-bus,num-paths = <1>;
2398                 qcom,msm-bus,vectors-KBps =
2399                                         /* No vote */
2400                                         <45 512 0 0>,
2401                                         /* Up to 200 Mbps */
2402                                         <45 512 41421 1520000>,
2403                                         /* Up to 400 Mbps */
2404                                         <45 512 96650 1520000>,
2405                                         /* Up to 800 Mbps */
2406                                         <45 512 207108 14432000>;
2407         };
2408
2409         wil6210: qcom,wil6210 {
2410                 compatible = "qcom,wil6210";
2411                 qcom,pcie-parent = <&pcie1>;
2412                 qcom,wigig-en = <&tlmm 94 0>;
2413                 qcom,sleep-clk-en = <&pm8994_gpios 18 0>;
2414                 qcom,msm-bus,name = "wil6210";
2415                 qcom,msm-bus,num-cases = <2>;
2416                 qcom,msm-bus,num-paths = <1>;
2417                 qcom,msm-bus,vectors-KBps =
2418                         <100 512 0 0>,
2419                         <100 512 600000 800000>; /* ~4.6Gbps (MCS12) */
2420                 status = "disabled";
2421         };
2422
2423         qcom,ssc@1c00000 {
2424                 compatible = "qcom,pil-tz-generic";
2425                 reg = <0x1c00000 0x4000>;
2426                 interrupts = <0 390 1>;
2427
2428                 vdd_cx-supply = <&pm8994_l26_corner>;
2429                 vdd_px-supply = <&pm8994_lvs2>;
2430                 qcom,vdd_cx-uV-uA = <5 0>;
2431                 qcom,proxy-reg-names = "vdd_cx", "vdd_px";
2432                 qcom,keep-proxy-regs-on;
2433
2434                 clocks = <&clock_gcc clk_cxo_pil_ssc_clk>,
2435                          <&clock_gcc clk_aggre2_noc_clk>;
2436                 clock-names = "xo", "aggre2";
2437                 qcom,proxy-clock-names = "xo", "aggre2";
2438
2439                 qcom,pas-id = <12>;
2440                 qcom,proxy-timeout-ms = <10000>;
2441                 qcom,smem-id = <424>;
2442                 qcom,sysmon-id = <3>;
2443                 qcom,ssctl-instance-id = <0x16>;
2444                 qcom,firmware-name = "slpi";
2445                 qcom,edge = "dsps";
2446                 memory-region = <&peripheral_mem>;
2447
2448                 /* GPIO inputs from ssc */
2449                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>;
2450                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>;
2451                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>;
2452                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>;
2453
2454                 /* GPIO output to ssc */
2455                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>;
2456         };
2457
2458        pil_modem: qcom,mss@2080000 {
2459                 compatible = "qcom,pil-q6v55-mss";
2460                 reg = <0x2080000 0x100>,
2461                       <0x0763000 0x008>,
2462                       <0x0765000 0x008>,
2463                       <0x0764000 0x008>,
2464                       <0x2180000 0x020>,
2465                       <0x038f008 0x004>;
2466                 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2467                         "halt_nc", "rmb_base", "restart_reg";
2468
2469                 clocks = <&clock_gcc clk_cxo_clk_src>,
2470                          <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
2471                          <&clock_gcc clk_pnoc_clk>,
2472                          <&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
2473                          <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
2474                          <&clock_gcc clk_gpll0_out_msscc>,
2475                          <&clock_gcc clk_gcc_mss_snoc_axi_clk>,
2476                          <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
2477                          <&clock_gcc clk_qdss_clk>;
2478                 clock-names = "xo", "iface_clk", "pnoc_clk", "bus_clk",
2479                               "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2480                               "mnoc_axi_clk", "qdss_clk";
2481                 qcom,proxy-clock-names = "xo", "pnoc_clk", "qdss_clk";
2482                 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2483                                           "gpll0_mss_clk", "snoc_axi_clk",
2484                                           "mnoc_axi_clk";
2485
2486                 interrupts = <0 448 1>;
2487                 vdd_cx-supply = <&pm8994_s1_corner>;
2488                 vdd_cx-voltage = <7>;
2489                 vdd_mx-supply = <&pm8994_s2_corner>;
2490                 vdd_mx-uV = <6>;
2491                 vdd_pll-supply = <&pm8994_l12>;
2492                 qcom,vdd_pll = <1800000>;
2493                 qcom,firmware-name = "modem";
2494                 qcom,pil-self-auth;
2495                 qcom,sysmon-id = <0>;
2496                 qcom,ssctl-instance-id = <0x12>;
2497                 qcom,override-acc;
2498                 qcom,ahb-clk-vote;
2499                 qcom,pnoc-clk-vote;
2500                 qcom,qdsp6v56-1-5;
2501                 qcom,mx-spike-wa;
2502                 memory-region = <&modem_mem>;
2503                 qcom,mem-protect-id = <0xF>;
2504
2505                 /* GPIO inputs from mss */
2506                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2507                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2508                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2509                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2510                 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2511
2512                 /* GPIO output to mss */
2513                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
2514                 status = "ok";
2515         };
2516
2517         tsens0: tsens@4a9000 {
2518                 compatible = "qcom,msm8996-tsens";
2519                 reg = <0x4a8000 0x2000>,
2520                         <0x74230 0x1000>;
2521                 reg-names = "tsens_physical", "tsens_eeprom_physical";
2522                 interrupts = <0 184 0>, <0 430 0>;
2523                 interrupt-names = "tsens-upper-lower", "tsens-critical";
2524                 qcom,sensors = <16>;
2525                 qcom,slope = <2901 2846 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200 3200>;
2526         };
2527
2528         spi_0: spi@7575000 { /* BLSP1 QUP1 */
2529                 compatible = "qcom,spi-qup-v2";
2530                 #address-cells = <1>;
2531                 #size-cells = <0>;
2532                 reg-names = "spi_physical", "spi_bam_physical";
2533                 reg = <0x07575000 0x600>,
2534                       <0x07544000 0x2b000>;
2535                 interrupt-names = "spi_irq", "spi_bam_irq";
2536                 interrupts = <0 95 0>, <0 238 0>;
2537                 spi-max-frequency = <19200000>;
2538
2539                 qcom,infinite-mode = <0>;
2540                 qcom,use-bam;
2541                 qcom,ver-reg-exists;
2542                 qcom,bam-consumer-pipe-index = <12>;
2543                 qcom,bam-producer-pipe-index = <13>;
2544                 qcom,master-id = <86>;
2545                 qcom,use-pinctrl;
2546                 pinctrl-names = "spi_default", "spi_sleep";
2547                 pinctrl-0 = <&spi_0_active &spi_0_cs_active>;
2548                 pinctrl-1 = <&spi_0_sleep &spi_0_cs_sleep>;
2549
2550                 clock-names = "iface_clk", "core_clk";
2551
2552                 clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
2553                          <&clock_gcc clk_gcc_blsp1_qup1_spi_apps_clk>;
2554         };
2555
2556         qcom,rmnet-ipa {
2557                 compatible = "qcom,rmnet-ipa";
2558                 qcom,rmnet-ipa-ssr;
2559                 qcom,ipa-loaduC;
2560                 qcom,ipa-advertise-sg-support;
2561         };
2562
2563         qcom_rng: qrng@83000 {
2564                 compatible = "qcom,msm-rng";
2565                 reg = <0x83000 0x1000>;
2566                 qcom,msm-rng-iface-clk;
2567                 qcom,no-qrng-config;
2568                 qcom,msm-bus,name = "msm-rng-noc";
2569                 qcom,msm-bus,num-cases = <2>;
2570                 qcom,msm-bus,num-paths = <1>;
2571                 qcom,msm-bus,vectors-KBps =
2572                                 <1 618 0 0>,            /* No vote */
2573                                 <1 618 0 800>;          /* 100 MB/s */
2574                 clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
2575                 clock-names = "iface_clk";
2576         };
2577
2578         qcom_crypto: qcrypto@660000 {
2579                 compatible = "qcom,qcrypto";
2580                 reg = <0x660000 0x20000>,
2581                       <0x644000 0x24000>;
2582                 reg-names = "crypto-base","crypto-bam-base";
2583                 interrupts = <0 206 0>;
2584                 qcom,bam-pipe-pair = <2>;
2585                 qcom,ce-hw-instance = <0>;
2586                 qcom,ce-device = <0>;
2587                 qcom,bam-ee = <0>;
2588                 qcom,ce-hw-shared;
2589                 qcom,clk-mgmt-sus-res;
2590                 qcom,msm-bus,name = "qcrypto-noc";
2591                 qcom,msm-bus,num-cases = <2>;
2592                 qcom,msm-bus,num-paths = <1>;
2593                 qcom,msm-bus,vectors-KBps =
2594                                 <55 512 0 0>,
2595                                 <55 512 3936000 393600>;
2596                 clock-names = "core_clk_src", "core_clk",
2597                                 "iface_clk", "bus_clk";
2598                 clocks = <&clock_gcc clk_qcrypto_ce1_clk>,
2599                          <&clock_gcc clk_qcrypto_ce1_clk>,
2600                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2601                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2602                 qcom,ce-opp-freq = <171430000>;
2603                 qcom,use-sw-aes-cbc-ecb-ctr-algo;
2604                 qcom,use-sw-aes-xts-algo;
2605                 qcom,use-sw-aes-ccm-algo;
2606                 qcom,use-sw-ahash-algo;
2607                 qcom,use-sw-hmac-algo;
2608                 qcom,use-sw-aead-algo;
2609         };
2610
2611         qcom_cedev: qcedev@660000 {
2612                 compatible = "qcom,qcedev";
2613                 reg = <0x660000 0x20000>,
2614                       <0x644000 0x24000>;
2615                 reg-names = "crypto-base","crypto-bam-base";
2616                 interrupts = <0 206 0>;
2617                 qcom,bam-pipe-pair = <1>;
2618                 qcom,ce-hw-instance = <0>;
2619                 qcom,ce-device = <0>;
2620                 qcom,ce-hw-shared;
2621                 qcom,bam-ee = <0>;
2622                 qcom,msm-bus,name = "qcedev-noc";
2623                 qcom,msm-bus,num-cases = <2>;
2624                 qcom,msm-bus,num-paths = <1>;
2625                 qcom,msm-bus,vectors-KBps =
2626                                 <55 512 0 0>,
2627                                 <55 512 3936000 393600>;
2628                 clock-names = "core_clk_src", "core_clk",
2629                                 "iface_clk", "bus_clk";
2630                 clocks = <&clock_gcc clk_qcedev_ce1_clk>,
2631                          <&clock_gcc clk_qcedev_ce1_clk>,
2632                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2633                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2634                 qcom,ce-opp-freq = <171430000>;
2635         };
2636
2637         qcom_seecom: qseecom@86600000 {
2638                 compatible = "qcom,qseecom";
2639                 reg = <0x86600000 0x2200000>;
2640                 reg-names = "secapp-region";
2641                 qcom,hlos-num-ce-hw-instances = <1>;
2642                 qcom,hlos-ce-hw-instance = <0>;
2643                 qcom,qsee-ce-hw-instance = <0>;
2644                 qcom,disk-encrypt-pipe-pair = <2>;
2645                 qcom,support-fde;
2646                 qcom,no-clock-support;
2647                 qcom,appsbl-qseecom-support;
2648                 qcom,msm-bus,name = "qseecom-noc";
2649                 qcom,msm-bus,num-cases = <4>;
2650                 qcom,msm-bus,num-paths = <1>;
2651                 qcom,msm-bus,vectors-KBps =
2652                                 <55 512 0 0>,
2653                                 <55 512 0 0>,
2654                                 <55 512 120000 1200000>,
2655                                 <55 512 393600 3936000>;
2656                 clock-names = "core_clk_src", "core_clk",
2657                                 "iface_clk", "bus_clk";
2658                 clocks = <&clock_gcc clk_ce1_clk>,
2659                          <&clock_gcc clk_qseecom_ce1_clk>,
2660                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2661                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2662                 qcom,ce-opp-freq = <171430000>;
2663                 qcom,qsee-reentrancy-support = <2>;
2664         };
2665
2666         qcom,qbt1000 {
2667                 compatible = "qcom,qbt1000";
2668                 qcom,fingerprint-sensor-ssc-spi-conn {
2669                         qcom,spi-port-id = <2>;
2670                         qcom,spi-port-slave-index = <0>;
2671                         qcom,tz-subsys-id = <1>;
2672                         qcom,ssc-subsys-id = <5>;
2673                         clock-frequency = <15000000>;
2674                 };
2675         };
2676
2677         qcom,sensor-information {
2678                 compatible = "qcom,sensor-information";
2679                 sensor_information0: qcom,sensor-information-0 {
2680                         qcom,sensor-type = "tsens";
2681                         qcom,sensor-name = "tsens_tz_sensor0";
2682                         qcom,scaling-factor = <10>;
2683                 };
2684
2685                 sensor_information1: qcom,sensor-information-1 {
2686                         qcom,sensor-type =  "tsens";
2687                         qcom,sensor-name = "tsens_tz_sensor1";
2688                         qcom,alias-name = "pop_mem";
2689                         qcom,scaling-factor = <10>;
2690                 };
2691
2692                 sensor_information2: qcom,sensor-information-2 {
2693                         qcom,sensor-type =  "tsens";
2694                         qcom,sensor-name = "tsens_tz_sensor2";
2695                         qcom,scaling-factor = <10>;
2696                 };
2697
2698                 sensor_information3: qcom,sensor-information-3 {
2699                         qcom,sensor-type =  "tsens";
2700                         qcom,sensor-name = "tsens_tz_sensor3";
2701                         qcom,scaling-factor = <10>;
2702                 };
2703
2704                 sensor_information4: qcom,sensor-information-4 {
2705                         qcom,sensor-type = "tsens";
2706                         qcom,sensor-name = "tsens_tz_sensor4";
2707                         qcom,scaling-factor = <10>;
2708                 };
2709
2710                 sensor_information5: qcom,sensor-information-5 {
2711                         qcom,sensor-type = "tsens";
2712                         qcom,sensor-name = "tsens_tz_sensor5";
2713                         qcom,scaling-factor = <10>;
2714                 };
2715
2716                 sensor_information6: qcom,sensor-information-6 {
2717                         qcom,sensor-type = "tsens";
2718                         qcom,sensor-name = "tsens_tz_sensor6";
2719                         qcom,scaling-factor = <10>;
2720                 };
2721
2722                 sensor_information7: qcom,sensor-information-7 {
2723                         qcom,sensor-type = "tsens";
2724                         qcom,sensor-name = "tsens_tz_sensor7";
2725                         qcom,scaling-factor = <10>;
2726                 };
2727
2728                 sensor_information8: qcom,sensor-information-8 {
2729                         qcom,sensor-type = "tsens";
2730                         qcom,sensor-name = "tsens_tz_sensor8";
2731                         qcom,scaling-factor = <10>;
2732                 };
2733
2734                 sensor_information9: qcom,sensor-information-9 {
2735                         qcom,sensor-type = "tsens";
2736                         qcom,sensor-name = "tsens_tz_sensor9";
2737                         qcom,scaling-factor = <10>;
2738                 };
2739
2740                 sensor_information10: qcom,sensor-information-10 {
2741                         qcom,sensor-type = "tsens";
2742                         qcom,sensor-name = "tsens_tz_sensor10";
2743                         qcom,scaling-factor = <10>;
2744                 };
2745
2746                 sensor_information11: qcom,sensor-information-11 {
2747                         qcom,sensor-type = "tsens";
2748                         qcom,sensor-name = "tsens_tz_sensor11";
2749                         qcom,scaling-factor = <10>;
2750                 };
2751
2752                 sensor_information12: qcom,sensor-information-12 {
2753                         qcom,sensor-type = "tsens";
2754                         qcom,sensor-name = "tsens_tz_sensor12";
2755                         qcom,scaling-factor = <10>;
2756                 };
2757
2758                 sensor_information13: qcom,sensor-information-13 {
2759                         qcom,sensor-type = "tsens";
2760                         qcom,sensor-name = "tsens_tz_sensor13";
2761                         qcom,scaling-factor = <10>;
2762                 };
2763
2764                 sensor_information14: qcom,sensor-information-14 {
2765                         qcom,sensor-type = "tsens";
2766                         qcom,sensor-name = "tsens_tz_sensor14";
2767                         qcom,scaling-factor = <10>;
2768                 };
2769
2770                 sensor_information15: qcom,sensor-information-15 {
2771                         qcom,sensor-type = "tsens";
2772                         qcom,sensor-name = "tsens_tz_sensor15";
2773                         qcom,alias-name = "gpu";
2774                         qcom,scaling-factor = <10>;
2775                 };
2776
2777                 sensor_information16: qcom,sensor-information-16 {
2778                         qcom,sensor-type =  "alarm";
2779                         qcom,sensor-name = "pm8994_tz";
2780                         qcom,scaling-factor = <1000>;
2781                 };
2782
2783                 sensor_information17: qcom,sensor-information-17 {
2784                         qcom,sensor-type =  "adc";
2785                         qcom,sensor-name = "msm_therm";
2786                 };
2787
2788                 sensor_information18: qcom,sensor-information-18 {
2789                         qcom,sensor-type =  "adc";
2790                         qcom,sensor-name = "emmc_therm";
2791                 };
2792
2793                 sensor_information19: qcom,sensor-information-19 {
2794                         qcom,sensor-type =  "adc";
2795                         qcom,sensor-name = "pa_therm0";
2796                 };
2797
2798                 sensor_information20: qcom,sensor-information-20 {
2799                         qcom,sensor-type =  "adc";
2800                         qcom,sensor-name = "pa_therm1";
2801                 };
2802
2803                 sensor_information21: qcom,sensor-information-21 {
2804                         qcom,sensor-type =  "adc";
2805                         qcom,sensor-name = "quiet_therm";
2806                 };
2807                 sensor_information22: qcom,sensor-information-22 {
2808                         qcom,sensor-type =  "llm";
2809                         qcom,sensor-name = "DLMt_APC1";
2810                 };
2811                 sensor_information23: qcom,sensor-information-23 {
2812                         qcom,sensor-type =  "llm";
2813                         qcom,sensor-name = "LLM_m4m0";
2814                 };
2815                 sensor_information24: qcom,sensor-information-24 {
2816                         qcom,sensor-type =  "llm";
2817                         qcom,sensor-name = "LLM_cp10";
2818                 };
2819                 sensor_information25: qcom,sensor-information-25 {
2820                         qcom,sensor-type =  "llm";
2821                         qcom,sensor-name = "LLM_l3--";
2822                 };
2823                 sensor_information26: qcom,sensor-information-26 {
2824                         qcom,sensor-type =  "llm";
2825                         qcom,sensor-name = "LLM_cp01";
2826                 };
2827                 sensor_information27: qcom,sensor-information-27 {
2828                         qcom,sensor-type =  "llm";
2829                         qcom,sensor-name = "LLM_cp00";
2830                 };
2831                 sensor_information28: qcom,sensor-information-28 {
2832                         qcom,sensor-type =  "llm";
2833                         qcom,sensor-name = "LLM_l21-";
2834                 };
2835                 sensor_information29: qcom,sensor-information-29 {
2836                         qcom,sensor-type =  "llm";
2837                         qcom,sensor-name = "LLM_cp11";
2838                 };
2839                 sensor_information30: qcom,sensor-information-30 {
2840                         qcom,sensor-type =  "llm";
2841                         qcom,sensor-name = "LLM_l20-";
2842                 };
2843                 sensor_information31: qcom,sensor-information-31 {
2844                         qcom,sensor-type = "tsens";
2845                         qcom,sensor-name = "tsens_tz_sensor16";
2846                         qcom,scaling-factor = <10>;
2847                 };
2848                 sensor_information32: qcom,sensor-information-32 {
2849                         qcom,sensor-type = "tsens";
2850                         qcom,sensor-name = "tsens_tz_sensor17";
2851                         qcom,scaling-factor = <10>;
2852                 };
2853                 sensor_information33: qcom,sensor-information-33 {
2854                         qcom,sensor-type = "tsens";
2855                         qcom,sensor-name = "tsens_tz_sensor18";
2856                         qcom,scaling-factor = <10>;
2857                 };
2858                 sensor_information34: qcom,sensor-information-34 {
2859                         qcom,sensor-type = "tsens";
2860                         qcom,sensor-name = "tsens_tz_sensor19";
2861                         qcom,scaling-factor = <10>;
2862                 };
2863                 sensor_information35: qcom,sensor-information-35 {
2864                         qcom,sensor-type = "tsens";
2865                         qcom,sensor-name = "tsens_tz_sensor20";
2866                         qcom,scaling-factor = <10>;
2867                 };
2868         };
2869
2870         mitigation_profile0: qcom,limit_info-0 {
2871                 qcom,temperature-sensor = <&sensor_information4>;
2872                 qcom,boot-frequency-mitigate;
2873                 qcom,hotplug-mitigation-enable;
2874         };
2875
2876         mitigation_profile1: qcom,limit_info-1 {
2877                 qcom,temperature-sensor = <&sensor_information6>;
2878                 qcom,boot-frequency-mitigate;
2879                 qcom,hotplug-mitigation-enable;
2880         };
2881
2882         mitigation_profile2: qcom,limit_info-2 {
2883                 qcom,temperature-sensor = <&sensor_information9>;
2884                 qcom,boot-frequency-mitigate;
2885                 qcom,hotplug-mitigation-enable;
2886         };
2887
2888         mitigation_profile3: qcom,limit_info-3 {
2889                 qcom,temperature-sensor = <&sensor_information11>;
2890                 qcom,boot-frequency-mitigate;
2891                 qcom,hotplug-mitigation-enable;
2892         };
2893
2894         qcom,msm-thermal {
2895                 compatible = "qcom,msm-thermal";
2896                 reg = <0x70000 0x1000>;
2897                 qcom,sensor-id = <11>;
2898                 qcom,poll-ms = <100>;
2899                 qcom,limit-temp = <60>;
2900                 qcom,temp-hysteresis = <10>;
2901                 qcom,therm-reset-temp = <115>;
2902                 qcom,freq-step = <4>;
2903                 qcom,core-limit-temp = <70>;
2904                 qcom,core-temp-hysteresis = <10>;
2905                 qcom,hotplug-temp = <105>;
2906                 qcom,hotplug-temp-hysteresis = <40>;
2907                 qcom,freq-mitigation-temp = <90>;
2908                 qcom,freq-mitigation-temp-hysteresis = <40>;
2909                 qcom,freq-mitigation-value = <576000>;
2910                 qcom,online-hotplug-core;
2911                 qcom,synchronous-cluster-id = <0 1>;
2912                 qcom,synchronous-cluster-map = <0 2 &CPU0 &CPU1>,
2913                         <1 2 &CPU2 &CPU3>;
2914
2915                 qcom,vdd-restriction-temp = <5>;
2916                 qcom,vdd-restriction-temp-hysteresis = <10>;
2917
2918                 vdd-dig-supply = <&pm8994_s1_floor_corner>;
2919                 vdd-gfx-supply = <&gfx_vreg>;
2920
2921                 qcom,vdd-dig-rstr{
2922                         qcom,vdd-rstr-reg = "vdd-dig";
2923                         qcom,levels = <5 7 7>; /* Nominal, Super Turbo, Super Turbo */
2924                         qcom,min-level = <1>; /* No Request */
2925                 };
2926
2927                 qcom,vdd-gfx-rstr{
2928                         qcom,vdd-rstr-reg = "vdd-gfx";
2929                         qcom,levels = <4 7 7>; /* Nominal, Turbo, Turbo */
2930                         qcom,min-level = <1>; /* No Request */
2931                 };
2932
2933                 msm_thermal_freq: qcom,vdd-apps-rstr{
2934                         qcom,vdd-rstr-reg = "vdd-apps";
2935                         qcom,levels = <576000 600000 600000>;
2936                         qcom,freq-req;
2937                 };
2938         };
2939
2940         qcom,bcl {
2941                 compatible = "qcom,bcl";
2942                 qcom,bcl-enable;
2943                 qcom,bcl-framework-interface;
2944                 qcom,bcl-freq-control-list = <&CPU2 &CPU3>;
2945                 qcom,bcl-hotplug-list = <&CPU2 &CPU3>;
2946                 qcom,bcl-soc-hotplug-list = <&CPU2 &CPU3>;
2947                 qcom,ibat-monitor {
2948                         qcom,low-threshold-uamp = <3400000>;
2949                         qcom,high-threshold-uamp = <4200000>;
2950                         qcom,mitigation-freq-khz = <576000>;
2951                         qcom,vph-high-threshold-uv = <3500000>;
2952                         qcom,vph-low-threshold-uv = <3300000>;
2953                         qcom,soc-low-threshold = <10>;
2954                         qcom,thermal-handle = <&msm_thermal_freq>;
2955                 };
2956         };
2957
2958         qcom,memshare {
2959                 compatible = "qcom,memshare";
2960
2961                 qcom,client_1 {
2962                         compatible = "qcom,memshare-peripheral";
2963                         qcom,peripheral-size = <0x200000>;
2964                         qcom,client-id = <0>;
2965                         label = "modem";
2966                 };
2967
2968                 qcom,client_2 {
2969                         compatible = "qcom,memshare-peripheral";
2970                         qcom,peripheral-size = <0x300000>;
2971                         qcom,client-id = <2>;
2972                         label = "modem";
2973                 };
2974
2975                 qcom,client_3 {
2976                         compatible = "qcom,memshare-peripheral";
2977                         qcom,peripheral-size = <0x0>;
2978                         qcom,client-id = <1>;
2979                         label = "modem";
2980                 };
2981         };
2982
2983         qcom,msm-core@70000 {
2984                 compatible = "qcom,apss-core-ea";
2985                 reg = <0x70000 0x1000>;
2986                 qcom,low-hyst-temp = <10>;
2987                 qcom,high-hyst-temp = <5>;
2988                 qcom,polling-interval = <50>;
2989
2990                 ea0: ea0 {
2991                         sensor = <&sensor_information4>;
2992                 };
2993
2994                 ea1: ea1 {
2995                         sensor = <&sensor_information6>;
2996                 };
2997
2998                 ea2: ea2 {
2999                         sensor = <&sensor_information9>;
3000                 };
3001
3002                 ea3: ea3 {
3003                         sensor = <&sensor_information11>;
3004                 };
3005         };
3006
3007         cpuss_dump {
3008                 compatible = "qcom,cpuss-dump";
3009                 qcom,l2_dump0 {
3010                         qcom,dump-node = <&L2_0>;
3011                         qcom,dump-id = <0xC0>;
3012                 };
3013                 qcom,l2_dump1 {
3014                         qcom,dump-node = <&L2_1>;
3015                         qcom,dump-id = <0xC1>;
3016                 };
3017                 qcom,l1_d_dump0 {
3018                         qcom,dump-node = <&L1_D_0>;
3019                         qcom,dump-id = <0x80>;
3020                 };
3021                 qcom,l1_d_dump1 {
3022                         qcom,dump-node = <&L1_D_1>;
3023                         qcom,dump-id = <0x81>;
3024                 };
3025                 qcom,l1_d_dump100 {
3026                         qcom,dump-node = <&L1_D_100>;
3027                         qcom,dump-id = <0x82>;
3028                 };
3029                 qcom,l1_d_dump101 {
3030                         qcom,dump-node = <&L1_D_101>;
3031                         qcom,dump-id = <0x83>;
3032                 };
3033                 qcom,l1_tlb_dump0 {
3034                         qcom,dump-node = <&L1_TLB_0>;
3035                         qcom,dump-id = <0x20>;
3036                 };
3037                 qcom,l1_tlb_dump1 {
3038                         qcom,dump-node = <&L1_TLB_1>;
3039                         qcom,dump-id = <0x21>;
3040                 };
3041                 qcom,l1_tlb_dump100 {
3042                         qcom,dump-node = <&L1_TLB_100>;
3043                         qcom,dump-id = <0x22>;
3044                 };
3045                 qcom,l1_tlb_dump101 {
3046                         qcom,dump-node = <&L1_TLB_101>;
3047                         qcom,dump-id = <0x23>;
3048                 };
3049         };
3050
3051         qcom_tzlog: tz-log@66bf720 {
3052                 compatible = "qcom,tz-log";
3053                 reg = <0x066bf720 0x2000>;
3054                 qcom,hyplog-enabled;
3055                 hyplog-address-offset = <0x410>; /* 0x066BFB30 */
3056                 hyplog-size-offset = <0x414>;    /* 0x066BFB34 */
3057         };
3058
3059         sound-9335 {
3060                 compatible = "qcom,msm8996-asoc-snd-tasha";
3061                 qcom,model = "msm8996-tasha-snd-card";
3062
3063                 qcom,audio-routing =
3064                         "AIF4 VI", "MCLK",
3065                         "RX_BIAS", "MCLK",
3066                         "MADINPUT", "MCLK",
3067                         "AMIC2", "MIC BIAS2",
3068                         "MIC BIAS2", "Headset Mic",
3069                         "AMIC3", "MIC BIAS2",
3070                         "MIC BIAS2", "ANCRight Headset Mic",
3071                         "AMIC4", "MIC BIAS2",
3072                         "MIC BIAS2", "ANCLeft Headset Mic",
3073                         "AMIC5", "MIC BIAS3",
3074                         "MIC BIAS3", "Handset Mic",
3075                         "AMIC6", "MIC BIAS4",
3076                         "MIC BIAS4", "Analog Mic6",
3077                         "DMIC0", "MIC BIAS1",
3078                         "MIC BIAS1", "Digital Mic0",
3079                         "DMIC1", "MIC BIAS1",
3080                         "MIC BIAS1", "Digital Mic1",
3081                         "DMIC2", "MIC BIAS3",
3082                         "MIC BIAS3", "Digital Mic2",
3083                         "DMIC3", "MIC BIAS3",
3084                         "MIC BIAS3", "Digital Mic3",
3085                         "DMIC4", "MIC BIAS4",
3086                         "MIC BIAS4", "Digital Mic4",
3087                         "DMIC5", "MIC BIAS4",
3088                         "MIC BIAS4", "Digital Mic5",
3089                         "SpkrLeft IN", "SPK1 OUT",
3090                         "SpkrRight IN", "SPK2 OUT";
3091
3092                 qcom,msm-mbhc-hphl-swh = <0>;
3093                 qcom,msm-mbhc-gnd-swh = <0>;
3094                 qcom,tasha-mclk-clk-freq = <9600000>;
3095                 asoc-platform = <&pcm0>, <&pcm1>, <&pcm2>, <&voip>, <&voice>,
3096                                 <&loopback>, <&compress>, <&hostless>,
3097                                 <&afe>, <&lsm>, <&routing>, <&cpe>,
3098                                 <&compr>, <&pcmnoirq>, <&cpe3>;
3099                 asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", "msm-pcm-dsp.2",
3100                                 "msm-voip-dsp", "msm-pcm-voice", "msm-pcm-loopback",
3101                                 "msm-compress-dsp", "msm-pcm-hostless", "msm-pcm-afe",
3102                                 "msm-lsm-client", "msm-pcm-routing", "msm-cpe-lsm",
3103                                 "msm-compr-dsp", "msm-pcm-dsp-noirq",
3104                                 "msm-cpe-lsm.3";
3105                 asoc-cpu = <&dai_pri_auxpcm>, <&dai_sec_auxpcm>, <&dai_hdmi>, <&dai_mi2s>,
3106                                 <&sb_0_rx>, <&sb_0_tx>, <&sb_1_rx>, <&sb_1_tx>,
3107                                 <&sb_2_rx>, <&sb_2_tx>, <&sb_3_rx>, <&sb_3_tx>,
3108                                 <&sb_4_rx>, <&sb_4_tx>, <&sb_5_tx>, <&afe_pcm_rx>,
3109                                 <&afe_pcm_tx>, <&afe_proxy_rx>, <&afe_proxy_tx>,
3110                                 <&incall_record_rx>, <&incall_record_tx>,
3111                                 <&incall_music_rx>, <&incall_music2_rx>,
3112                                 <&sb_5_rx>, <&sb_6_rx>,
3113                                 <&usb_audio_rx>, <&usb_audio_tx>;
3114                 asoc-cpu-names = "msm-dai-q6-auxpcm.1", "msm-dai-q6-auxpcm.2",
3115                                 "msm-dai-q6-hdmi.8", "msm-dai-q6-mi2s.2",
3116                                 "msm-dai-q6-dev.16384", "msm-dai-q6-dev.16385",
3117                                 "msm-dai-q6-dev.16386", "msm-dai-q6-dev.16387",
3118                                 "msm-dai-q6-dev.16388", "msm-dai-q6-dev.16389",
3119                                 "msm-dai-q6-dev.16390", "msm-dai-q6-dev.16391",
3120                                 "msm-dai-q6-dev.16392", "msm-dai-q6-dev.16393",
3121                                 "msm-dai-q6-dev.16395", "msm-dai-q6-dev.224",
3122                                 "msm-dai-q6-dev.225", "msm-dai-q6-dev.241",
3123                                 "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771",
3124                                 "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773",
3125                                 "msm-dai-q6-dev.32770", "msm-dai-q6-dev.16394",
3126                                 "msm-dai-q6-dev.16396",
3127                                 "msm-dai-q6-dev.28672", "msm-dai-q6-dev.28673";
3128                 asoc-codec = <&stub_codec>;
3129                 asoc-codec-names = "msm-stub-codec.1";
3130         };
3131
3132         qcom,msm-adsp-loader {
3133                 status = "ok";
3134                 compatible = "qcom,adsp-loader";
3135                 qcom,adsp-state = <0>;
3136         };
3137
3138         qcom,msm-audio-ion {
3139                 compatible = "qcom,msm-audio-ion";
3140                 qcom,smmu-version = <2>;
3141                 qcom,smmu-enabled;
3142                 iommus = <&lpass_q6_smmu 1>;
3143         };
3144
3145         pcm0: qcom,msm-pcm {
3146                 compatible = "qcom,msm-pcm-dsp";
3147                 qcom,msm-pcm-dsp-id = <0>;
3148         };
3149
3150         pcm1: qcom,msm-pcm-low-latency {
3151                 compatible = "qcom,msm-pcm-dsp";
3152                 qcom,msm-pcm-dsp-id = <1>;
3153                 qcom,msm-pcm-low-latency;
3154                 qcom,latency-level = "regular";
3155         };
3156
3157         pcm2: qcom,msm-ultra-low-latency {
3158                 compatible = "qcom,msm-pcm-dsp";
3159                 qcom,msm-pcm-dsp-id = <2>;
3160                 qcom,msm-pcm-low-latency;
3161                 qcom,latency-level = "ultra";
3162         };
3163
3164         routing: qcom,msm-pcm-routing {
3165                 compatible = "qcom,msm-pcm-routing";
3166         };
3167
3168         compr: qcom,msm-compr-dsp {
3169                 compatible = "qcom,msm-compr-dsp";
3170         };
3171
3172         compress: qcom,msm-compress-dsp {
3173                 compatible = "qcom,msm-compress-dsp";
3174         };
3175
3176         pcmnoirq: qcom,msm-pcm-dsp-noirq {
3177                 compatible = "qcom,msm-pcm-dsp-noirq";
3178                 qcom,msm-pcm-low-latency;
3179                 qcom,latency-level = "ultra";
3180         };
3181
3182         voip: qcom,msm-voip-dsp {
3183                 compatible = "qcom,msm-voip-dsp";
3184         };
3185
3186         voice: qcom,msm-pcm-voice {
3187                 compatible = "qcom,msm-pcm-voice";
3188                 qcom,destroy-cvd;
3189         };
3190
3191         stub_codec: qcom,msm-stub-codec {
3192                 compatible = "qcom,msm-stub-codec";
3193         };
3194
3195         qcom,msm-dai-fe {
3196                 compatible = "qcom,msm-dai-fe";
3197         };
3198
3199         afe: qcom,msm-pcm-afe {
3200                 compatible = "qcom,msm-pcm-afe";
3201         };
3202
3203         dai_hdmi: qcom,msm-dai-q6-hdmi {
3204                 compatible = "qcom,msm-dai-q6-hdmi";
3205                 qcom,msm-dai-q6-dev-id = <8>;
3206         };
3207
3208         lsm: qcom,msm-lsm-client {
3209                 compatible = "qcom,msm-lsm-client";
3210         };
3211
3212         loopback: qcom,msm-pcm-loopback {
3213                 compatible = "qcom,msm-pcm-loopback";
3214         };
3215
3216         cpe: qcom,msm-cpe-lsm {
3217                 compatible = "qcom,msm-cpe-lsm";
3218                 qcom,msm-cpe-lsm-id = <1>;
3219         };
3220
3221         cpe3: qcom,msm-cpe-lsm@3 {
3222                 compatible = "qcom,msm-cpe-lsm";
3223                 qcom,msm-cpe-lsm-id = <3>;
3224         };
3225
3226         qcom,msm-dai-q6 {
3227                 compatible = "qcom,msm-dai-q6";
3228                 sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
3229                         compatible = "qcom,msm-dai-q6-dev";
3230                         qcom,msm-dai-q6-dev-id = <16384>;
3231                 };
3232
3233                 sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
3234                         compatible = "qcom,msm-dai-q6-dev";
3235                         qcom,msm-dai-q6-dev-id = <16385>;
3236                 };
3237
3238                 sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
3239                         compatible = "qcom,msm-dai-q6-dev";
3240                         qcom,msm-dai-q6-dev-id = <16386>;
3241                 };
3242
3243                 sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
3244                         compatible = "qcom,msm-dai-q6-dev";
3245                         qcom,msm-dai-q6-dev-id = <16387>;
3246                 };
3247
3248                 sb_2_rx: qcom,msm-dai-q6-sb-2-rx {
3249                         compatible = "qcom,msm-dai-q6-dev";
3250                         qcom,msm-dai-q6-dev-id = <16388>;
3251                 };
3252
3253                 sb_2_tx: qcom,msm-dai-q6-sb-2-tx {
3254                         compatible = "qcom,msm-dai-q6-dev";
3255                         qcom,msm-dai-q6-dev-id = <16389>;
3256                 };
3257
3258                 sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
3259                         compatible = "qcom,msm-dai-q6-dev";
3260                         qcom,msm-dai-q6-dev-id = <16390>;
3261                 };
3262
3263                 sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
3264                         compatible = "qcom,msm-dai-q6-dev";
3265                         qcom,msm-dai-q6-dev-id = <16391>;
3266                 };
3267
3268                 sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
3269                         compatible = "qcom,msm-dai-q6-dev";
3270                         qcom,msm-dai-q6-dev-id = <16392>;
3271                 };
3272
3273                 sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
3274                         compatible = "qcom,msm-dai-q6-dev";
3275                         qcom,msm-dai-q6-dev-id = <16393>;
3276                 };
3277
3278                 sb_5_tx: qcom,msm-dai-q6-sb-5-tx {
3279                         compatible = "qcom,msm-dai-q6-dev";
3280                         qcom,msm-dai-q6-dev-id = <16395>;
3281                 };
3282
3283                 bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
3284                         compatible = "qcom,msm-dai-q6-dev";
3285                         qcom,msm-dai-q6-dev-id = <12288>;
3286                 };
3287
3288                 bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
3289                         compatible = "qcom,msm-dai-q6-dev";
3290                         qcom,msm-dai-q6-dev-id = <12289>;
3291                 };
3292
3293                 afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
3294                         compatible = "qcom,msm-dai-q6-dev";
3295                         qcom,msm-dai-q6-dev-id = <224>;
3296                 };
3297
3298                 afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
3299                         compatible = "qcom,msm-dai-q6-dev";
3300                         qcom,msm-dai-q6-dev-id = <225>;
3301                 };
3302
3303                 afe_proxy_rx: com,msm-dai-q6-afe-proxy-rx {
3304                         compatible = "qcom,msm-dai-q6-dev";
3305                         qcom,msm-dai-q6-dev-id = <241>;
3306                 };
3307
3308                 afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
3309                         compatible = "qcom,msm-dai-q6-dev";
3310                         qcom,msm-dai-q6-dev-id = <240>;
3311                 };
3312
3313                 incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
3314                         compatible = "qcom,msm-dai-q6-dev";
3315                         qcom,msm-dai-q6-dev-id = <32771>;
3316                 };
3317
3318                 incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
3319                         compatible = "qcom,msm-dai-q6-dev";
3320                         qcom,msm-dai-q6-dev-id = <32772>;
3321                 };
3322
3323                 incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
3324                         compatible = "qcom,msm-dai-q6-dev";
3325                         qcom,msm-dai-q6-dev-id = <32773>;
3326                 };
3327
3328                 incall_music2_rx: qcom,msm-dai-q6-incall-music-2-rx {
3329                         compatible = "qcom,msm-dai-q6-dev";
3330                         qcom,msm-dai-q6-dev-id = <32770>;
3331                 };
3332
3333                 sb_5_rx: qcom,msm-dai-q6-sb-5-rx {
3334                         compatible = "qcom,msm-dai-q6-dev";
3335                         qcom,msm-dai-q6-dev-id = <16394>;
3336                 };
3337
3338                 sb_6_rx: qcom,msm-dai-q6-sb-6-rx {
3339                         compatible = "qcom,msm-dai-q6-dev";
3340                         qcom,msm-dai-q6-dev-id = <16396>;
3341                 };
3342
3343                 usb_audio_rx: qcom,msm-dai-q6-usb-audio-rx {
3344                         compatible = "qcom,msm-dai-q6-dev";
3345                         qcom,msm-dai-q6-dev-id = <28672>;
3346                 };
3347
3348                 usb_audio_tx: qcom,msm-dai-q6-usb-audio-tx {
3349                         compatible = "qcom,msm-dai-q6-dev";
3350                         qcom,msm-dai-q6-dev-id = <28673>;
3351                 };
3352         };
3353
3354         dai_pri_auxpcm: qcom,msm-pri-auxpcm {
3355                 compatible = "qcom,msm-auxpcm-dev";
3356                 qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
3357                 qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
3358                 qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
3359                 qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
3360                 qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
3361                 qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
3362                 qcom,msm-cpudai-auxpcm-data = <0>, <0>;
3363                 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
3364                 qcom,msm-auxpcm-interface = "primary";
3365                 qcom,msm-cpudai-afe-clk-ver = <2>;
3366                 pinctrl-names = "default", "sleep";
3367                 pinctrl-0 = <&pri_aux_pcm_active &pri_aux_pcm_din_active
3368                              &pri_aux_pcm_dout_active>;
3369                 pinctrl-1 = <&pri_aux_pcm_sleep &pri_aux_pcm_din_sleep
3370                              &pri_aux_pcm_dout_sleep>;
3371         };
3372
3373         dai_sec_auxpcm: qcom,msm-sec-auxpcm {
3374                 compatible = "qcom,msm-auxpcm-dev";
3375                 qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
3376                 qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
3377                 qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
3378                 qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
3379                 qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
3380                 qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
3381                 qcom,msm-cpudai-auxpcm-data = <0>, <0>;
3382                 qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
3383                 qcom,msm-auxpcm-interface = "secondary";
3384                 qcom,msm-cpudai-afe-clk-ver = <2>;
3385         };
3386
3387         qcom,msm-dai-mi2s {
3388                 compatible = "qcom,msm-dai-mi2s";
3389                 dai_mi2s_sec: qcom,msm-dai-q6-mi2s-sec {
3390                         compatible = "qcom,msm-dai-q6-mi2s";
3391                         qcom,msm-dai-q6-mi2s-dev-id = <1>;
3392                         qcom,msm-mi2s-rx-lines = <1>;
3393                         qcom,msm-mi2s-tx-lines = <0>;
3394                 };
3395
3396                 dai_mi2s: qcom,msm-dai-q6-mi2s-tert {
3397                         compatible = "qcom,msm-dai-q6-mi2s";
3398                         qcom,msm-dai-q6-mi2s-dev-id = <2>;
3399                         qcom,msm-mi2s-rx-lines = <2>;
3400                         qcom,msm-mi2s-tx-lines = <1>;
3401                         pinctrl-names = "default", "sleep";
3402                         pinctrl-0 = <&tert_mi2s_active &tert_mi2s_sd0_active>;
3403                         pinctrl-1 = <&tert_mi2s_sleep &tert_mi2s_sd0_sleep>;
3404                 };
3405
3406                 dai_mi2s_quat: qcom,msm-dai-q6-mi2s-quat {
3407                         compatible = "qcom,msm-dai-q6-mi2s";
3408                         qcom,msm-dai-q6-mi2s-dev-id = <3>;
3409                         qcom,msm-mi2s-rx-lines = <1>;
3410                         qcom,msm-mi2s-tx-lines = <0>;
3411                 };
3412         };
3413
3414         qcom,msm-dai-tdm-pri-rx {
3415                 compatible = "qcom,msm-dai-tdm";
3416                 qcom,msm-cpudai-tdm-group-id = <37120>;
3417                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3418                 qcom,msm-cpudai-tdm-group-port-id = <36864 36866 36868 36870>;
3419                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3420                 qcom,msm-cpudai-tdm-clk-internal = <1>;
3421                 qcom,msm-cpudai-tdm-sync-mode = <0>;
3422                 qcom,msm-cpudai-tdm-sync-src = <1>;
3423                 qcom,msm-cpudai-tdm-data-out = <0>;
3424                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3425                 qcom,msm-cpudai-tdm-data-delay = <1>;
3426                 qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>;
3427                 dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 {
3428                         compatible = "qcom,msm-dai-q6-tdm";
3429                         qcom,msm-cpudai-tdm-dev-id = <36864>;
3430                         qcom,msm-cpudai-tdm-data-align = <0>;
3431                 };
3432
3433                 dai_pri_tdm_rx_1: qcom,msm-dai-q6-tdm-pri-rx-1 {
3434                         compatible = "qcom,msm-dai-q6-tdm";
3435                         qcom,msm-cpudai-tdm-dev-id = <36866>;
3436                         qcom,msm-cpudai-tdm-data-align = <0>;
3437                 };
3438
3439                 dai_pri_tdm_rx_2: qcom,msm-dai-q6-tdm-pri-rx-2 {
3440                         compatible = "qcom,msm-dai-q6-tdm";
3441                         qcom,msm-cpudai-tdm-dev-id = <36868>;
3442                         qcom,msm-cpudai-tdm-data-align = <0>;
3443                 };
3444
3445                 dai_pri_tdm_rx_3: qcom,msm-dai-q6-tdm-pri-rx-3 {
3446                         compatible = "qcom,msm-dai-q6-tdm";
3447                         qcom,msm-cpudai-tdm-dev-id = <36870>;
3448                         qcom,msm-cpudai-tdm-data-align = <0>;
3449                 };
3450         };
3451
3452         qcom,msm-dai-tdm-pri-tx {
3453                 compatible = "qcom,msm-dai-tdm";
3454                 qcom,msm-cpudai-tdm-group-id = <37121>;
3455                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3456                 qcom,msm-cpudai-tdm-group-port-id = <36865 36867 36869 36871>;
3457                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3458                 qcom,msm-cpudai-tdm-clk-internal = <1>;
3459                 qcom,msm-cpudai-tdm-sync-mode = <0>;
3460                 qcom,msm-cpudai-tdm-sync-src = <1>;
3461                 qcom,msm-cpudai-tdm-data-out = <0>;
3462                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3463                 qcom,msm-cpudai-tdm-data-delay = <1>;
3464                 qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>;
3465                 dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 {
3466                         compatible = "qcom,msm-dai-q6-tdm";
3467                         qcom,msm-cpudai-tdm-dev-id = <36865>;
3468                         qcom,msm-cpudai-tdm-data-align = <0>;
3469                 };
3470
3471                 dai_pri_tdm_tx_1: qcom,msm-dai-q6-tdm-pri-tx-1 {
3472                         compatible = "qcom,msm-dai-q6-tdm";
3473                         qcom,msm-cpudai-tdm-dev-id = <36867>;
3474                         qcom,msm-cpudai-tdm-data-align = <0>;
3475                 };
3476
3477                 dai_pri_tdm_tx_2: qcom,msm-dai-q6-tdm-pri-tx-2 {
3478                         compatible = "qcom,msm-dai-q6-tdm";
3479                         qcom,msm-cpudai-tdm-dev-id = <36869>;
3480                         qcom,msm-cpudai-tdm-data-align = <0>;
3481                 };
3482
3483                 dai_pri_tdm_tx_3: qcom,msm-dai-q6-tdm-pri-tx-3 {
3484                         compatible = "qcom,msm-dai-q6-tdm";
3485                         qcom,msm-cpudai-tdm-dev-id = <36871>;
3486                         qcom,msm-cpudai-tdm-data-align = <0>;
3487                 };
3488         };
3489
3490         qcom,msm-dai-tdm-sec-rx {
3491                 compatible = "qcom,msm-dai-tdm";
3492                 qcom,msm-cpudai-tdm-group-id = <37136>;
3493                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3494                 qcom,msm-cpudai-tdm-group-port-id = <36880 36882 36884 36886>;
3495                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3496                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3497                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3498                 qcom,msm-cpudai-tdm-sync-src = <0>;
3499                 qcom,msm-cpudai-tdm-data-out = <0>;
3500                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3501                 qcom,msm-cpudai-tdm-data-delay = <0>;
3502                 dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 {
3503                         compatible = "qcom,msm-dai-q6-tdm";
3504                         qcom,msm-cpudai-tdm-dev-id = <36880>;
3505                         qcom,msm-cpudai-tdm-data-align = <0>;
3506                 };
3507
3508                 dai_sec_tdm_rx_1: qcom,msm-dai-q6-tdm-sec-rx-1 {
3509                         compatible = "qcom,msm-dai-q6-tdm";
3510                         qcom,msm-cpudai-tdm-dev-id = <36882>;
3511                         qcom,msm-cpudai-tdm-data-align = <0>;
3512                 };
3513
3514                 dai_sec_tdm_rx_2: qcom,msm-dai-q6-tdm-sec-rx-2 {
3515                         compatible = "qcom,msm-dai-q6-tdm";
3516                         qcom,msm-cpudai-tdm-dev-id = <36884>;
3517                         qcom,msm-cpudai-tdm-data-align = <0>;
3518                 };
3519
3520                 dai_sec_tdm_rx_3: qcom,msm-dai-q6-tdm-sec-rx-3 {
3521                         compatible = "qcom,msm-dai-q6-tdm";
3522                         qcom,msm-cpudai-tdm-dev-id = <36886>;
3523                         qcom,msm-cpudai-tdm-data-align = <0>;
3524                 };
3525         };
3526
3527         qcom,msm-dai-tdm-sec-tx {
3528                 compatible = "qcom,msm-dai-tdm";
3529                 qcom,msm-cpudai-tdm-group-id = <37137>;
3530                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3531                 qcom,msm-cpudai-tdm-group-port-id = <36881 36883 36885 36887>;
3532                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3533                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3534                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3535                 qcom,msm-cpudai-tdm-sync-src = <0>;
3536                 qcom,msm-cpudai-tdm-data-out = <0>;
3537                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3538                 qcom,msm-cpudai-tdm-data-delay = <0>;
3539                 dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 {
3540                         compatible = "qcom,msm-dai-q6-tdm";
3541                         qcom,msm-cpudai-tdm-dev-id = <36881>;
3542                         qcom,msm-cpudai-tdm-data-align = <0>;
3543                 };
3544
3545                 dai_sec_tdm_tx_1: qcom,msm-dai-q6-tdm-sec-tx-1 {
3546                         compatible = "qcom,msm-dai-q6-tdm";
3547                         qcom,msm-cpudai-tdm-dev-id = <36883>;
3548                         qcom,msm-cpudai-tdm-data-align = <0>;
3549                 };
3550
3551                 dai_sec_tdm_tx_2: qcom,msm-dai-q6-tdm-sec-tx-2 {
3552                         compatible = "qcom,msm-dai-q6-tdm";
3553                         qcom,msm-cpudai-tdm-dev-id = <36885>;
3554                         qcom,msm-cpudai-tdm-data-align = <0>;
3555                 };
3556
3557                 dai_sec_tdm_tx_3: qcom,msm-dai-q6-tdm-sec-tx-3 {
3558                         compatible = "qcom,msm-dai-q6-tdm";
3559                         qcom,msm-cpudai-tdm-dev-id = <36887>;
3560                         qcom,msm-cpudai-tdm-data-align = <0>;
3561                 };
3562         };
3563
3564         qcom,msm-dai-tdm-tert-rx {
3565                 compatible = "qcom,msm-dai-tdm";
3566                 qcom,msm-cpudai-tdm-group-id = <37152>;
3567                 qcom,msm-cpudai-tdm-group-num-ports = <5>;
3568                 qcom,msm-cpudai-tdm-group-port-id = <36896 36898 36900
3569                                                         36902 36904>;
3570                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3571                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3572                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3573                 qcom,msm-cpudai-tdm-sync-src = <0>;
3574                 qcom,msm-cpudai-tdm-data-out = <0>;
3575                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3576                 qcom,msm-cpudai-tdm-data-delay = <0>;
3577                 dai_tert_tdm_rx_0: qcom,msm-dai-q6-tdm-tert-rx-0 {
3578                         compatible = "qcom,msm-dai-q6-tdm";
3579                         qcom,msm-cpudai-tdm-dev-id = <36896>;
3580                         qcom,msm-cpudai-tdm-data-align = <0>;
3581                 };
3582
3583                 dai_tert_tdm_rx_1: qcom,msm-dai-q6-tdm-tert-rx-1 {
3584                         compatible = "qcom,msm-dai-q6-tdm";
3585                         qcom,msm-cpudai-tdm-dev-id = <36898>;
3586                         qcom,msm-cpudai-tdm-data-align = <0>;
3587                 };
3588
3589                 dai_tert_tdm_rx_2: qcom,msm-dai-q6-tdm-tert-rx-2 {
3590                         compatible = "qcom,msm-dai-q6-tdm";
3591                         qcom,msm-cpudai-tdm-dev-id = <36900>;
3592                         qcom,msm-cpudai-tdm-data-align = <0>;
3593                 };
3594
3595                 dai_tert_tdm_rx_3: qcom,msm-dai-q6-tdm-tert-rx-3 {
3596                         compatible = "qcom,msm-dai-q6-tdm";
3597                         qcom,msm-cpudai-tdm-dev-id = <36902>;
3598                         qcom,msm-cpudai-tdm-data-align = <0>;
3599                 };
3600
3601                 dai_tert_tdm_rx_4: qcom,msm-dai-q6-tdm-tert-rx-4 {
3602                         compatible = "qcom,msm-dai-q6-tdm";
3603                         qcom,msm-cpudai-tdm-dev-id = <36904>;
3604                         qcom,msm-cpudai-tdm-data-align = <0>;
3605                 };
3606         };
3607
3608         qcom,msm-dai-tdm-tert-tx {
3609                 compatible = "qcom,msm-dai-tdm";
3610                 qcom,msm-cpudai-tdm-group-id = <37153>;
3611                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3612                 qcom,msm-cpudai-tdm-group-port-id = <36897 36899 36901 36903>;
3613                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3614                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3615                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3616                 qcom,msm-cpudai-tdm-sync-src = <0>;
3617                 qcom,msm-cpudai-tdm-data-out = <0>;
3618                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3619                 qcom,msm-cpudai-tdm-data-delay = <0>;
3620                 dai_tert_tdm_tx_0: qcom,msm-dai-q6-tdm-tert-tx-0 {
3621                         compatible = "qcom,msm-dai-q6-tdm";
3622                         qcom,msm-cpudai-tdm-dev-id = <36897>;
3623                         qcom,msm-cpudai-tdm-data-align = <0>;
3624                 };
3625
3626                 dai_tert_tdm_tx_1: qcom,msm-dai-q6-tdm-tert-tx-1 {
3627                         compatible = "qcom,msm-dai-q6-tdm";
3628                         qcom,msm-cpudai-tdm-dev-id = <36899>;
3629                         qcom,msm-cpudai-tdm-data-align = <0>;
3630                 };
3631
3632                 dai_tert_tdm_tx_2: qcom,msm-dai-q6-tdm-tert-tx-2 {
3633                         compatible = "qcom,msm-dai-q6-tdm";
3634                         qcom,msm-cpudai-tdm-dev-id = <36901>;
3635                         qcom,msm-cpudai-tdm-data-align = <0>;
3636                 };
3637
3638                 dai_tert_tdm_tx_3: qcom,msm-dai-q6-tdm-tert-tx-3 {
3639                         compatible = "qcom,msm-dai-q6-tdm";
3640                         qcom,msm-cpudai-tdm-dev-id = <36903>;
3641                         qcom,msm-cpudai-tdm-data-align = <0>;
3642                 };
3643         };
3644
3645         qcom,msm-dai-tdm-quat-rx {
3646                 compatible = "qcom,msm-dai-tdm";
3647                 qcom,msm-cpudai-tdm-group-id = <37168>;
3648                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3649                 qcom,msm-cpudai-tdm-group-port-id = <36912 36914 36916 36918>;
3650                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3651                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3652                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3653                 qcom,msm-cpudai-tdm-sync-src = <0>;
3654                 qcom,msm-cpudai-tdm-data-out = <0>;
3655                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3656                 qcom,msm-cpudai-tdm-data-delay = <0>;
3657                 dai_quat_tdm_rx_0: qcom,msm-dai-q6-tdm-quat-rx-0 {
3658                         compatible = "qcom,msm-dai-q6-tdm";
3659                         qcom,msm-cpudai-tdm-dev-id = <36912>;
3660                         qcom,msm-cpudai-tdm-data-align = <0>;
3661                 };
3662
3663                 dai_quat_tdm_rx_1: qcom,msm-dai-q6-tdm-quat-rx-1 {
3664                         compatible = "qcom,msm-dai-q6-tdm";
3665                         qcom,msm-cpudai-tdm-dev-id = <36914>;
3666                         qcom,msm-cpudai-tdm-data-align = <0>;
3667                 };
3668
3669                 dai_quat_tdm_rx_2: qcom,msm-dai-q6-tdm-quat-rx-2 {
3670                         compatible = "qcom,msm-dai-q6-tdm";
3671                         qcom,msm-cpudai-tdm-dev-id = <36916>;
3672                         qcom,msm-cpudai-tdm-data-align = <0>;
3673                 };
3674
3675                 dai_quat_tdm_rx_3: qcom,msm-dai-q6-tdm-quat-rx-3 {
3676                         compatible = "qcom,msm-dai-q6-tdm";
3677                         qcom,msm-cpudai-tdm-dev-id = <36918>;
3678                         qcom,msm-cpudai-tdm-data-align = <0>;
3679                 };
3680         };
3681
3682         qcom,msm-dai-tdm-quat-tx {
3683                 compatible = "qcom,msm-dai-tdm";
3684                 qcom,msm-cpudai-tdm-group-id = <37169>;
3685                 qcom,msm-cpudai-tdm-group-num-ports = <4>;
3686                 qcom,msm-cpudai-tdm-group-port-id = <36913 36915 36917 36919>;
3687                 qcom,msm-cpudai-tdm-clk-rate = <12288000>;
3688                 qcom,msm-cpudai-tdm-clk-internal = <0>;
3689                 qcom,msm-cpudai-tdm-sync-mode = <1>;
3690                 qcom,msm-cpudai-tdm-sync-src = <0>;
3691                 qcom,msm-cpudai-tdm-data-out = <0>;
3692                 qcom,msm-cpudai-tdm-invert-sync = <0>;
3693                 qcom,msm-cpudai-tdm-data-delay = <0>;
3694                 dai_quat_tdm_tx_0: qcom,msm-dai-q6-tdm-quat-tx-0 {
3695                         compatible = "qcom,msm-dai-q6-tdm";
3696                         qcom,msm-cpudai-tdm-dev-id = <36913>;
3697                         qcom,msm-cpudai-tdm-data-align = <0>;
3698                 };
3699
3700                 dai_quat_tdm_tx_1: qcom,msm-dai-q6-tdm-quat-tx-1 {
3701                         compatible = "qcom,msm-dai-q6-tdm";
3702                         qcom,msm-cpudai-tdm-dev-id = <36915>;
3703                         qcom,msm-cpudai-tdm-data-align = <0>;
3704                 };
3705
3706                 dai_quat_tdm_tx_2: qcom,msm-dai-q6-tdm-quat-tx-2 {
3707                         compatible = "qcom,msm-dai-q6-tdm";
3708                         qcom,msm-cpudai-tdm-dev-id = <36917>;
3709                         qcom,msm-cpudai-tdm-data-align = <0>;
3710                 };
3711
3712                 dai_quat_tdm_tx_3: qcom,msm-dai-q6-tdm-quat-tx-3 {
3713                         compatible = "qcom,msm-dai-q6-tdm";
3714                         qcom,msm-cpudai-tdm-dev-id = <36919>;
3715                         qcom,msm-cpudai-tdm-data-align = <0>;
3716                 };
3717         };
3718
3719         hostless: qcom,msm-pcm-hostless {
3720                 compatible = "qcom,msm-pcm-hostless";
3721         };
3722
3723         ssc_sensors: qcom,msm-ssc-sensors {
3724                 compatible = "qcom,msm-ssc-sensors";
3725                 status = "ok";
3726                 qcom,firmware-name = "slpi";
3727         };
3728
3729         qcom,msm-pacman {
3730                 compatible = "qcom,msm-pacman";
3731         };
3732
3733         qcom,msm-adsprpc-mem {
3734                 compatible = "qcom,msm-adsprpc-mem-region";
3735                 memory-region = <&adsp_mem>;
3736         };
3737
3738         qcom,msm_fastrpc {
3739                 compatible = "qcom,msm-fastrpc-adsp";
3740
3741                 qcom,msm_fastrpc_compute_cb1 {
3742                         compatible = "qcom,msm-fastrpc-compute-cb";
3743                         label = "adsprpc-smd";
3744                         iommus = <&lpass_q6_smmu 8>;
3745                 };
3746                 qcom,msm_fastrpc_compute_cb2 {
3747                         compatible = "qcom,msm-fastrpc-compute-cb";
3748                         label = "adsprpc-smd";
3749                         iommus = <&lpass_q6_smmu 9>;
3750                 };
3751                 qcom,msm_fastrpc_compute_cb3 {
3752                         compatible = "qcom,msm-fastrpc-compute-cb";
3753                         label = "adsprpc-smd";
3754                         iommus = <&lpass_q6_smmu 10>;
3755                 };
3756                 qcom,msm_fastrpc_compute_cb4 {
3757                         compatible = "qcom,msm-fastrpc-compute-cb";
3758                         label = "adsprpc-smd";
3759                         iommus = <&lpass_q6_smmu 11>;
3760                 };
3761                 qcom,msm_fastrpc_compute_cb5 {
3762                         compatible = "qcom,msm-fastrpc-compute-cb";
3763                         label = "adsprpc-smd";
3764                         iommus = <&lpass_q6_smmu 12>;
3765                 };
3766                 qcom,msm_fastrpc_compute_cb6 {
3767                         compatible = "qcom,msm-fastrpc-compute-cb";
3768                         label = "adsprpc-smd";
3769                         iommus = <&lpass_q6_smmu 5>;
3770                 };
3771                 qcom,msm_fastrpc_compute_cb7 {
3772                         compatible = "qcom,msm-fastrpc-compute-cb";
3773                         label = "adsprpc-smd";
3774                         iommus = <&lpass_q6_smmu 6>;
3775                 };
3776                 qcom,msm_fastrpc_compute_cb8 {
3777                         compatible = "qcom,msm-fastrpc-compute-cb";
3778                         label = "adsprpc-smd";
3779                         iommus = <&lpass_q6_smmu 7>;
3780                 };
3781         };
3782
3783         cpu_pmu: cpu-pmu {
3784                 compatible = "arm,armv8-pmuv3";
3785                 qcom,irq-is-percpu;
3786                 interrupts = <1 7 4>;
3787         };
3788
3789         qcom,glink-smem-native-xprt-modem@86000000 {
3790                 compatible = "qcom,glink-smem-native-xprt";
3791                 reg = <0x86000000 0x200000>,
3792                         <0x9820010 0x4>;
3793                 reg-names = "smem", "irq-reg-base";
3794                 qcom,irq-mask = <0x8000>;
3795                 interrupts = <0 452 1>;
3796                 label = "mpss";
3797         };
3798
3799         qcom,glink-smem-native-xprt-adsp@86000000 {
3800                 compatible = "qcom,glink-smem-native-xprt";
3801                 reg = <0x86000000 0x200000>,
3802                         <0x9820010 0x4>;
3803                 reg-names = "smem", "irq-reg-base";
3804                 qcom,irq-mask = <0x200>;
3805                 interrupts = <0 157 1>;
3806                 label = "lpass";
3807                 qcom,qos-config = <&glink_qos_adsp>;
3808                 qcom,ramp-time = <0xaf>;
3809         };
3810
3811         glink_qos_adsp: qcom,glink-qos-config-adsp {
3812                 compatible = "qcom,glink-qos-config";
3813                 qcom,flow-info = <0x3c 0x0>,
3814                                 <0x3c 0x0>,
3815                                 <0x3c 0x0>,
3816                                 <0x3c 0x0>;
3817                 qcom,mtu-size = <0x800>;
3818                 qcom,tput-stats-cycle = <0xa>;
3819         };
3820
3821         qcom,glink-smem-native-xprt-dsps@86000000 {
3822                 compatible = "qcom,glink-smem-native-xprt";
3823                 reg = <0x86000000 0x200000>,
3824                         <0x9820010 0x4>;
3825                 reg-names = "smem", "irq-reg-base";
3826                 qcom,irq-mask = <0x8000000>;
3827                 interrupts = <0 179 1>;
3828                 label = "dsps";
3829         };
3830
3831         qcom,glink-smem-native-xprt-rpm@68000 {
3832                 compatible = "qcom,glink-rpm-native-xprt";
3833                 reg = <0x68000 0x6000>,
3834                         <0x9820010 0x4>;
3835                 reg-names = "msgram", "irq-reg-base";
3836                 qcom,irq-mask = <0x1>;
3837                 interrupts = <0 168 1>;
3838                 label = "rpm";
3839         };
3840
3841         glink_mpss: qcom,glink-ssr-modem {
3842                 compatible = "qcom,glink_ssr";
3843                 label = "modem";
3844                 qcom,edge = "mpss";
3845                 qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>;
3846                 qcom,xprt = "smem";
3847         };
3848
3849         glink_lpass: qcom,glink-ssr-adsp {
3850                 compatible = "qcom,glink_ssr";
3851                 label = "adsp";
3852                 qcom,edge = "lpass";
3853                 qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>;
3854                 qcom,xprt = "smem";
3855         };
3856
3857         glink_dsps: qcom,glink-ssr-dsps {
3858                 compatible = "qcom,glink_ssr";
3859                 label = "slpi";
3860                 qcom,edge = "dsps";
3861                 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>;
3862                 qcom,xprt = "smem";
3863         };
3864
3865         glink_rpm: qcom,glink-ssr-rpm {
3866                 compatible = "qcom,glink_ssr";
3867                 label = "rpm";
3868                 qcom,edge = "rpm";
3869                 qcom,notify-edges = <&glink_lpass>, <&glink_mpss>, <&glink_dsps>;
3870                 qcom,xprt = "smem";
3871         };
3872
3873          qcom,glink_pkt {
3874                  compatible = "qcom,glinkpkt";
3875
3876                  qcom,glinkpkt-at-mdm0 {
3877                          qcom,glinkpkt-transport = "smd_trans";
3878                          qcom,glinkpkt-edge = "mpss";
3879                          qcom,glinkpkt-ch-name = "DS";
3880                          qcom,glinkpkt-dev-name = "at_mdm0";
3881                  };
3882
3883                  qcom,glinkpkt-loopback_cntl {
3884                          qcom,glinkpkt-transport = "lloop";
3885                          qcom,glinkpkt-edge = "local";
3886                          qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
3887                          qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
3888                  };
3889
3890                  qcom,glinkpkt-loopback_data {
3891                          qcom,glinkpkt-transport = "lloop";
3892                          qcom,glinkpkt-edge = "local";
3893                          qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
3894                          qcom,glinkpkt-dev-name = "glink_pkt_loopback";
3895                  };
3896          };
3897
3898         qcom,cache_erp64@6500000 {
3899                 compatible = "qcom,kryo_cache_erp64";
3900                 reg = <0x6500000 0x4000>;
3901                 /*
3902                  * PPI 0  for L0/L1
3903                  * SPI 1  for Cluster 1 L2 Info
3904                  * SPI 9  for Cluster 2 L2 Info
3905                  * SPI 2  for Cluster 1 L2 Error
3906                  * SPI 10 for Cluster 2 L2 Error
3907                  * SPI 17 for L3 error
3908                  */
3909                 interrupts = <1 0 0>, <0 1 0>, <0 9 0>, <0 2 0>, <0 10 0>,
3910                              <0 17 0>;
3911                 interrupt-names = "l1_irq", "l2_irq_info_0", "l2_irq_info_1",
3912                                   "l2_irq_err_0", "l2_irq_err_1", "l3_irq";
3913         };
3914
3915         qcom,m4m_erp64@9A40000 {
3916                 compatible = "qcom,m4m_erp";
3917                 reg = <0x9A40000 0x40000>;
3918                 interrupts = <0 22 0>;
3919                 interrupt-names = "m4m_irq";
3920         };
3921
3922         lmh: qcom,lmh {
3923                 compatible = "qcom,lmh_v1";
3924                 interrupts = <0 23 4>;
3925         };
3926
3927         timer@09840000 {
3928                 #address-cells = <1>;
3929                 #size-cells = <1>;
3930                 ranges;
3931                 compatible = "arm,armv7-timer-mem";
3932                 reg = <0x09840000 0x1000>;
3933                 clock-frequency = <19200000>;
3934
3935                 frame@09850000 {
3936                         frame-number = <0>;
3937                         interrupts = <0 31 0x4>,
3938                                      <0 30 0x4>;
3939                         reg = <0x09850000 0x1000>,
3940                               <0x09860000 0x1000>;
3941                 };
3942
3943                 frame@09870000 {
3944                         frame-number = <1>;
3945                         interrupts = <0 32 0x4>;
3946                         reg = <0x09870000 0x1000>;
3947                         status = "disabled";
3948                 };
3949
3950                 frame@09880000 {
3951                         frame-number = <2>;
3952                         interrupts = <0 33 0x4>;
3953                         reg = <0x09880000 0x1000>;
3954                         status = "disabled";
3955                 };
3956
3957                 frame@09890000 {
3958                         frame-number = <3>;
3959                         interrupts = <0 34 0x4>;
3960                         reg = <0x09890000 0x1000>;
3961                         status = "disabled";
3962                 };
3963
3964                 frame@098a0000 {
3965                         frame-number = <4>;
3966                         interrupts = <0 35 0x4>;
3967                         reg = <0x098a0000 0x1000>;
3968                         status = "disabled";
3969                 };
3970
3971                 frame@098b0000 {
3972                         frame-number = <5>;
3973                         interrupts = <0 36 0x4>;
3974                         reg = <0x098b0000 0x1000>;
3975                         status = "disabled";
3976                 };
3977
3978                 frame@098c0000 {
3979                         frame-number = <6>;
3980                         interrupts = <0 37 0x4>;
3981                         reg = <0x098c0000 0x1000>;
3982                         status = "disabled";
3983                 };
3984         };
3985
3986         qcom,avtimer@90f7000 {
3987                 compatible = "qcom,avtimer";
3988                 reg = <0x90f700c 0x4>,
3989                       <0x90f7010 0x4>;
3990                 reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
3991                 qcom,clk-div = <27>;
3992         };
3993
3994         mcd {
3995                 compatible = "qcom,mcd";
3996                 qcom,ce-hw-instance = <0>;
3997                 qcom,ce-device = <0>;
3998                 interrupts = <0 248 0>;
3999                 interrupt-names = "mcd_irq";
4000                 clock-names = "core_clk_src", "core_clk",
4001                         "iface_clk", "bus_clk";
4002                 clocks = <&clock_gcc clk_ce1_clk>,
4003                         <&clock_gcc clk_qseecom_ce1_clk>,
4004                         <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
4005                         <&clock_gcc clk_gcc_ce1_axi_m_clk>;
4006                         qcom,ce-opp-freq = <171430000>;
4007         };
4008
4009         dcc: dcc@4b3000 {
4010                 compatible = "qcom,dcc";
4011                 reg = <0x4b3000 0x1000>,
4012                       <0x4b4000 0x2000>,
4013                       <0x4b0000 0x4>;
4014                 reg-names = "dcc-base", "dcc-ram-base", "dcc-xpu-base";
4015
4016                 clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>;
4017                 clock-names = "dcc_clk";
4018
4019                 qcom,save-reg;
4020         };
4021 };
4022
4023 &gdsc_venus {
4024         clock-names = "bus_clk", "maxi_clk", "core_clk";
4025         clocks = <&clock_mmss clk_video_axi_clk>,
4026                  <&clock_mmss clk_video_maxi_clk>,
4027                  <&clock_mmss clk_video_core_clk>;
4028         parent-supply = <&gdsc_mmagic_video>;
4029         status = "ok";
4030 };
4031
4032 &gdsc_venus_core0 {
4033         clock-names = "core0_clk";
4034         clocks = <&clock_mmss clk_video_subcore0_clk>;
4035         status = "ok";
4036 };
4037
4038 &gdsc_venus_core1 {
4039         clock-names = "core1_clk";
4040         clocks = <&clock_mmss clk_video_subcore1_clk>;
4041         status = "ok";
4042 };
4043
4044 &gdsc_camss_top {
4045         clock-names = "bus_clk", "vfe_axi";
4046         clocks = <&clock_mmss clk_camss_cpp_axi_clk>,
4047                  <&clock_mmss clk_camss_vfe_axi_clk>;
4048         parent-supply = <&gdsc_mmagic_camss>;
4049         status = "ok";
4050 };
4051
4052 &gdsc_vfe0 {
4053         clock-names = "core0_clk";
4054         clocks = <&clock_mmss clk_camss_vfe0_clk>;
4055         parent-supply = <&gdsc_camss_top>;
4056         status = "ok";
4057 };
4058
4059 &gdsc_vfe1 {
4060         clock-names = "core1_clk";
4061         clocks = <&clock_mmss clk_camss_vfe1_clk>;
4062         parent-supply = <&gdsc_camss_top>;
4063         status = "ok";
4064 };
4065
4066 &gdsc_jpeg {
4067         clock-names = "bus_clk", "dma_clk", "core0_clk", "core2_clk";
4068         clocks = <&clock_mmss clk_camss_jpeg_axi_clk>,
4069                  <&clock_mmss clk_camss_jpeg_dma_clk>,
4070                  <&clock_mmss clk_camss_jpeg0_clk>,
4071                  <&clock_mmss clk_camss_jpeg2_clk>;
4072         parent-supply = <&gdsc_camss_top>;
4073         status = "ok";
4074 };
4075
4076 &gdsc_cpp {
4077         clock-names = "core_clk";
4078         clocks = <&clock_mmss clk_camss_cpp_clk>;
4079         parent-supply = <&gdsc_camss_top>;
4080         qcom,support-hw-trigger;
4081         status = "ok";
4082 };
4083
4084 &gdsc_fd {
4085         clock-names = "core_clk", "core_uar_clk";
4086         clocks = <&clock_mmss clk_fd_core_clk>,
4087                  <&clock_mmss clk_fd_core_uar_clk>;
4088         parent-supply = <&gdsc_camss_top>;
4089         status = "ok";
4090 };
4091
4092 &gdsc_mdss {
4093         clock-names = "bus_clk";
4094         clocks = <&clock_mmss clk_mdss_axi_clk>;
4095         parent-supply = <&gdsc_mmagic_mdss>;
4096         proxy-supply = <&gdsc_mdss>;
4097         qcom,proxy-consumer-enable;
4098         status = "ok";
4099 };
4100
4101 &gdsc_pcie_0 {
4102         status = "ok";
4103 };
4104
4105 &gdsc_pcie_1 {
4106         status = "ok";
4107 };
4108
4109 &gdsc_pcie_2 {
4110         status = "ok";
4111 };
4112
4113 &gdsc_usb30 {
4114         reg = <0x30f004 0x4>;
4115         status = "ok";
4116 };
4117
4118 &gdsc_ufs {
4119         status = "ok";
4120 };
4121
4122 &gdsc_gpu {
4123         status = "ok";
4124 };
4125
4126 &gdsc_gpu_gx {
4127         clock-names = "core_clk", "core_root_clk";
4128         clocks = <&clock_gpu clk_gpu_gx_gfx3d_clk>,
4129                  <&clock_gpu clk_gfx3d_clk_src>;
4130         qcom,force-enable-root-clk;
4131         parent-supply = <&gfx_vreg>;
4132         status = "ok";
4133 };
4134
4135 &gdsc_hlos1_vote_aggre0_noc {
4136         status = "ok";
4137 };
4138
4139 &gdsc_hlos1_vote_lpass_adsp {
4140         status = "ok";
4141 };
4142
4143 &gdsc_hlos1_vote_lpass_core {
4144         status = "ok";
4145 };
4146
4147 &gdsc_aggre0_noc {
4148         status = "ok";
4149 };
4150
4151 &gdsc_mmagic_bimc {
4152         status = "ok";
4153 };
4154
4155 &gdsc_mmagic_video {
4156         clock-names = "core_root_clk";
4157         /* RPM enables the mmagic bimc GDSC when this clk node is voted for. */
4158         clocks = <&clock_gcc clk_mmssnoc_gds_clk>;
4159         qcom,enable-root-clk;
4160         status = "ok";
4161 };
4162
4163 &gdsc_mmagic_mdss {
4164         clock-names = "core_root_clk";
4165         /* RPM enables the mmagic bimc GDSC when this clk node is voted for. */
4166         clocks = <&clock_gcc clk_mmssnoc_gds_clk>;
4167         qcom,enable-root-clk;
4168         status = "ok";
4169 };
4170
4171 &gdsc_mmagic_camss {
4172         clock-names = "core_root_clk";
4173         /* RPM enables the mmagic bimc GDSC when this clk node is voted for. */
4174         clocks = <&clock_gcc clk_mmssnoc_gds_clk>;
4175         qcom,enable-root-clk;
4176         status = "ok";
4177 };
4178
4179 #include "msm-pm8994-rpm-regulator.dtsi"
4180 #include "msm-pm8994.dtsi"
4181 #include "msm-pmi8994.dtsi"
4182 #include "msm8996-regulator.dtsi"
4183 #include "msm8996-camera.dtsi"
4184 #include "msm8996-gpu.dtsi"
4185 #include "msm8996-pm.dtsi"
4186 #include "msm-arm-smmu-8996.dtsi"
4187 #include "msm8996-vidc.dtsi"
4188 #include "msm8996-bus.dtsi"