arch/arm/boot/dts/qcom/msm8998.dtsi

   1 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include "skeleton64.dtsi"
  14 #include <dt-bindings/clock/msm-clocks-8998.h>
  15 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM 8998";
  20         compatible = "qcom,msm8998";
  21         qcom,msm-id = <292 0x0>;
  22         interrupt-parent = <&intc>;
  23
  24         aliases {
  25                 serial0 = &uartblsp2dm1;
  26                 pci-domain0 = &pcie0;
  27                 sdhc2 = &sdhc_2; /* SDC2 SD card slot */
  28         };
  29
  30         psci {
  31                 compatible = "arm,psci-1.0";
  32                 method = "smc";
  33         };
  34
  35         chosen {
  36                 stdout-path = "serial0";
  37                 bootargs = "rcupdate.rcu_expedited=1";
  38         };
  39
  40         cpus {
  41                 #address-cells = <2>;
  42                 #size-cells = <0>;
  43
  44                 CPU0: cpu@0 {
  45                         device_type = "cpu";
  46                         compatible = "arm,armv8";
  47                         reg = <0x0 0x0>;
  48                         qcom,limits-info = <&mitigation_profile0>;
  49                         qcom,lmh-dcvs = <&lmh_dcvs0>;
  50                         enable-method = "psci";
  51                         efficiency = <1024>;
  52                         next-level-cache = <&L2_0>;
  53                         qcom,ea = <&ea0>;
  54                         sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  55                         L2_0: l2-cache {
  56                               compatible = "arm,arch-cache";
  57                               cache-level = <2>;
  58                                   qcom,dump-size = <0x0>;      /* A53 L2 dump not supported */
  59                         };
  60                         L1_I_0: l1-icache {
  61                                 compatible = "arm,arch-cache";
  62                                 qcom,dump-size = <0x9040>;
  63                         };
  64                         L1_D_0: l1-dcache {
  65                                 compatible = "arm,arch-cache";
  66                                 qcom,dump-size = <0x9040>;
  67                         };
  68                         L1_TLB_0: l1-tlb {
  69                                 qcom,dump-size = <0x2000>;
  70                         };
  71                 };
  72
  73                 CPU1: cpu@1 {
  74                         device_type = "cpu";
  75                         compatible = "arm,armv8";
  76                         reg = <0x0 0x1>;
  77                         qcom,limits-info = <&mitigation_profile1>;
  78                         qcom,lmh-dcvs = <&lmh_dcvs0>;
  79                         enable-method = "psci";
  80                         efficiency = <1024>;
  81                         next-level-cache = <&L2_0>;
  82                         qcom,ea = <&ea1>;
  83                         sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
  84                         L1_I_1: l1-icache {
  85                                 compatible = "arm,arch-cache";
  86                                 qcom,dump-size = <0x9040>;
  87                         };
  88                         L1_D_1: l1-dcache {
  89                                 compatible = "arm,arch-cache";
  90                                 qcom,dump-size = <0x9040>;
  91                         };
  92                         L1_TLB_1: l1-tlb {
  93                                 qcom,dump-size = <0x2000>;
  94                         };
  95                 };
  96
  97                 CPU2: cpu@2 {
  98                         device_type = "cpu";
  99                         compatible = "arm,armv8";
 100                         reg = <0x0 0x2>;
 101                         qcom,limits-info = <&mitigation_profile2>;
 102                         qcom,lmh-dcvs = <&lmh_dcvs0>;
 103                         enable-method = "psci";
 104                         efficiency = <1024>;
 105                         next-level-cache = <&L2_0>;
 106                         qcom,ea = <&ea2>;
 107                         sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
 108                         L1_I_2: l1-icache {
 109                                 compatible = "arm,arch-cache";
 110                                 qcom,dump-size = <0x9040>;
 111                         };
 112                         L1_D_2: l1-dcache {
 113                                 compatible = "arm,arch-cache";
 114                                 qcom,dump-size = <0x9040>;
 115                         };
 116                         L1_TLB_2: l1-tlb {
 117                                 qcom,dump-size = <0x2000>;
 118                         };
 119                 };
 120
 121                 CPU3: cpu@3 {
 122                         device_type = "cpu";
 123                         compatible = "arm,armv8";
 124                         reg = <0x0 0x3>;
 125                         qcom,limits-info = <&mitigation_profile3>;
 126                         qcom,lmh-dcvs = <&lmh_dcvs0>;
 127                         enable-method = "psci";
 128                         efficiency = <1024>;
 129                         next-level-cache = <&L2_0>;
 130                         qcom,ea = <&ea3>;
 131                         sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
 132                         L1_I_3: l1-icache {
 133                                 compatible = "arm,arch-cache";
 134                                 qcom,dump-size = <0x9040>;
 135                         };
 136                         L1_D_3: l1-dcache {
 137                                 compatible = "arm,arch-cache";
 138                                 qcom,dump-size = <0x9040>;
 139                         };
 140                         L1_TLB_3: l1-tlb {
 141                                 qcom,dump-size = <0x2000>;
 142                         };
 143                 };
 144
 145                 CPU4: cpu@100 {
 146                         device_type = "cpu";
 147                         compatible = "arm,armv8";
 148                         reg = <0x0 0x100>;
 149                         qcom,limits-info = <&mitigation_profile4>;
 150                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 151                         enable-method = "psci";
 152                         efficiency = <1536>;
 153                         next-level-cache = <&L2_1>;
 154                         qcom,ea = <&ea4>;
 155                         sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
 156                         L2_1: l2-cache {
 157                                 compatible = "arm,arch-cache";
 158                                 cache-level = <2>;
 159                         };
 160                         L1_I_100: l1-icache {
 161                                 compatible = "arm,arch-cache";
 162                                 qcom,dump-size = <0x12000>;
 163                         };
 164                         L1_D_100: l1-dcache {
 165                                 compatible = "arm,arch-cache";
 166                                 qcom,dump-size = <0x12000>;
 167                         };
 168                         L1_TLB_100: l1-tlb {
 169                                 qcom,dump-size = <0x4800>;
 170                         };
 171                 };
 172
 173                 CPU5: cpu@101 {
 174                         device_type = "cpu";
 175                         compatible = "arm,armv8";
 176                         reg = <0x0 0x101>;
 177                         qcom,limits-info = <&mitigation_profile5>;
 178                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 179                         enable-method = "psci";
 180                         efficiency = <1536>;
 181                         next-level-cache = <&L2_1>;
 182                         qcom,ea = <&ea5>;
 183                         sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
 184                         L1_I_101: l1-icache {
 185                                 compatible = "arm,arch-cache";
 186                                 qcom,dump-size = <0x12000>;
 187                         };
 188                         L1_D_101: l1-dcache {
 189                                 compatible = "arm,arch-cache";
 190                                 qcom,dump-size = <0x12000>;
 191                         };
 192                         L1_TLB_101: l1-tlb {
 193                                 qcom,dump-size = <0x4800>;
 194                         };
 195                 };
 196
 197                 CPU6: cpu@102 {
 198                         device_type = "cpu";
 199                         compatible = "arm,armv8";
 200                         reg = <0x0 0x102>;
 201                         qcom,limits-info = <&mitigation_profile6>;
 202                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 203                         enable-method = "psci";
 204                         efficiency = <1536>;
 205                         next-level-cache = <&L2_1>;
 206                         qcom,ea = <&ea6>;
 207                         sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
 208                         L1_I_102: l1-icache {
 209                                 compatible = "arm,arch-cache";
 210                                 qcom,dump-size = <0x12000>;
 211                         };
 212                         L1_D_102: l1-dcache {
 213                                 compatible = "arm,arch-cache";
 214                                 qcom,dump-size = <0x12000>;
 215                         };
 216                         L1_TLB_102: l1-tlb {
 217                                 qcom,dump-size = <0x4800>;
 218                         };
 219                 };
 220
 221                 CPU7: cpu@103 {
 222                         device_type = "cpu";
 223                         compatible = "arm,armv8";
 224                         reg = <0x0 0x103>;
 225                         qcom,limits-info = <&mitigation_profile7>;
 226                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 227                         enable-method = "psci";
 228                         efficiency = <1536>;
 229                         next-level-cache = <&L2_1>;
 230                         qcom,ea = <&ea7>;
 231                         sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
 232                         L1_I_103: l1-icache {
 233                                 compatible = "arm,arch-cache";
 234                                 qcom,dump-size = <0x12000>;
 235                         };
 236                         L1_D_103: l1-dcache {
 237                                 compatible = "arm,arch-cache";
 238                                 qcom,dump-size = <0x12000>;
 239                         };
 240                         L1_TLB_103: l1-tlb {
 241                                 qcom,dump-size = <0x4800>;
 242                         };
 243                 };
 244
 245                 cpu-map {
 246                         cluster0 {
 247                                 core0 {
 248                                         cpu = <&CPU0>;
 249                                 };
 250
 251                                 core1 {
 252                                         cpu = <&CPU1>;
 253                                 };
 254
 255                                 core2 {
 256                                         cpu = <&CPU2>;
 257                                 };
 258
 259                                 core3 {
 260                                         cpu = <&CPU3>;
 261                                 };
 262                         };
 263
 264                         cluster1 {
 265                                 core0 {
 266                                         cpu = <&CPU4>;
 267                                 };
 268
 269                                 core1 {
 270                                         cpu = <&CPU5>;
 271                                 };
 272
 273                                 core2 {
 274                                         cpu = <&CPU6>;
 275                                 };
 276
 277                                 core3 {
 278                                         cpu = <&CPU7>;
 279                                 };
 280                         };
 281                 };
 282                 energy-costs {
 283                         CPU_COST_0: core-cost0 {
 284                                 busy-cost-data = <
 285                                         134 154
 286                                         154 156
 287                                         174 159
 288                                         194 161
 289                                         214 164
 290                                         229 166
 291                                         249 172
 292                                         269 175
 293                                         284 179
 294                                         304 185
 295                                         324 189
 296                                         344 196
 297                                         363 199
 298                                         383 205
 299                                         403 212
 300                                         433 228
 301                                         453 241
 302                                         473 255
 303                                         493 272
 304                                 >;
 305                                 idle-cost-data = <
 306                                         4 4 0 0
 307                                 >;
 308                         };
 309                         CPU_COST_1: core-cost1 {
 310                                 busy-cost-data = <
 311                                         182  171
 312                                         215  179
 313                                         248  186
 314                                         282  192
 315                                         315  200
 316                                         348  209
 317                                         390  219
 318                                         423  225
 319                                         456  236
 320                                         489  242
 321                                         514  260
 322                                         547  271
 323                                         580  287
 324                                         614  306
 325                                         647  333
 326                                         680  356
 327                                         713  386
 328                                         747  401
 329                                         780  452
 330                                         813  553
 331                                         847  575
 332                                         880  717
 333                                         913  814
 334                                         954  994
 335                                         979  1168
 336                                         1003 1428
 337                                         1011 1558
 338                                         1023 1677
 339                                         1024 1707
 340                                 >;
 341                                 idle-cost-data = <
 342                                         10 10 0 0
 343                                 >;
 344                         };
 345                         CLUSTER_COST_0: cluster-cost0 {
 346                                 busy-cost-data = <
 347                                         113 20
 348                                         130 21
 349                                         147 22
 350                                         164 23
 351                                         181 24
 352                                         194 27
 353                                         211 29
 354                                         228 30
 355                                         243 32
 356                                         258 33
 357                                         275 35
 358                                         292 38
 359                                         308 39
 360                                         326 42
 361                                         342 46
 362                                         368 48
 363                                         384 53
 364                                         401 59
 365                                         419 66
 366                                 >;
 367                                 idle-cost-data = <
 368                                         31 31 31 0
 369                                 >;
 370                         };
 371                         CLUSTER_COST_1: cluster-cost1 {
 372                                 busy-cost-data = <
 373                                         182  26
 374                                         216  29
 375                                         247  30
 376                                         278  33
 377                                         312  35
 378                                         344  37
 379                                         391  38
 380                                         419  40
 381                                         453  43
 382                                         487  44
 383                                         509  46
 384                                         546  50
 385                                         581  54
 386                                         615  60
 387                                         650  63
 388                                         676  70
 389                                         712  74
 390                                         739  80
 391                                         776  87
 392                                         803  96
 393                                         834  104
 394                                         881  120
 395                                         914  130
 396                                         957  171
 397                                         975  178
 398                                         996  185
 399                                         1016 200
 400                                         1021 202
 401                                         1024 203
 402                                 >;
 403                                 idle-cost-data = <
 404                                         50 50 50 0
 405                                 >;
 406                         };
 407                 };
 408         };
 409
 410         soc: soc { };
 411
 412         vendor: vendor {
 413                 #address-cells = <1>;
 414                 #size-cells = <1>;
 415                 ranges = <0 0 0 0xffffffff>;
 416                 compatible = "simple-bus";
 417         };
 418
 419         firmware: firmware {
 420                 android {
 421                         compatible = "android,firmware";
 422                         fstab {
 423                                 compatible = "android,fstab";
 424                                 vendor {
 425                                         compatible = "android,vendor";
 426                                         dev = "/dev/block/platform/soc/1da4000.ufshc/by-name/vendor";
 427                                         type = "ext4";
 428                                         mnt_flags = "ro,barrier=1,discard";
 429                                         fsmgr_flags = "wait,slotselect,verify";
 430                                         status = "ok";
 431                                 };
 432                         };
 433                 };
 434         };
 435
 436         reserved-memory {
 437                 #address-cells = <2>;
 438                 #size-cells = <2>;
 439                 ranges;
 440
 441                 removed_regions: removed_regions@85800000 {
 442                         compatible = "removed-dma-pool";
 443                         no-map;
 444                         reg = <0 0x85800000 0 0x3700000>;
 445                 };
 446
 447                 pil_ipa_gpu_mem: pil_ipa_gpu_region@95200000 {
 448                         compatible = "removed-dma-pool";
 449                         no-map;
 450                         reg = <0 0x95200000 0 0x100000>;
 451                 };
 452
 453                 pil_slpi_mem: pil_slpi_region@94300000 {
 454                         compatible = "removed-dma-pool";
 455                         no-map;
 456                         reg = <0 0x94300000 0 0xf00000>;
 457                 };
 458
 459                 pil_mba_mem: pil_mba_region@94100000 {
 460                         compatible = "removed-dma-pool";
 461                         no-map;
 462                         reg = <0 0x94100000 0 0x200000>;
 463                 };
 464
 465                 pil_video_mem: pil_video_region@93c00000 {
 466                         compatible = "removed-dma-pool";
 467                         no-map;
 468                         reg = <0 0x93c00000 0 0x500000>;
 469                 };
 470
 471                 modem_mem: modem_region@8cc00000 {
 472                         compatible = "removed-dma-pool";
 473                         no-map;
 474                         reg = <0 0x8cc00000 0 0x7000000>;
 475                 };
 476
 477                 pil_adsp_mem: pil_adsp_region@0x8b200000 {
 478                         compatible = "removed-dma-pool";
 479                         no-map;
 480                         reg = <0 0x8b200000 0 0x1a00000>;
 481                 };
 482
 483                 spss_mem: spss_region@8ab00000 { /* for SPSS-PIL */
 484                         compatible = "removed-dma-pool";
 485                         no-map;
 486                         reg = <0 0x8ab00000 0 0x700000>;
 487                 };
 488
 489                 adsp_mem: adsp_region {
 490                         compatible = "shared-dma-pool";
 491                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 492                         reusable;
 493                         alignment = <0 0x400000>;
 494                         size = <0 0x800000>;
 495                 };
 496
 497                 qseecom_mem: qseecom_region {
 498                         compatible = "shared-dma-pool";
 499                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 500                         reusable;
 501                         alignment = <0 0x400000>;
 502                         size = <0 0x1400000>;
 503                 };
 504
 505                 sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
 506                         compatible = "shared-dma-pool";
 507                         alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
 508                         reusable;
 509                         alignment = <0 0x100000>;
 510                         size = <0 0x800000>;
 511                 };
 512
 513                 secure_display_memory: secure_region {
 514                         compatible = "shared-dma-pool";
 515                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 516                         reusable;
 517                         alignment = <0 0x200000>;
 518                         size = <0 0x5c00000>;
 519                 };
 520
 521                 /* global autoconfigured region for contiguous allocations */
 522                 linux,cma {
 523                         compatible = "shared-dma-pool";
 524                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 525                         reusable;
 526                         alignment = <0 0x400000>;
 527                         size = <0 0x2000000>;
 528                         linux,cma-default;
 529                 };
 530
 531                 cont_splash_mem: splash_region@9d600000 {
 532                         reg = <0x0 0x9d600000 0x0 0x02400000>;
 533                         label = "cont_splash_mem";
 534                 };
 535         };
 536 };
 537
 538 #include "msm8998-smp2p.dtsi"
 539 #include "msm-gdsc-8998.dtsi"
 540
 541 &soc {
 542         #address-cells = <1>;
 543         #size-cells = <1>;
 544         ranges = <0 0 0 0xffffffff>;
 545         compatible = "simple-bus";
 546
 547         intc: interrupt-controller@17a00000 {
 548                 compatible = "arm,gic-v3";
 549                 reg = <0x17a00000 0x10000>,       /* GICD */
 550                       <0x17b00000 0x100000>;      /* GICR * 8 */
 551                 #interrupt-cells = <3>;
 552                 #address-cells = <1>;
 553                 #size-cells = <1>;
 554                 ranges;
 555                 interrupt-controller;
 556                 #redistributor-regions = <1>;
 557                 redistributor-stride = <0x0 0x20000>;
 558                 interrupts = <1 9 4>;
 559
 560                 gic-its@0x17a20000{
 561                         compatible = "arm,gic-v3-its";
 562                         msi-contoller;
 563                         reg = <0x17a20000 0x20000>;
 564                 };
 565         };
 566
 567         timer {
 568                 compatible = "arm,armv8-timer";
 569                 interrupts = <1 1 0xf08>,
 570                              <1 2 0xf08>,
 571                              <1 3 0xf08>,
 572                              <1 0 0xf08>;
 573                 clock-frequency = <19200000>;
 574         };
 575
 576         restart@10ac000 {
 577                 compatible = "qcom,pshold";
 578                 reg = <0x10ac000 0x4>,
 579                       <0x1fd3000 0x4>;
 580                 reg-names = "pshold-base", "tcsr-boot-misc-detect";
 581         };
 582
 583         spmi_bus: qcom,spmi@800f000 {
 584                 compatible = "qcom,spmi-pmic-arb";
 585                 reg =   <0x800f000 0x1000>,
 586                         <0x8400000 0x1000000>,
 587                         <0x9400000 0x1000000>,
 588                         <0xa400000 0x220000>,
 589                         <0x800a000 0x3000>;
 590                 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 591                 interrupt-names = "periph_irq";
 592                 interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
 593                 qcom,ee = <0>;
 594                 qcom,channel = <0>;
 595                 qcom,reserved-chan = <511>;
 596                 #address-cells = <2>;
 597                 #size-cells = <0>;
 598                 interrupt-controller;
 599                 #interrupt-cells = <4>;
 600                 cell-index = <0>;
 601         };
 602
 603         qcom,sps {
 604                 compatible = "qcom,msm_sps_4k";
 605                 qcom,device-type = <3>;
 606                 qcom,pipe-attr-ee;
 607         };
 608
 609         uartblsp1dm1: serial@0c170000 {
 610                 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 611                 reg = <0xc170000 0x1000>;
 612                 interrupts = <0 108 0>;
 613                 status = "disabled";
 614                 clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
 615                          <&clock_gcc clk_gcc_blsp1_ahb_clk>;
 616                 clock-names = "core", "iface";
 617         };
 618
 619         uartblsp2dm1: serial@0c1b0000 {
 620                 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 621                 reg = <0xc1b0000 0x1000>;
 622                 interrupts = <0 114 0>;
 623                 status = "disabled";
 624                 clocks = <&clock_gcc clk_gcc_blsp2_uart2_apps_clk>,
 625                          <&clock_gcc clk_gcc_blsp2_ahb_clk>;
 626                 clock-names = "core", "iface";
 627         };
 628
 629         slim_aud: slim@171c0000 {
 630                 cell-index = <1>;
 631                 compatible = "qcom,slim-ngd";
 632                 reg = <0x171c0000 0x2C000>,
 633                         <0x17184000 0x32000>;
 634                 reg-names = "slimbus_physical", "slimbus_bam_physical";
 635                 interrupts = <0 163 0>, <0 164 0>;
 636                 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
 637                 qcom,apps-ch-pipes = <0x00001f80>;
 638                 qcom,ea-pc = <0x210>;
 639         };
 640
 641         slim_qca: slim@17240000 {
 642                 status = "ok";
 643                 cell-index = <3>;
 644                 compatible = "qcom,slim-ngd";
 645                 reg = <0x17240000 0x2C000>,
 646                         <0x17204000 0x26000>;
 647                 reg-names = "slimbus_physical", "slimbus_bam_physical";
 648                 interrupts = <0 291 0>, <0 292 0>;
 649                 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
 650
 651                 /* Slimbus Slave DT for WCN3990 */
 652                 btfmslim_codec: wcn3990 {
 653                         compatible = "qcom,btfmslim_slave";
 654                         elemental-addr = [00 01 20 02 17 02];
 655                         qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
 656                         qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
 657                 };
 658         };
 659
 660         timer@17920000 {
 661                 #address-cells = <1>;
 662                 #size-cells = <1>;
 663                 ranges;
 664                 compatible = "arm,armv7-timer-mem";
 665                 reg = <0x17920000 0x1000>;
 666                 clock-frequency = <19200000>;
 667
 668                 frame@17921000 {
 669                         frame-number = <0>;
 670                         interrupts = <0 8 0x4>,
 671                                      <0 7 0x4>;
 672                         reg = <0x17921000 0x1000>,
 673                               <0x17922000 0x1000>;
 674                 };
 675
 676                 frame@17923000 {
 677                         frame-number = <1>;
 678                         interrupts = <0 9 0x4>;
 679                         reg = <0x17923000 0x1000>;
 680                         status = "disabled";
 681                 };
 682
 683                 frame@17924000 {
 684                         frame-number = <2>;
 685                         interrupts = <0 10 0x4>;
 686                         reg = <0x17924000 0x1000>;
 687                         status = "disabled";
 688                 };
 689
 690                 frame@17925000 {
 691                         frame-number = <3>;
 692                         interrupts = <0 11 0x4>;
 693                         reg = <0x17925000 0x1000>;
 694                         status = "disabled";
 695                 };
 696
 697                 frame@17926000 {
 698                         frame-number = <4>;
 699                         interrupts = <0 12 0x4>;
 700                         reg = <0x17926000 0x1000>;
 701                         status = "disabled";
 702                 };
 703
 704                 frame@17927000 {
 705                         frame-number = <5>;
 706                         interrupts = <0 13 0x4>;
 707                         reg = <0x17927000 0x1000>;
 708                         status = "disabled";
 709                 };
 710
 711                 frame@17928000 {
 712                         frame-number = <6>;
 713                         interrupts = <0 14 0x4>;
 714                         reg = <0x17928000 0x1000>;
 715                         status = "disabled";
 716                 };
 717         };
 718
 719         cpubw: qcom,cpubw {
 720                 compatible = "qcom,devbw";
 721                 governor = "performance";
 722                 qcom,src-dst-ports = <1 512>;
 723                 qcom,active-only;
 724                 qcom,bw-tbl =
 725                         <   762 /*  100 MHz */ >,
 726                         <  1144 /*  150 MHz */ >,
 727                         <  1525 /*  200 MHz */ >,
 728                         <  2288 /*  300 MHz */ >,
 729                         <  3143 /*  412 MHz */ >,
 730                         <  4173 /*  547 MHz */ >,
 731                         <  5195 /*  681 MHz */ >,
 732                         <  5859 /*  768 MHz */ >,
 733                         <  7759 /* 1017 MHz */ >,
 734                         <  9887 /* 1296 MHz */ >,
 735                         < 11863 /* 1555 MHz */ >,
 736                         < 13763 /* 1804 MHz */ >;
 737         };
 738
 739         bwmon: qcom,cpu-bwmon {
 740                 compatible = "qcom,bimc-bwmon3";
 741                 reg = <0x01008000 0x300>, <0x01001000 0x200>;
 742                 reg-names = "base", "global_base";
 743                 interrupts = <0 183 4>;
 744                 qcom,mport = <0>;
 745                 qcom,target-dev = <&cpubw>;
 746         };
 747
 748         mincpubw: qcom,mincpubw {
 749                 compatible = "qcom,devbw";
 750                 governor = "powersave";
 751                 qcom,src-dst-ports = <1 512>;
 752                 qcom,active-only;
 753                 qcom,bw-tbl =
 754                         <   762 /*  100 MHz */ >,
 755                         <  1144 /*  150 MHz */ >,
 756                         <  1525 /*  200 MHz */ >,
 757                         <  2288 /*  300 MHz */ >,
 758                         <  3143 /*  412 MHz */ >,
 759                         <  4173 /*  547 MHz */ >,
 760                         <  5195 /*  681 MHz */ >,
 761                         <  5859 /*  768 MHz */ >,
 762                         <  7759 /* 1017 MHz */ >,
 763                         <  9887 /* 1296 MHz */ >,
 764                         < 11863 /* 1555 MHz */ >,
 765                         < 13763 /* 1804 MHz */ >;
 766         };
 767
 768         memlat_cpu0: qcom,memlat-cpu0 {
 769                 compatible = "qcom,devbw";
 770                 governor = "powersave";
 771                 qcom,src-dst-ports = <1 512>;
 772                 qcom,active-only;
 773                 qcom,bw-tbl =
 774                         <   762 /*  100 MHz */ >,
 775                         <  1144 /*  150 MHz */ >,
 776                         <  1525 /*  200 MHz */ >,
 777                         <  2288 /*  300 MHz */ >,
 778                         <  3143 /*  412 MHz */ >,
 779                         <  4173 /*  547 MHz */ >,
 780                         <  5195 /*  681 MHz */ >,
 781                         <  5859 /*  768 MHz */ >,
 782                         <  7759 /* 1017 MHz */ >,
 783                         <  9887 /* 1296 MHz */ >,
 784                         < 11863 /* 1555 MHz */ >,
 785                         < 13763 /* 1804 MHz */ >;
 786         };
 787
 788         memlat_cpu4: qcom,memlat-cpu4 {
 789                 compatible = "qcom,devbw";
 790                 governor = "powersave";
 791                 qcom,src-dst-ports = <1 512>;
 792                 qcom,active-only;
 793                 status = "ok";
 794                 qcom,bw-tbl =
 795                         <   762 /*  100 MHz */ >,
 796                         <  1144 /*  150 MHz */ >,
 797                         <  1525 /*  200 MHz */ >,
 798                         <  2288 /*  300 MHz */ >,
 799                         <  3143 /*  412 MHz */ >,
 800                         <  4173 /*  547 MHz */ >,
 801                         <  5195 /*  681 MHz */ >,
 802                         <  5859 /*  768 MHz */ >,
 803                         <  7759 /* 1017 MHz */ >,
 804                         <  9887 /* 1296 MHz */ >,
 805                         < 11863 /* 1555 MHz */ >,
 806                         < 13763 /* 1804 MHz */ >;
 807         };
 808
 809         devfreq_memlat_0: qcom,arm-memlat-mon-0 {
 810                 compatible = "qcom,arm-memlat-mon";
 811                 qcom,cpulist =  <&CPU0 &CPU1 &CPU2 &CPU3>;
 812                 qcom,target-dev = <&memlat_cpu0>;
 813                 qcom,core-dev-table =
 814                         <  300000 1525 >,
 815                         <  499200 3143 >,
 816                         < 1113600 4173 >,
 817                         < 1881600 5859 >;
 818         };
 819
 820         devfreq_memlat_4: qcom,arm-memlat-mon-4 {
 821                 compatible = "qcom,arm-memlat-mon";
 822                 qcom,cpulist =  <&CPU4 &CPU5 &CPU6 &CPU7>;
 823                 qcom,target-dev = <&memlat_cpu4>;
 824                 qcom,core-dev-table =
 825                         <  300000  1525 >,
 826                         <  480000  3143 >,
 827                         <  900000  4173 >,
 828                         < 1017000  7759 >,
 829                         < 1296000  9887 >,
 830                         < 1555000 11863 >,
 831                         < 1804000 13763 >;
 832         };
 833
 834         devfreq_cpufreq: devfreq-cpufreq {
 835                 mincpubw-cpufreq {
 836                         target-dev = <&mincpubw>;
 837                         cpu-to-dev-map-0 =
 838                                 < 1881600 1525 >;
 839                         cpu-to-dev-map-4 =
 840                                 < 2016000 1525 >,
 841                                 < 2092800 5195 >;
 842                 };
 843         };
 844
 845         msm_cpufreq: qcom,msm-cpufreq {
 846                 compatible = "qcom,msm-cpufreq";
 847                 clock-names = "cpu0_clk", "cpu1_clk", "cpu2_clk",
 848                                 "cpu3_clk", "cpu4_clk", "cpu5_clk",
 849                                 "cpu6_clk", "cpu7_clk";
 850                 clocks = <&clock_cpu clk_pwrcl_clk>,
 851                          <&clock_cpu clk_pwrcl_clk>,
 852                          <&clock_cpu clk_pwrcl_clk>,
 853                          <&clock_cpu clk_pwrcl_clk>,
 854                          <&clock_cpu clk_perfcl_clk>,
 855                          <&clock_cpu clk_perfcl_clk>,
 856                          <&clock_cpu clk_perfcl_clk>,
 857                          <&clock_cpu clk_perfcl_clk>;
 858
 859                 qcom,governor-per-policy;
 860
 861                 qcom,cpufreq-table-0 =
 862                         <  300000 >,
 863                         <  345600 >,
 864                         <  422400 >,
 865                         <  499200 >,
 866                         <  576000 >,
 867                         <  633600 >,
 868                         <  710400 >,
 869                         <  806400 >,
 870                         <  883200 >,
 871                         <  960000 >,
 872                         < 1036800 >,
 873                         < 1113600 >,
 874                         < 1190400 >,
 875                         < 1248000 >,
 876                         < 1324800 >,
 877                         < 1401600 >,
 878                         < 1478400 >,
 879                         < 1574400 >,
 880                         < 1651200 >,
 881                         < 1728000 >,
 882                         < 1804800 >,
 883                         < 1881600 >;
 884
 885                 qcom,cpufreq-table-4 =
 886                         <  300000 >,
 887                         <  345600 >,
 888                         <  422400 >,
 889                         <  480000 >,
 890                         <  556800 >,
 891                         <  633600 >,
 892                         <  710400 >,
 893                         <  787200 >,
 894                         <  844800 >,
 895                         <  902400 >,
 896                         <  979200 >,
 897                         < 1056000 >,
 898                         < 1171200 >,
 899                         < 1248000 >,
 900                         < 1324800 >,
 901                         < 1401600 >,
 902                         < 1478400 >,
 903                         < 1536000 >,
 904                         < 1632000 >,
 905                         < 1708800 >,
 906                         < 1785600 >,
 907                         < 1862400 >,
 908                         < 1939200 >,
 909                         < 2016000 >,
 910                         < 2092800 >;
 911         };
 912
 913         arm64-cpu-erp {
 914                 compatible = "arm,arm64-cpu-erp";
 915                 interrupts = <0 43 4>,
 916                              <0 44 4>,
 917                              <0 41 4>,
 918                              <0 42 4>;
 919
 920                 interrupt-names = "pri-dbe-irq",
 921                                   "sec-dbe-irq",
 922                                   "pri-ext-irq",
 923                                   "sec-ext-irq";
 924
 925                 poll-delay-ms = <5000>;
 926         };
 927
 928         clock_gcc: qcom,gcc@100000 {
 929                 compatible = "qcom,gcc-8998";
 930                 reg = <0x100000 0xb0000>;
 931                 reg-names = "cc_base";
 932                 vdd_dig-supply = <&pm8998_s1_level>;
 933                 vdd_dig_ao-supply = <&pm8998_s1_level_ao>;
 934                 #clock-cells = <1>;
 935                 #reset-cells = <1>;
 936         };
 937
 938         clock_mmss: qcom,mmsscc@c8c0000 {
 939                 compatible = "qcom,mmsscc-8998";
 940                 reg = <0xc8c0000 0x40000>;
 941                 reg-names = "cc_base";
 942                 vdd_dig-supply = <&pm8998_s1_level>;
 943                 vdd_mmsscc_mx-supply = <&pm8998_s9_level>;
 944                 clock-names = "xo", "gpll0", "gpll0_div",
 945                                 "pclk0_src", "pclk1_src",
 946                                 "byte0_src", "byte1_src",
 947                                 "dp_link_src", "dp_vco_div",
 948                                 "extpclk_src";
 949                 clocks = <&clock_gcc clk_cxo_clk_src>,
 950                          <&clock_gcc clk_gcc_mmss_gpll0_clk>,
 951                          <&clock_gcc clk_gcc_mmss_gpll0_div_clk>,
 952                          <&mdss_dsi0_pll clk_dsi0pll_pclk_mux>,
 953                          <&mdss_dsi1_pll clk_dsi1pll_pclk_mux>,
 954                          <&mdss_dsi0_pll clk_dsi0pll_byteclk_mux>,
 955                          <&mdss_dsi1_pll clk_dsi1pll_byteclk_mux>,
 956                          <&mdss_dp_pll clk_dp_link_2x_clk_divsel_five>,
 957                          <&mdss_dp_pll clk_vco_divided_clk_src_mux>,
 958                          <&mdss_hdmi_pll clk_hdmi_vco_clk>;
 959                 #clock-cells = <1>;
 960                 #reset-cells = <1>;
 961         };
 962
 963         clock_gpu: qcom,gpucc@5065000 {
 964                 compatible = "qcom,gpucc-8998";
 965                 reg = <0x5065000 0x9000>;
 966                 reg-names = "cc_base";
 967                 vdd_dig-supply = <&pm8998_s1_level>;
 968                 clock-names = "xo_ao", "gpll0";
 969                 clocks = <&clock_gcc clk_cxo_clk_src_ao>,
 970                         <&clock_gcc clk_gcc_gpu_gpll0_clk>;
 971                 #clock-cells = <1>;
 972         };
 973
 974         clock_gfx: qcom,gfxcc@5065000 {
 975                 compatible = "qcom,gfxcc-8998";
 976                 reg = <0x5065000 0x9000>;
 977                 reg-names = "cc_base";
 978                 vdd_gpucc-supply = <&gfx_vreg>;
 979                 vdd_mx-supply = <&pm8998_s9_level>;
 980                 vdd_gpu_mx-supply = <&pm8998_s9_level>;
 981                 qcom,gfx3d_clk_src-opp-handle = <&msm_gpu>;
 982                 qcom,gfxfreq-speedbin0 =
 983                         <         0 0                           0 >,
 984                         < 171000000 1 RPM_SMD_REGULATOR_LEVEL_SVS >,
 985                         < 251000000 2 RPM_SMD_REGULATOR_LEVEL_SVS >,
 986                         < 332000000 3 RPM_SMD_REGULATOR_LEVEL_SVS >,
 987                         < 403000000 4 RPM_SMD_REGULATOR_LEVEL_SVS >,
 988                         < 504000000 5 RPM_SMD_REGULATOR_LEVEL_NOM >,
 989                         < 650000000 6 RPM_SMD_REGULATOR_LEVEL_TURBO >;
 990                 qcom,gfxfreq-mx-speedbin0 =
 991                         <         0                           0 >,
 992                         < 171000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 993                         < 251000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 994                         < 332000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 995                         < 403000000 RPM_SMD_REGULATOR_LEVEL_SVS >,
 996                         < 504000000 RPM_SMD_REGULATOR_LEVEL_NOM >,
 997                         < 650000000 RPM_SMD_REGULATOR_LEVEL_TURBO >;
 998                 #clock-cells = <1>;
 999         };
1000
1001         clock_cpu: qcom,cpu-clock-8998@179c0000 {
1002                 compatible = "qcom,cpu-clock-osm-msm8998-v1";
1003                 reg = <0x179c0000 0x4000>,
1004                       <0x17916000 0x1000>,
1005                       <0x17816000 0x1000>,
1006                       <0x179d1000 0x1000>,
1007                       <0x00784130 0x8>,
1008                       <0x1791101c 0x8>;
1009                 reg-names = "osm", "pwrcl_pll", "perfcl_pll",
1010                             "apcs_common", "perfcl_efuse", "debug";
1011
1012                 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
1013                 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
1014
1015                 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
1016                              <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1017                 interrupt-names = "pwrcl-irq", "perfcl-irq";
1018
1019                 qcom,pwrcl-speedbin0-v0 =
1020                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1021                         <   345600000 0x05040012 0x02200020 0x1 2 >,
1022                         <   422400000 0x05040016 0x02200020 0x1 3 >,
1023                         <   499200000 0x0504001a 0x02200020 0x1 4 >,
1024                         <   576000000 0x0504001e 0x03200020 0x1 5 >,
1025                         <   633600000 0x05040021 0x03200020 0x1 6 >,
1026                         <   710400000 0x05040025 0x03200020 0x1 7 >,
1027                         <   806400000 0x0504002a 0x04200020 0x1 8 >,
1028                         <   883200000 0x0404002e 0x04250025 0x1 9 >,
1029                         <   960000000 0x04040032 0x05280028 0x1 10 >,
1030                         <  1036800000 0x04040036 0x052b002b 0x2 11 >,
1031                         <  1113600000 0x0404003a 0x052e002e 0x2 12 >,
1032                         <  1190400000 0x0404003e 0x06320032 0x2 13 >,
1033                         <  1248000000 0x04040041 0x06340034 0x2 14 >,
1034                         <  1324800000 0x04040045 0x06370037 0x2 15 >,
1035                         <  1401600000 0x04040049 0x073a003a 0x2 16 >,
1036                         <  1478400000 0x0404004d 0x073e003e 0x2 17 >,
1037                         <  1574400000 0x04040052 0x08420042 0x2 18 >,
1038                         <  1651200000 0x04040056 0x08450045 0x2 19 >,
1039                         <  1728000000 0x0404005a 0x08480048 0x2 20 >,
1040                         <  1804800000 0x0404005e 0x094b004b 0x3 21 >,
1041                         <  1881600000 0x04040062 0x094e004e 0x3 22 >;
1042
1043                 qcom,perfcl-speedbin0-v0 =
1044                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1045                         <   345600000 0x05040012 0x02200020 0x1 2 >,
1046                         <   422400000 0x05040016 0x02200020 0x1 3 >,
1047                         <   480000000 0x05040019 0x02200020 0x1 4 >,
1048                         <   556800000 0x0504001d 0x03200020 0x1 5 >,
1049                         <   633600000 0x05040021 0x03200020 0x1 6 >,
1050                         <   710400000 0x05040025 0x03200020 0x1 7 >,
1051                         <   787200000 0x05040029 0x04200020 0x1 8 >,
1052                         <   844800000 0x0404002c 0x04230023 0x1 9 >,
1053                         <   902400000 0x0404002f 0x04260026 0x1 10 >,
1054                         <   979200000 0x04040033 0x05290029 0x1 11 >,
1055                         <  1056000000 0x04040037 0x052c002c 0x1 12 >,
1056                         <  1171200000 0x0404003d 0x06310031 0x2 13 >,
1057                         <  1248000000 0x04040041 0x06340034 0x2 14 >,
1058                         <  1324800000 0x04040045 0x06370037 0x2 15 >,
1059                         <  1401600000 0x04040049 0x073a003a 0x2 16 >,
1060                         <  1478400000 0x0404004d 0x073e003e 0x2 17 >,
1061                         <  1536000000 0x04040050 0x07400040 0x2 18 >,
1062                         <  1632000000 0x04040055 0x08440044 0x2 19 >,
1063                         <  1708800000 0x04040059 0x08470047 0x2 20 >,
1064                         <  1785600000 0x0404005d 0x094a004a 0x2 21 >,
1065                         <  1862400000 0x04040061 0x094e004e 0x2 22 >,
1066                         <  1939200000 0x04040065 0x09510051 0x3 23 >,
1067                         <  2016000000 0x04040069 0x0a540054 0x3 24 >,
1068                         <  2092800000 0x0404006d 0x0a570057 0x3 25 >;
1069
1070                 qcom,up-timer =
1071                         <1000 1000>;
1072                 qcom,down-timer =
1073                         <1000 1000>;
1074                 qcom,pc-override-index =
1075                         <0 0>;
1076                 qcom,set-ret-inactive;
1077                 qcom,enable-llm-freq-vote;
1078                 qcom,llm-freq-up-timer =
1079                         <327675 327675>;
1080                 qcom,llm-freq-down-timer =
1081                         <327675 327675>;
1082                 qcom,enable-llm-volt-vote;
1083                 qcom,llm-volt-up-timer =
1084                         <327675 327675>;
1085                 qcom,llm-volt-down-timer =
1086                         <327675 327675>;
1087                 qcom,cc-reads = <10>;
1088                 qcom,cc-delay = <5>;
1089                 qcom,cc-factor = <100>;
1090                 qcom,osm-clk-rate = <200000000>;
1091                 qcom,xo-clk-rate = <19200000>;
1092
1093                 qcom,l-val-base =
1094                         <0x17916004 0x17816004>;
1095                 qcom,apcs-itm-present =
1096                         <0x179d143c 0x179d143c>;
1097                 qcom,apcs-pll-user-ctl =
1098                         <0x1791600c 0x1781600c>;
1099                 qcom,apcs-cfg-rcgr =
1100                         <0x17911054 0x17811054>;
1101                 qcom,apcs-cmd-rcgr =
1102                         <0x17911050 0x17811050>;
1103                 qcom,apm-mode-ctl =
1104                         <0x179d0004 0x179d0010>;
1105                 qcom,apm-ctrl-status =
1106                         <0x179d000c 0x179d0018>;
1107                 qcom,llm-sw-overr=
1108                         <0x8fff0036 0x8fff003a 0x0fff0036>,
1109                         <0x8fff003d 0x8fff0041 0x0fff003d>;
1110
1111                 qcom,apm-threshold-voltage = <832000>;
1112                 qcom,boost-fsm-en;
1113                 qcom,safe-fsm-en;
1114                 qcom,ps-fsm-en;
1115                 qcom,droop-fsm-en;
1116                 qcom,wfx-fsm-en;
1117                 qcom,pc-fsm-en;
1118
1119                 qcom,pwrcl-apcs-mem-acc-cfg =
1120                         <0x179d1360 0x179d1364 0x179d1364>;
1121                 qcom,perfcl-apcs-mem-acc-cfg =
1122                         <0x179d1368 0x179d136C 0x179d1370>;
1123                 qcom,pwrcl-apcs-mem-acc-val =
1124                         <0x00000000 0x80000000 0x80000000>,
1125                         <0x00000000 0x00000000 0x00000000>,
1126                         <0x00000000 0x00000001 0x00000001>;
1127                 qcom,perfcl-apcs-mem-acc-val =
1128                         <0x00000000 0x00000000 0x80000000>,
1129                         <0x00000000 0x00000000 0x00000000>,
1130                         <0x00000000 0x00000000 0x00000001>;
1131
1132                 clock-names = "aux_clk", "xo_ao";
1133                 clocks = <&clock_gcc clk_hmss_gpll0_clk_src>,
1134                         <&clock_gcc clk_cxo_clk_src_ao>;
1135                 #clock-cells = <1>;
1136         };
1137
1138         clock_debug: qcom,debugcc@162000 {
1139                 compatible = "qcom,cc-debug-8998";
1140                 reg = <0x162000 0x4>;
1141                 reg-names = "cc_base";
1142                 clock-names = "debug_gpu_clk", "debug_gfx_clk",
1143                                 "debug_mmss_clk", "debug_cpu_clk";
1144                 clocks = <&clock_gpu clk_gpucc_gcc_dbg_clk>,
1145                          <&clock_gfx clk_gfxcc_dbg_clk>,
1146                          <&clock_mmss clk_mmss_debug_mux>,
1147                          <&clock_cpu clk_cpu_debug_mux>;
1148                 #clock-cells = <1>;
1149         };
1150
1151         qcom,rmtfs_sharedmem@0 {
1152                 compatible = "qcom,sharedmem-uio";
1153                 reg = <0x0 0x00200000>;
1154                 reg-names = "rmtfs";
1155                 qcom,client-id = <0x00000001>;
1156         };
1157
1158         qcom,msm_gsi {
1159                 compatible = "qcom,msm_gsi";
1160         };
1161
1162         qcom,rmnet-ipa {
1163                 compatible = "qcom,rmnet-ipa3";
1164                 qcom,rmnet-ipa-ssr;
1165                 qcom,ipa-loaduC;
1166                 qcom,ipa-advertise-sg-support;
1167         };
1168
1169         ipa_hw: qcom,ipa@01e00000 {
1170                 compatible = "qcom,ipa";
1171                 reg = <0x01e00000 0x34000>,
1172                         <0x01e84000 0x31fff>,
1173                         <0x01e04000 0x2c000>;
1174                 reg-names = "ipa-base", "bam-base", "gsi-base";
1175                 interrupts =
1176                         <0 333 0>,
1177                         <0 432 0>,
1178                         <0 432 0>;
1179                 interrupt-names = "ipa-irq", "bam-irq", "gsi-irq";
1180                 qcom,ipa-hw-ver = <11>; /* IPA core version = IPAv3.1 */
1181                 qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
1182                 qcom,ee = <0>;
1183                 qcom,use-gsi;
1184                 qcom,use-ipa-tethering-bridge;
1185                 qcom,modem-cfg-emb-pipe-flt;
1186                 qcom,do-not-use-ch-gsi-20;
1187                 qcom,ipa-wdi2;
1188                 qcom,use-64-bit-dma-mask;
1189                 clocks = <&clock_gcc clk_ipa_clk>;
1190                 clock-names = "core_clk";
1191                 qcom,arm-smmu;
1192                 qcom,smmu-disable-htw;
1193                 qcom,smmu-s1-bypass;
1194                 qcom,msm-bus,name = "ipa";
1195                 qcom,msm-bus,num-cases = <4>;
1196                 qcom,msm-bus,num-paths = <4>;
1197                 qcom,msm-bus,vectors-KBps =
1198                 /* No vote */
1199                         <90 512 0 0>,
1200                         <90 585 0 0>,
1201                         <1 676 0 0>,
1202                          /* SMMU smmu_aggre2_noc_clk */
1203                         <81 10065 0 0>,
1204                 /* SVS */
1205                         <90 512 80000 640000>,
1206                         <90 585 80000 640000>,
1207                         <1 676 80000 80000>,
1208                         /* SMMU smmu_aggre2_noc_clk */
1209                         <81 10065 0 16000>,
1210                 /* NOMINAL */
1211                         <90 512 206000 960000>,
1212                         <90 585 206000 960000>,
1213                         <1 676 206000 160000>,
1214                         /* SMMU smmu_aggre2_noc_clk */
1215                         <81 10065 0 16000>,
1216                 /* TURBO */
1217                         <90 512 206000 3600000>,
1218                         <90 585 206000 3600000>,
1219                         <1 676 206000 300000>,
1220                         /* SMMU smmu_aggre2_noc_clk */
1221                         <81 10065 0 16000>;
1222                 qcom,bus-vector-names = "MIN", "SVS", "NOMINAL", "TURBO";
1223
1224                 /* IPA RAM mmap */
1225                 qcom,ipa-ram-mmap = <
1226                                 0x280   /* ofst_start; */
1227                                 0x0     /* nat_ofst; */
1228                                 0x0     /* nat_size; */
1229                                 0x288   /* v4_flt_hash_ofst; */
1230                                 0x78    /* v4_flt_hash_size; */
1231                                 0x4000  /* v4_flt_hash_size_ddr; */
1232                                 0x308   /* v4_flt_nhash_ofst; */
1233                                 0x78    /* v4_flt_nhash_size; */
1234                                 0x4000  /* v4_flt_nhash_size_ddr; */
1235                                 0x388   /* v6_flt_hash_ofst; */
1236                                 0x78    /* v6_flt_hash_size; */
1237                                 0x4000  /* v6_flt_hash_size_ddr; */
1238                                 0x408   /* v6_flt_nhash_ofst; */
1239                                 0x78    /* v6_flt_nhash_size; */
1240                                 0x4000  /* v6_flt_nhash_size_ddr; */
1241                                 0xf     /* v4_rt_num_index; */
1242                                 0x0     /* v4_modem_rt_index_lo; */
1243                                 0x7     /* v4_modem_rt_index_hi; */
1244                                 0x8     /* v4_apps_rt_index_lo; */
1245                                 0xe     /* v4_apps_rt_index_hi; */
1246                                 0x488   /* v4_rt_hash_ofst; */
1247                                 0x78    /* v4_rt_hash_size; */
1248                                 0x4000  /* v4_rt_hash_size_ddr; */
1249                                 0x508   /* v4_rt_nhash_ofst; */
1250                                 0x78    /* v4_rt_nhash_size; */
1251                                 0x4000  /* v4_rt_nhash_size_ddr; */
1252                                 0xf     /* v6_rt_num_index; */
1253                                 0x0     /* v6_modem_rt_index_lo; */
1254                                 0x7     /* v6_modem_rt_index_hi; */
1255                                 0x8     /* v6_apps_rt_index_lo; */
1256                                 0xe     /* v6_apps_rt_index_hi; */
1257                                 0x588   /* v6_rt_hash_ofst; */
1258                                 0x78    /* v6_rt_hash_size; */
1259                                 0x4000  /* v6_rt_hash_size_ddr; */
1260                                 0x608   /* v6_rt_nhash_ofst; */
1261                                 0x78    /* v6_rt_nhash_size; */
1262                                 0x4000  /* v6_rt_nhash_size_ddr; */
1263                                 0x688   /* modem_hdr_ofst; */
1264                                 0x140   /* modem_hdr_size; */
1265                                 0x7c8   /* apps_hdr_ofst; */
1266                                 0x0     /* apps_hdr_size; */
1267                                 0x800   /* apps_hdr_size_ddr; */
1268                                 0x7d0   /* modem_hdr_proc_ctx_ofst; */
1269                                 0x200   /* modem_hdr_proc_ctx_size; */
1270                                 0x9d0   /* apps_hdr_proc_ctx_ofst; */
1271                                 0x200   /* apps_hdr_proc_ctx_size; */
1272                                 0x0     /* apps_hdr_proc_ctx_size_ddr; */
1273                                 0x0     /* modem_comp_decomp_ofst; diff */
1274                                 0x0     /* modem_comp_decomp_size; diff */
1275                                 0xbd8   /* modem_ofst; */
1276                                 0x1424  /* modem_size; */
1277                                 0x1ffc  /* apps_v4_flt_hash_ofst; */
1278                                 0x0     /* apps_v4_flt_hash_size; */
1279                                 0x1ffc  /* apps_v4_flt_nhash_ofst; */
1280                                 0x0     /* apps_v4_flt_nhash_size; */
1281                                 0x1ffc  /* apps_v6_flt_hash_ofst; */
1282                                 0x0     /* apps_v6_flt_hash_size; */
1283                                 0x1ffc  /* apps_v6_flt_nhash_ofst; */
1284                                 0x0     /* apps_v6_flt_nhash_size; */
1285                                 0x80    /* uc_info_ofst; */
1286                                 0x200   /* uc_info_size; */
1287                                 0x2000  /* end_ofst; */
1288                                 0x1ffc  /* apps_v4_rt_hash_ofst; */
1289                                 0x0     /* apps_v4_rt_hash_size; */
1290                                 0x1ffc  /* apps_v4_rt_nhash_ofst; */
1291                                 0x0     /* apps_v4_rt_nhash_size; */
1292                                 0x1ffc  /* apps_v6_rt_hash_ofst; */
1293                                 0x0     /* apps_v6_rt_hash_size; */
1294                                 0x1ffc  /* apps_v6_rt_nhash_ofst; */
1295                                 0x0     /* apps_v6_rt_nhash_size; */
1296                                 >;
1297
1298                 /* smp2p gpio information */
1299                 qcom,smp2pgpio_map_ipa_1_out {
1300                         compatible = "qcom,smp2pgpio-map-ipa-1-out";
1301                         gpios = <&smp2pgpio_ipa_1_out 0 0>;
1302                 };
1303
1304                 qcom,smp2pgpio_map_ipa_1_in {
1305                         compatible = "qcom,smp2pgpio-map-ipa-1-in";
1306                         gpios = <&smp2pgpio_ipa_1_in 0 0>;
1307                 };
1308
1309                 ipa_smmu_ap: ipa_smmu_ap {
1310                         compatible = "qcom,ipa-smmu-ap-cb";
1311                         iommus = <&anoc2_smmu 0x18e0>;
1312                         qcom,iova-mapping = <0x10000000 0x40000000>;
1313                 };
1314
1315                 ipa_smmu_wlan: ipa_smmu_wlan {
1316                         compatible = "qcom,ipa-smmu-wlan-cb";
1317                         iommus = <&anoc2_smmu 0x18e1>;
1318                 };
1319
1320                 ipa_smmu_uc: ipa_smmu_uc {
1321                         compatible = "qcom,ipa-smmu-uc-cb";
1322                         iommus = <&anoc2_smmu 0x18e2>;
1323                         qcom,iova-mapping = <0x40000000 0x20000000>;
1324                 };
1325         };
1326
1327         qcom,ipa_fws@1e08000 {
1328                 compatible = "qcom,pil-tz-generic";
1329                 qcom,pas-id = <0xF>;
1330                 qcom,firmware-name = "ipa_fws";
1331         };
1332
1333         qcom,chd_silver {
1334                 compatible = "qcom,core-hang-detect";
1335                 label = "silver";
1336                 qcom,threshold-arr = <0x179880b0 0x179980b0
1337                 0x179a80b0 0x179b80b0>;
1338                 qcom,config-arr = <0x179880b8 0x179980b8
1339                 0x179a80b8 0x179b80b8>;
1340         };
1341
1342         qcom,chd_gold {
1343                 compatible = "qcom,core-hang-detect";
1344                 label = "gold";
1345                 qcom,threshold-arr = <0x178880b0 0x178980b0
1346                 0x178a80b0 0x178b80b0>;
1347                 qcom,config-arr = <0x178880b8 0x178980b8
1348                 0x178a80b8 0x178b80b8>;
1349         };
1350
1351         qcom,ipc-spinlock@1f40000 {
1352                 compatible = "qcom,ipc-spinlock-sfpb";
1353                 reg = <0x1f40000 0x8000>;
1354                 qcom,num-locks = <8>;
1355         };
1356
1357         qcom,ghd {
1358                 compatible = "qcom,gladiator-hang-detect";
1359                 qcom,threshold-arr = <0x179d141c 0x179d1420
1360                 0x179d1424 0x179d1428 0x179d142c 0x179d1430>;
1361                 qcom,config-reg = <0x179d1434>;
1362         };
1363
1364         qcom,msm-gladiator-v2@17900000 {
1365                 compatible = "qcom,msm-gladiator-v2";
1366                 reg = <0x17900000 0xe000>;
1367                 reg-names = "gladiator_base";
1368                 interrupts = <0 22 0>;
1369                 clock-names = "atb_clk";
1370                 clocks = <&clock_gcc clk_qdss_clk>;
1371         };
1372
1373         qcom,smem@86000000 {
1374                 compatible = "qcom,smem";
1375                 reg = <0x86000000 0x200000>,
1376                         <0x17911008 0x4>,
1377                         <0x778000 0x7000>,
1378                         <0x1fd4000 0x8>;
1379                 reg-names = "smem", "irq-reg-base", "aux-mem1",
1380                         "smem_targ_info_reg";
1381                 qcom,mpu-enabled;
1382         };
1383
1384         qcom,msm-adsprpc-mem {
1385                 compatible = "qcom,msm-adsprpc-mem-region";
1386                 memory-region = <&adsp_mem>;
1387         };
1388
1389         qcom,msm_fastrpc {
1390                 compatible = "qcom,msm-fastrpc-adsp";
1391                 qcom,fastrpc-glink;
1392
1393                 qcom,msm_fastrpc_cpz_cb1 {
1394                         compatible = "qcom,msm-fastrpc-compute-cb";
1395                         label = "adsprpc-smd";
1396                         iommus = <&lpass_q6_smmu 2>;
1397                         qcom,secure-context-bank;
1398                         dma-coherent;
1399                 };
1400                 qcom,msm_fastrpc_compute_cb1 {
1401                         compatible = "qcom,msm-fastrpc-compute-cb";
1402                         label = "adsprpc-smd";
1403                         iommus = <&lpass_q6_smmu 8>;
1404                         dma-coherent;
1405                 };
1406                 qcom,msm_fastrpc_compute_cb2 {
1407                         compatible = "qcom,msm-fastrpc-compute-cb";
1408                         label = "adsprpc-smd";
1409                         iommus = <&lpass_q6_smmu 9>;
1410                         dma-coherent;
1411                 };
1412                 qcom,msm_fastrpc_compute_cb3 {
1413                         compatible = "qcom,msm-fastrpc-compute-cb";
1414                         label = "adsprpc-smd";
1415                         iommus = <&lpass_q6_smmu 10>;
1416                         dma-coherent;
1417                 };
1418                 qcom,msm_fastrpc_compute_cb4 {
1419                         compatible = "qcom,msm-fastrpc-compute-cb";
1420                         label = "adsprpc-smd";
1421                         iommus = <&lpass_q6_smmu 11>;
1422                         dma-coherent;
1423                 };
1424                 qcom,msm_fastrpc_compute_cb6 {
1425                         compatible = "qcom,msm-fastrpc-compute-cb";
1426                         label = "adsprpc-smd";
1427                         iommus = <&lpass_q6_smmu 5>;
1428                         dma-coherent;
1429                 };
1430                 qcom,msm_fastrpc_compute_cb7 {
1431                         compatible = "qcom,msm-fastrpc-compute-cb";
1432                         label = "adsprpc-smd";
1433                         iommus = <&lpass_q6_smmu 6>;
1434                         dma-coherent;
1435                 };
1436                 qcom,msm_fastrpc_compute_cb8 {
1437                         compatible = "qcom,msm-fastrpc-compute-cb";
1438                         label = "adsprpc-smd";
1439                         iommus = <&lpass_q6_smmu 7>;
1440                         dma-coherent;
1441                 };
1442         };
1443
1444         rpm_bus: qcom,rpm-smd {
1445                 compatible = "qcom,rpm-glink";
1446                 qcom,glink-edge = "rpm";
1447                 rpm-channel-name = "rpm_requests";
1448         };
1449
1450         glink_mpss: qcom,glink-ssr-modem {
1451                 compatible = "qcom,glink_ssr";
1452                 label = "modem";
1453                 qcom,edge = "mpss";
1454                 qcom,notify-edges = <&glink_lpass>, <&glink_dsps>, <&glink_rpm>;
1455                 qcom,xprt = "smem";
1456         };
1457
1458         glink_lpass: qcom,glink-ssr-adsp {
1459                 compatible = "qcom,glink_ssr";
1460                 label = "adsp";
1461                 qcom,edge = "lpass";
1462                 qcom,notify-edges = <&glink_mpss>, <&glink_dsps>, <&glink_rpm>;
1463                 qcom,xprt = "smem";
1464         };
1465
1466         glink_dsps: qcom,glink-ssr-dsps {
1467                 compatible = "qcom,glink_ssr";
1468                 label = "slpi";
1469                 qcom,edge = "dsps";
1470                 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>, <&glink_rpm>;
1471                 qcom,xprt = "smem";
1472         };
1473
1474         glink_rpm: qcom,glink-ssr-rpm {
1475                 compatible = "qcom,glink_ssr";
1476                 label = "rpm";
1477                 qcom,edge = "rpm";
1478                 qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
1479                                         <&glink_dsps>, <&glink_spss>;
1480                 qcom,xprt = "smem";
1481         };
1482
1483         glink_spss: qcom,glink-ssr-spss {
1484                 compatible = "qcom,glink_ssr";
1485                 label = "spss";
1486                 qcom,edge = "spss";
1487                 qcom,notify-edges = <&glink_mpss>, <&glink_lpass>,
1488                                 <&glink_dsps>, <&glink_rpm>;
1489                 qcom,xprt = "mailbox";
1490         };
1491
1492         qcom,glink-smem-native-xprt-modem@86000000 {
1493                 compatible = "qcom,glink-smem-native-xprt";
1494                 reg = <0x86000000 0x200000>,
1495                         <0x17911008 0x4>;
1496                 reg-names = "smem", "irq-reg-base";
1497                 qcom,irq-mask = <0x8000>;
1498                 interrupts = <0 452 1>;
1499                 label = "mpss";
1500         };
1501
1502         qcom,glink-smem-native-xprt-adsp@86000000 {
1503                 compatible = "qcom,glink-smem-native-xprt";
1504                 reg = <0x86000000 0x200000>,
1505                         <0x17911008 0x4>;
1506                 reg-names = "smem", "irq-reg-base";
1507                 qcom,irq-mask = <0x200>;
1508                 interrupts = <0 157 1>;
1509                 label = "lpass";
1510                 qcom,qos-config = <&glink_qos_adsp>;
1511                 qcom,ramp-time = <0xaf>;
1512         };
1513
1514         glink_qos_adsp: qcom,glink-qos-config-adsp {
1515                 compatible = "qcom,glink-qos-config";
1516                 qcom,flow-info = <0x3c 0x0>,
1517                                 <0x3c 0x0>,
1518                                 <0x3c 0x0>,
1519                                 <0x3c 0x0>;
1520                 qcom,mtu-size = <0x800>;
1521                 qcom,tput-stats-cycle = <0xa>;
1522         };
1523
1524         qcom,glink-smem-native-xprt-dsps@86000000 {
1525                 compatible = "qcom,glink-smem-native-xprt";
1526                 reg = <0x86000000 0x200000>,
1527                         <0x17911008 0x4>;
1528                 reg-names = "smem", "irq-reg-base";
1529                 qcom,irq-mask = <0x8000000>;
1530                 interrupts = <0 179 1>;
1531                 label = "dsps";
1532         };
1533
1534         qcom,glink-smem-native-xprt-rpm@778000 {
1535                 compatible = "qcom,glink-rpm-native-xprt";
1536                 reg = <0x778000 0x7000>,
1537                         <0x17911008 0x4>;
1538                 reg-names = "msgram", "irq-reg-base";
1539                 qcom,irq-mask = <0x1>;
1540                 interrupts = <0 168 1>;
1541                 label = "rpm";
1542         };
1543
1544         qcom,glink-mailbox-xprt-spss@1d05008 {
1545                 compatible = "qcom,glink-mailbox-xprt";
1546                 reg = <0x1d05008 0x8>,
1547                         <0x1d05010 0x4>,
1548                         <0x1d0501c 0x4>,
1549                         <0x1d06008 0x4>;
1550                 reg-names = "mbox-loc-addr", "mbox-loc-size", "irq-reg-base",
1551                         "irq-rx-reset";
1552                 qcom,irq-mask = <0x1>;
1553                 interrupts = <0 348 4>;
1554                 label = "spss";
1555                 qcom,tx-ring-size = <0x800>;
1556                 qcom,rx-ring-size = <0x800>;
1557         };
1558
1559         glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1560                 compatible = "qcom,glink-spi-xprt";
1561                 label = "wdsp";
1562                 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1563                 qcom,qos-config = <&glink_qos_wdsp>;
1564                 qcom,ramp-time = <0x10>,
1565                                      <0x20>,
1566                                      <0x30>,
1567                                      <0x40>;
1568         };
1569
1570         glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1571                 compatible = "qcom,glink-fifo-config";
1572                 qcom,out-read-idx-reg = <0x12000>;
1573                 qcom,out-write-idx-reg = <0x12004>;
1574                 qcom,in-read-idx-reg = <0x1200C>;
1575                 qcom,in-write-idx-reg = <0x12010>;
1576         };
1577
1578         glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1579                 compatible = "qcom,glink-qos-config";
1580                 qcom,flow-info = <0x80 0x0>,
1581                                  <0x70 0x1>,
1582                                  <0x60 0x2>,
1583                                  <0x50 0x3>;
1584                 qcom,mtu-size = <0x800>;
1585                 qcom,tput-stats-cycle = <0xa>;
1586         };
1587
1588         qcom,glink_pkt {
1589                 compatible = "qcom,glinkpkt";
1590
1591                 qcom,glinkpkt-at-mdm0 {
1592                         qcom,glinkpkt-transport = "smem";
1593                         qcom,glinkpkt-edge = "mpss";
1594                         qcom,glinkpkt-ch-name = "DS";
1595                         qcom,glinkpkt-dev-name = "at_mdm0";
1596                 };
1597
1598                 qcom,glinkpkt-loopback_cntl {
1599                         qcom,glinkpkt-transport = "lloop";
1600                         qcom,glinkpkt-edge = "local";
1601                         qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1602                         qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1603                 };
1604
1605                 qcom,glinkpkt-loopback_data {
1606                         qcom,glinkpkt-transport = "lloop";
1607                         qcom,glinkpkt-edge = "local";
1608                         qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1609                         qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1610                 };
1611
1612                 qcom,glinkpkt-apr-apps2 {
1613                         qcom,glinkpkt-transport = "smem";
1614                         qcom,glinkpkt-edge = "adsp";
1615                         qcom,glinkpkt-ch-name = "apr_apps2";
1616                         qcom,glinkpkt-dev-name = "apr_apps2";
1617                 };
1618
1619                 qcom,glinkpkt-data40-cntl {
1620                         qcom,glinkpkt-transport = "smem";
1621                         qcom,glinkpkt-edge = "mpss";
1622                         qcom,glinkpkt-ch-name = "DATA40_CNTL";
1623                         qcom,glinkpkt-dev-name = "smdcntl8";
1624                 };
1625
1626                 qcom,glinkpkt-data1 {
1627                         qcom,glinkpkt-transport = "smem";
1628                         qcom,glinkpkt-edge = "mpss";
1629                         qcom,glinkpkt-ch-name = "DATA1";
1630                         qcom,glinkpkt-dev-name = "smd7";
1631                 };
1632
1633                 qcom,glinkpkt-data4 {
1634                         qcom,glinkpkt-transport = "smem";
1635                         qcom,glinkpkt-edge = "mpss";
1636                         qcom,glinkpkt-ch-name = "DATA4";
1637                         qcom,glinkpkt-dev-name = "smd8";
1638                 };
1639
1640                 qcom,glinkpkt-data11 {
1641                         qcom,glinkpkt-transport = "smem";
1642                         qcom,glinkpkt-edge = "mpss";
1643                         qcom,glinkpkt-ch-name = "DATA11";
1644                         qcom,glinkpkt-dev-name = "smd11";
1645                 };
1646         };
1647
1648         qcom,ipc_router {
1649                 compatible = "qcom,ipc_router";
1650                 qcom,node-id = <1>;
1651         };
1652
1653         qcom,ipc_router_modem_xprt {
1654                 compatible = "qcom,ipc_router_glink_xprt";
1655                 qcom,ch-name = "IPCRTR";
1656                 qcom,xprt-remote = "mpss";
1657                 qcom,glink-xprt = "smem";
1658                 qcom,xprt-linkid = <1>;
1659                 qcom,xprt-version = <1>;
1660                 qcom,fragmented-data;
1661         };
1662
1663         qcom,ipc_router_q6_xprt {
1664                 compatible = "qcom,ipc_router_glink_xprt";
1665                 qcom,ch-name = "IPCRTR";
1666                 qcom,xprt-remote = "lpass";
1667                 qcom,glink-xprt = "smem";
1668                 qcom,xprt-linkid = <1>;
1669                 qcom,xprt-version = <1>;
1670                 qcom,fragmented-data;
1671         };
1672
1673         qcom,ipc_router_dsps_xprt {
1674                 compatible = "qcom,ipc_router_glink_xprt";
1675                 qcom,ch-name = "IPCRTR";
1676                 qcom,xprt-remote = "dsps";
1677                 qcom,glink-xprt = "smem";
1678                 qcom,xprt-linkid = <1>;
1679                 qcom,xprt-version = <1>;
1680                 qcom,fragmented-data;
1681                 qcom,dynamic-wakeup-source;
1682         };
1683
1684         qcom,spcom {
1685                 compatible = "qcom,spcom";
1686
1687                 /* predefined channels, remote side is server */
1688                 qcom,spcom-ch-names = "sp_kernel" , "sp_ssr";
1689                 status = "ok";
1690         };
1691
1692         spss_utils: qcom,spss_utils {
1693                 compatible = "qcom,spss-utils";
1694                 /* spss fuses physical address */
1695                 qcom,spss-fuse1-addr = <0x007841c4>;
1696                 qcom,spss-fuse1-bit = <27>;
1697                 qcom,spss-fuse2-addr = <0x0078413c>;
1698                 qcom,spss-fuse2-bit = <31>;
1699                 qcom,spss-test-firmware-name = "spss";    /* default name */
1700                 qcom,spss-prod-firmware-name = "spss1p";  /* 8 chars max */
1701                 qcom,spss-hybr-firmware-name = "spss1h";  /* 8 chars max */
1702                 qcom,spss-debug-reg-addr = <0x01d06020>;
1703                 status = "ok";
1704         };
1705
1706         sdhc_2: sdhci@c0a4900 {
1707                 compatible = "qcom,sdhci-msm";
1708                 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
1709                 reg-names = "hc_mem", "core_mem";
1710
1711                 interrupts = <0 125 0>, <0 221 0>;
1712                 interrupt-names = "hc_irq", "pwr_irq";
1713
1714                 clock-names = "iface_clk", "core_clk";
1715                 clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
1716                          <&clock_gcc clk_gcc_sdcc2_apps_clk>;
1717
1718                 qcom,large-address-bus;
1719                 qcom,bus-width = <4>;
1720                 qcom,cpu-dma-latency-us = <701>;
1721
1722                 qcom,devfreq,freq-table = <52000000 200000000>;
1723
1724                 qcom,msm-bus,name = "sdhc2";
1725                 qcom,msm-bus,num-cases = <8>;
1726                 qcom,msm-bus,num-paths = <1>;
1727                 qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
1728                                 <81 512 1600 3200>,    /* 400 KB/s*/
1729                                 <81 512 80000 160000>, /* 20 MB/s */
1730                                 <81 512 100000 200000>, /* 25 MB/s */
1731                                 <81 512 200000 400000>, /* 50 MB/s */
1732                                 <81 512 400000 800000>, /* 100 MB/s */
1733                                 <81 512 800000 800000>, /* 200 MB/s */
1734                                 <81 512 2048000 4096000>; /* Max. bandwidth */
1735                 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1736                                                 100000000 200000000 4294967295>;
1737
1738                 qcom,sdr104-wa;
1739
1740                 status = "disabled";
1741         };
1742
1743         ufsphy1: ufsphy@1da7000 {
1744                 compatible = "qcom,ufs-phy-qmp-v3";
1745                 reg = <0x1da7000 0xda8>;
1746                 reg-names = "phy_mem";
1747                 #phy-cells = <0>;
1748                 clock-names = "ref_clk_src",
1749                         "ref_clk",
1750                         "ref_aux_clk";
1751                 clocks = <&clock_gcc clk_ln_bb_clk1>,
1752                         <&clock_gcc clk_gcc_ufs_clkref_clk>,
1753                         <&clock_gcc clk_gcc_ufs_phy_aux_hw_ctl_clk>;
1754                 status = "disabled";
1755         };
1756
1757         ufs_ice: ufsice@1db0000 {
1758                 compatible = "qcom,ice";
1759                 reg = <0x1db0000 0x8000>;
1760                 qcom,enable-ice-clk;
1761                 clock-names =   "ufs_core_clk",
1762                                 "bus_clk",
1763                                 "iface_clk",
1764                                 "ice_core_clk";
1765                 clocks = <&clock_gcc clk_gcc_ufs_axi_clk>,
1766                          <&clock_gcc clk_gcc_aggre1_ufs_axi_clk>,
1767                          <&clock_gcc clk_gcc_ufs_ahb_clk>,
1768                          <&clock_gcc clk_gcc_ufs_ice_core_clk>;
1769                 qcom,op-freq-hz =       <0>,
1770                                         <0>,
1771                                         <0>,
1772                                         <300000000>;
1773                 vdd-hba-supply = <&gdsc_ufs>;
1774                 qcom,msm-bus,name = "ufs_ice_noc";
1775                 qcom,msm-bus,num-cases = <2>;
1776                 qcom,msm-bus,num-paths = <1>;
1777                 qcom,msm-bus,vectors-KBps =
1778                                 <1 650 0 0>,    /* No vote */
1779                                 <1 650 1000 0>; /* Max. bandwidth */
1780                 qcom,bus-vector-names = "MIN",
1781                                         "MAX";
1782                 qcom,instance-type = "ufs";
1783                 status = "disabled";
1784         };
1785
1786         ufs1: ufshc@1da4000 {
1787                 compatible = "qcom,ufshc";
1788                 reg = <0x1da4000 0x2500>;
1789                 interrupts = <0 265 0>;
1790                 phys = <&ufsphy1>;
1791                 phy-names = "ufsphy";
1792                 ufs-qcom-crypto = <&ufs_ice>;
1793
1794                 clock-names =
1795                         "core_clk",
1796                         "bus_aggr_clk",
1797                         "iface_clk",
1798                         "core_clk_unipro",
1799                         "core_clk_ice",
1800                         "ref_clk",
1801                         "tx_lane0_sync_clk",
1802                         "rx_lane0_sync_clk";
1803                 clocks =
1804                         <&clock_gcc clk_gcc_ufs_axi_hw_ctl_clk>,
1805                         <&clock_gcc clk_gcc_aggre1_ufs_axi_hw_ctl_clk>,
1806                         <&clock_gcc clk_gcc_ufs_ahb_clk>,
1807                         <&clock_gcc clk_gcc_ufs_unipro_core_hw_ctl_clk>,
1808                         <&clock_gcc clk_gcc_ufs_ice_core_hw_ctl_clk>,
1809                         <&clock_gcc clk_ln_bb_clk1>,
1810                         <&clock_gcc clk_gcc_ufs_tx_symbol_0_clk>,
1811                         <&clock_gcc clk_gcc_ufs_rx_symbol_0_clk>;
1812                 freq-table-hz =
1813                         <50000000 200000000>,
1814                         <0 0>,
1815                         <0 0>,
1816                         <37500000 150000000>,
1817                         <75000000 300000000>,
1818                         <0 0>,
1819                         <0 0>,
1820                         <0 0>;
1821
1822                 lanes-per-direction = <1>;
1823
1824                 qcom,msm-bus,name = "ufs1";
1825                 qcom,msm-bus,num-cases = <22>;
1826                 qcom,msm-bus,num-paths = <2>;
1827                 qcom,msm-bus,vectors-KBps =
1828                 /*
1829                  * During HS G3 UFS runs at nominal voltage corner, vote
1830                  * higher bandwidth to push other buses in the data path
1831                  * to run at nominal to achieve max throughput.
1832                  * 4GBps pushes BIMC to run at nominal.
1833                  * 200MBps pushes CNOC to run at nominal.
1834                  * Vote for half of this bandwidth for HS G3 1-lane.
1835                  * For max bandwidth, vote high enough to push the buses
1836                  * to run in turbo voltage corner.
1837                  */
1838                 <95 512 0 0>, <1 650 0 0>,          /* No vote */
1839                 <95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */
1840                 <95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */
1841                 <95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */
1842                 <95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */
1843                 <95 512 1844 0>, <1 650 1000 0>,    /* PWM G1 L2 */
1844                 <95 512 3688 0>, <1 650 1000 0>,    /* PWM G2 L2 */
1845                 <95 512 7376 0>, <1 650 1000 0>,    /* PWM G3 L2 */
1846                 <95 512 14752 0>, <1 650 1000 0>,   /* PWM G4 L2 */
1847                 <95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */
1848                 <95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */
1849                 <95 512 2097152 0>, <1 650 102400 0>,  /* HS G3 RA */
1850                 <95 512 255591 0>, <1 650 1000 0>,  /* HS G1 RA L2 */
1851                 <95 512 511181 0>, <1 650 1000 0>,  /* HS G2 RA L2 */
1852                 <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RA L2 */
1853                 <95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */
1854                 <95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */
1855                 <95 512 2097152 0>, <1 650 102400 0>,  /* HS G3 RB */
1856                 <95 512 298189 0>, <1 650 1000 0>,  /* HS G1 RB L2 */
1857                 <95 512 596378 0>, <1 650 1000 0>,  /* HS G2 RB L2 */
1858                 <95 512 4194304 0>, <1 650 204800 0>, /* HS G3 RB L2 */
1859                 <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */
1860                 qcom,bus-vector-names = "MIN",
1861                 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
1862                 "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
1863                 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
1864                 "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",
1865                 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
1866                 "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",
1867                 "MAX";
1868
1869                 /* PM QoS */
1870                 qcom,pm-qos-cpu-groups = <0x0F 0xF0>;
1871                 qcom,pm-qos-cpu-group-latency-us = <100 100>;
1872                 qcom,pm-qos-default-cpu = <0>;
1873
1874                 pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
1875                 pinctrl-0 = <&ufs_dev_reset_assert>;
1876                 pinctrl-1 = <&ufs_dev_reset_deassert>;
1877
1878                 resets = <&clock_gcc UFS_BCR>;
1879                 reset-names = "core_reset";
1880
1881                 status = "disabled";
1882         };
1883
1884         usb3: ssusb@a800000 {
1885                 compatible = "qcom,dwc-usb3-msm";
1886                 reg = <0x0a800000 0xf8c00>,
1887                       <0x0c016000 0x400>;
1888                 reg-names = "core_base", "ahb2phy_base";
1889                 #address-cells = <1>;
1890                 #size-cells = <1>;
1891                 ranges;
1892
1893                 interrupts = <0 347 0>, <0 243 0>,  <0 180 0>;
1894                 interrupt-names = "hs_phy_irq", "ss_phy_irq", "pwr_event_irq";
1895
1896                 USB3_GDSC-supply = <&gdsc_usb30>;
1897                 qcom,usb-dbm = <&dbm_1p5>;
1898                 qcom,msm-bus,name = "usb3";
1899                 qcom,msm-bus,num-cases = <2>;
1900                 qcom,msm-bus,num-paths = <1>;
1901                 qcom,msm-bus,vectors-KBps =
1902                                         <61 512 0 0>,
1903                                         <61 512 240000 800000>;
1904
1905                 qcom,dwc-usb3-msm-tx-fifo-size = <21288>;
1906                 extcon = <&pmi8998_pdphy>;
1907
1908                 clocks = <&clock_gcc clk_gcc_usb30_master_clk>,
1909                         <&clock_gcc clk_gcc_cfg_noc_usb3_axi_clk>,
1910                         <&clock_gcc clk_gcc_aggre1_usb3_axi_clk>,
1911                         <&clock_gcc clk_gcc_usb30_mock_utmi_clk>,
1912                         <&clock_gcc clk_gcc_usb30_sleep_clk>,
1913                         <&clock_gcc clk_cxo_dwc3_clk>;
1914
1915                 clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
1916                                 "utmi_clk", "sleep_clk", "xo";
1917
1918                 qcom,core-clk-rate = <120000000>;
1919                 qcom,core-clk-rate-hs = <60000000>;
1920
1921                 resets = <&clock_gcc USB_30_BCR>;
1922                 reset-names = "core_reset";
1923
1924                 dwc3@a800000 {
1925                         compatible = "snps,dwc3";
1926                         reg = <0x0a800000 0xcd00>;
1927                         interrupt-parent = <&intc>;
1928                         interrupts = <0 131 0>;
1929                         usb-phy = <&qusb_phy0>, <&ssphy>;
1930                         tx-fifo-resize;
1931                         snps,nominal-elastic-buffer;
1932                         snps,disable-clk-gating;
1933                         snps,has-lpm-erratum;
1934                         snps,hird-threshold = /bits/ 8 <0x10>;
1935                         snps,num-gsi-evt-buffs = <0x3>;
1936                 };
1937
1938                 qcom,usbbam@a904000 {
1939                         compatible = "qcom,usb-bam-msm";
1940                         reg = <0xa904000 0x17000>;
1941                         interrupt-parent = <&intc>;
1942                         interrupts = <0 132 0>;
1943
1944                         qcom,bam-type = <0>;
1945                         qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
1946                         qcom,usb-bam-num-pipes = <8>;
1947                         qcom,ignore-core-reset-ack;
1948                         qcom,disable-clk-gating;
1949                         qcom,usb-bam-override-threshold = <0x4001>;
1950                         qcom,usb-bam-max-mbps-highspeed = <400>;
1951                         qcom,usb-bam-max-mbps-superspeed = <3600>;
1952                         qcom,reset-bam-on-connect;
1953
1954                         qcom,pipe0 {
1955                                 label = "ssusb-qdss-in-0";
1956                                 qcom,usb-bam-mem-type = <2>;
1957                                 qcom,dir = <1>;
1958                                 qcom,pipe-num = <0>;
1959                                 qcom,peer-bam = <0>;
1960                                 qcom,peer-bam-physical-address = <0x6064000>;
1961                                 qcom,src-bam-pipe-index = <0>;
1962                                 qcom,dst-bam-pipe-index = <0>;
1963                                 qcom,data-fifo-offset = <0x0>;
1964                                 qcom,data-fifo-size = <0x1800>;
1965                                 qcom,descriptor-fifo-offset = <0x1800>;
1966                                 qcom,descriptor-fifo-size = <0x800>;
1967                         };
1968                 };
1969         };
1970
1971         qusb_phy0: qusb@c012000 {
1972                 compatible = "qcom,qusb2phy-v2";
1973                 reg = <0x0c012000 0x2a8>,
1974                       <0x01fcb24c 0x4>;
1975                 reg-names = "qusb_phy_base",
1976                                 "tcsr_clamp_dig_n_1p8";
1977                 vdd-supply = <&pm8998_l1>;
1978                 vdda12-supply = <&pm8998_l2>;
1979                 vdda18-supply = <&pm8998_l12>;
1980                 vdda33-supply = <&pm8998_l24>;
1981                 qcom,vdd-voltage-level = <0 880000 880000>;
1982                 qcom,vdda33-voltage-level = <2400000 3088000 3088000>;
1983                 qcom,qusb-phy-init-seq =
1984                                 /* <value reg_offset> */
1985                                         <0x80 0x0
1986                                         0x13 0x04
1987                                         0x7c 0x18c
1988                                         0x80 0x2c
1989                                         0x0a 0x184
1990                                         0x00 0x240>;
1991                 phy_type= "utmi";
1992
1993                 clocks = <&clock_gcc clk_ln_bb_clk1>,
1994                          <&clock_gcc clk_gcc_rx1_usb2_clkref_clk>;
1995                 clock-names = "ref_clk_src", "ref_clk";
1996
1997                 resets = <&clock_gcc QUSB2PHY_PRIM_BCR>;
1998                 reset-names = "phy_reset";
1999         };
2000
2001         ssphy: ssphy@c010000 {
2002                 compatible = "qcom,usb-ssphy-qmp-v2";
2003                 reg = <0x0c010000 0xe0c>,
2004                       <0x01fcb244 0x4>,
2005                       <0x01fcb248 0x4>;
2006                 reg-names = "qmp_phy_base",
2007                             "vls_clamp_reg",
2008                             "tcsr_usb3_dp_phymode";
2009                 vdd-supply = <&pm8998_l1>;
2010                 core-supply = <&pm8998_l2>;
2011                 qcom,vdd-voltage-level = <0 880000 880000>;
2012                 qcom,vbus-valid-override;
2013                 qcom,qmp-phy-init-seq =
2014                         /* <reg_offset, value, delay> */
2015                         <0x138 0x30 0x00
2016                          0x034 0x04 0x01
2017                          0x080 0x14 0x00
2018                          0x03c 0x06 0x00
2019                          0x08c 0x08 0x00
2020                          0x15c 0x06 0x00
2021                          0x164 0x01 0x00
2022                          0x13c 0x80 0x00
2023                          0x0b0 0x82 0x00
2024                          0x0b8 0xab 0x00
2025                          0x0bc 0xea 0x00
2026                          0x0c0 0x02 0x00
2027                          0x060 0x06 0x00
2028                          0x068 0x16 0x00
2029                          0x070 0x36 0x00
2030                          0x0dc 0x00 0x00
2031                          0x0d8 0x3f 0x00
2032                          0x0f8 0x01 0x00
2033                          0x0f4 0xc9 0x00
2034                          0x148 0x0a 0x00
2035                          0x0a0 0x00 0x00
2036                          0x09c 0x34 0x00
2037                          0x098 0x15 0x00
2038                          0x090 0x04 0x00
2039                          0x154 0x00 0x00
2040                          0x094 0x00 0x00
2041                          0x0f0 0x00 0x00
2042                          0x00c 0x0a 0x00
2043                          0x048 0x07 0x00
2044                          0x0d0 0x80 0x00
2045                          0x184 0x01 0x00
2046                          0x010 0x01 0x00
2047                          0x01c 0x31 0x00
2048                          0x020 0x01 0x00
2049                          0x014 0x00 0x00
2050                          0x018 0x00 0x00
2051                          0x024 0x85 0x00
2052                          0x028 0x07 0x00
2053                          0x430 0x0b 0x00
2054                          0x4d4 0x0f 0x00
2055                          0x4d8 0x4e 0x00
2056                          0x4dc 0x18 0x00
2057                          0x4f8 0x07 0x00
2058                          0x4fc 0x80 0x00
2059                          0x504 0x43 0x00
2060                          0x50c 0x1c 0x00
2061                          0x434 0x75 0x00
2062                          0x43c 0x00 0x00
2063                          0x440 0x00 0x00
2064                          0x444 0x80 0x00
2065                          0x408 0x0a 0x00
2066                          0x414 0x06 0x00
2067                          0x500 0x00 0x00
2068                          0x4c0 0x03 0x00
2069                          0x564 0x05 0x00
2070                          0x830 0x0b 0x00
2071                          0x8d4 0x0f 0x00
2072                          0x8d8 0x4e 0x00
2073                          0x8dc 0x18 0x00
2074                          0x8f8 0x07 0x00
2075                          0x8fc 0x80 0x00
2076                          0x904 0x43 0x00
2077                          0x90c 0x1c 0x00
2078                          0x834 0x75 0x00
2079                          0x83c 0x00 0x00
2080                          0x840 0x00 0x00
2081                          0x844 0x80 0x00
2082                          0x808 0x0a 0x00
2083                          0x814 0x06 0x00
2084                          0x900 0x00 0x00
2085                          0x8c0 0x03 0x00
2086                          0x964 0x05 0x00
2087                          0x260 0x10 0x00
2088                          0x2a4 0x12 0x00
2089                          0x28c 0x16 0x00
2090                          0x244 0x00 0x00
2091                          0x660 0x10 0x00
2092                          0x6a4 0x12 0x00
2093                          0x68c 0x16 0x00
2094                          0x644 0x00 0x00
2095                          0xcc8 0x83 0x00
2096                          0xccc 0x09 0x00
2097                          0xcd0 0xa2 0x00
2098                          0xcd4 0x40 0x00
2099                          0xcc4 0x02 0x00
2100                          0xc80 0xd1 0x00
2101                          0xc84 0x1f 0x00
2102                          0xc88 0x47 0x00
2103                          0xc64 0x1b 0x00
2104                          0xc0c 0x9f 0x00
2105                          0xc10 0x9f 0x00
2106                          0xc14 0xb7 0x00
2107                          0xc18 0x4e 0x00
2108                          0xc1c 0x65 0x00
2109                          0xc20 0x6b 0x00
2110                          0xc24 0x15 0x00
2111                          0xc28 0x0d 0x00
2112                          0xc2c 0x15 0x00
2113                          0xc30 0x0d 0x00
2114                          0xc34 0x15 0x00
2115                          0xc38 0x0d 0x00
2116                          0xc3c 0x15 0x00
2117                          0xc40 0x0d 0x00
2118                          0xc44 0x15 0x00
2119                          0xc48 0x0d 0x00
2120                          0xc4c 0x15 0x00
2121                          0xc50 0x0d 0x00
2122                          0xc5c 0x02 0x00
2123                          0xca0 0x04 0x00
2124                          0xc8c 0x44 0x00
2125                          0xc70 0xe7 0x00
2126                          0xc74 0x03 0x00
2127                          0xc78 0x40 0x00
2128                          0xc7c 0x00 0x00
2129                          0xdd8 0x8a 0x00
2130                          0xcb8 0x75 0x00
2131                          0xcb0 0x86 0x00
2132                          0xcbc 0x13 0x00
2133                          0xffffffff 0xffffffff 0x00>;
2134
2135                 qcom,qmp-phy-reg-offset =
2136                                 <0xd74 /* USB3_PHY_PCS_STATUS */
2137                                  0xcd8 /* USB3_PHY_AUTONOMOUS_MODE_CTRL */
2138                                  0xcdc /* USB3_PHY_LFPS_RXTERM_IRQ_CLEAR */
2139                                  0xc04 /* USB3_PHY_POWER_DOWN_CONTROL */
2140                                  0xc00 /* USB3_PHY_SW_RESET */
2141                                  0xc08 /* USB3_PHY_START */
2142                                  0xa00>; /* USB3PHY_PCS_MISC_TYPEC_CTRL */
2143
2144                 clocks = <&clock_gcc clk_gcc_usb3_phy_aux_clk>,
2145                          <&clock_gcc clk_gcc_usb3_phy_pipe_clk>,
2146                          <&clock_gcc clk_ln_bb_clk1>,
2147                          <&clock_gcc clk_gcc_usb3_clkref_clk>;
2148
2149                 clock-names = "aux_clk", "pipe_clk", "ref_clk_src",
2150                                 "ref_clk";
2151
2152                 resets = <&clock_gcc USB3_PHY_BCR>,
2153                          <&clock_gcc USB3PHY_PHY_BCR>;
2154                 reset-names = "phy_reset", "phy_phy_reset";
2155         };
2156
2157         usb_audio_qmi_dev {
2158                 compatible = "qcom,usb-audio-qmi-dev";
2159                 iommus = <&lpass_q6_smmu 12>;
2160                 qcom,usb-audio-stream-id = <12>;
2161                 qcom,usb-audio-intr-num = <2>;
2162         };
2163
2164         dbm_1p5: dbm@a8f8000 {
2165                 compatible = "qcom,usb-dbm-1p5";
2166                 reg = <0xa8f8000 0x300>;
2167                 qcom,reset-ep-after-lpm-resume;
2168         };
2169
2170         usb_nop_phy: usb_nop_phy {
2171                 compatible = "usb-nop-xceiv";
2172         };
2173
2174         qcom,lpass@17300000 {
2175                 compatible = "qcom,pil-tz-generic";
2176                 reg = <0x17300000 0x00100>;
2177                 interrupts = <0 162 1>;
2178
2179                 vdd_cx-supply = <&pm8998_s1_level>;
2180                 qcom,proxy-reg-names = "vdd_cx";
2181                 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
2182
2183                 clocks = <&clock_gcc clk_cxo_pil_lpass_clk>;
2184                 clock-names = "xo";
2185                 qcom,proxy-clock-names = "xo";
2186
2187                 qcom,pas-id = <1>;
2188                 qcom,proxy-timeout-ms = <10000>;
2189                 qcom,smem-id = <423>;
2190                 qcom,sysmon-id = <1>;
2191                 status = "ok";
2192                 qcom,ssctl-instance-id = <0x14>;
2193                 qcom,firmware-name = "adsp";
2194                 memory-region = <&pil_adsp_mem>;
2195
2196                 /* GPIO inputs from lpass */
2197                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
2198                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
2199                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
2200                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
2201
2202                 /* GPIO output to lpass */
2203                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
2204         };
2205
2206         qcom,memshare {
2207                 compatible = "qcom,memshare";
2208
2209                 qcom,client_1 {
2210                         compatible = "qcom,memshare-peripheral";
2211                         qcom,peripheral-size = <0x200000>;
2212                         qcom,client-id = <0>;
2213                         qcom,allocate-boot-time;
2214                         label = "modem";
2215                 };
2216
2217                 qcom,client_2 {
2218                         compatible = "qcom,memshare-peripheral";
2219                         qcom,peripheral-size = <0x300000>;
2220                         qcom,client-id = <2>;
2221                         label = "modem";
2222                 };
2223
2224                 mem_client_3_size: qcom,client_3 {
2225                         compatible = "qcom,memshare-peripheral";
2226                         qcom,peripheral-size = <0x0>;
2227                         qcom,client-id = <1>;
2228                         qcom,allocate-boot-time;
2229                         label = "modem";
2230                 };
2231         };
2232
2233         pil_modem: qcom,mss@4080000 {
2234                 compatible = "qcom,pil-q6v55-mss";
2235                 reg = <0x4080000 0x100>,
2236                       <0x1f63000 0x008>,
2237                       <0x1f65000 0x008>,
2238                       <0x1f64000 0x008>,
2239                       <0x4180000 0x020>,
2240                       <0x00179000 0x004>;
2241                 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2242                             "halt_nc", "rmb_base", "restart_reg";
2243
2244                 clocks = <&clock_gcc clk_cxo_clk_src>,
2245                          <&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
2246                          <&clock_gcc clk_gcc_bimc_mss_q6_axi_clk>,
2247                          <&clock_gcc clk_gcc_boot_rom_ahb_clk>,
2248                          <&clock_gcc clk_gpll0_out_msscc>,
2249                          <&clock_gcc clk_gcc_mss_snoc_axi_clk>,
2250                          <&clock_gcc clk_gcc_mss_mnoc_bimc_axi_clk>,
2251                          <&clock_gcc clk_qdss_clk>;
2252                 clock-names = "xo", "iface_clk", "bus_clk",
2253                               "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2254                               "mnoc_axi_clk", "qdss_clk";
2255                 qcom,proxy-clock-names = "xo", "qdss_clk", "mem_clk";
2256                 qcom,active-clock-names = "iface_clk", "bus_clk",
2257                         "gpll0_mss_clk", "snoc_axi_clk", "mnoc_axi_clk";
2258
2259                 interrupts = <0 448 1>;
2260                 vdd_cx-supply = <&pm8998_s1_level>;
2261                 vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
2262                 vdd_mx-supply = <&pm8998_s9_level>;
2263                 vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
2264                 qcom,firmware-name = "modem";
2265                 qcom,pil-self-auth;
2266                 qcom,sysmon-id = <0>;
2267                 qcom,ssctl-instance-id = <0x12>;
2268                 qcom,qdsp6v62-1-2;
2269                 status = "ok";
2270                 memory-region = <&modem_mem>;
2271                 qcom,mem-protect-id = <0xF>;
2272
2273                 /* GPIO inputs from mss */
2274                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2275                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2276                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2277                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2278                 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2279
2280                 /* GPIO output to mss */
2281                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
2282                 qcom,mba-mem@0 {
2283                         compatible = "qcom,pil-mba-mem";
2284                         memory-region = <&pil_mba_mem>;
2285                 };
2286         };
2287
2288         tsens0: tsens@10aa000 {
2289                 compatible = "qcom,msm8998-tsens";
2290                 reg = <0x10aa000 0x2000>;
2291                 reg-names = "tsens_physical";
2292                 interrupts = <0 458 0>, <0 445 0>;
2293                 interrupt-names = "tsens-upper-lower", "tsens-critical";
2294                 qcom,client-id = <0 1 2 3 4 7 8 9 10 11 12 13>;
2295                 qcom,sensor-id = <0 1 2 3 4 7 8 9 10 11 12 13>;
2296                 qcom,sensors = <12>;
2297         };
2298
2299         tsens1: tsens@10ad000 {
2300                 compatible = "qcom,msm8998-tsens";
2301                 reg = <0x10ad000 0x2000>;
2302                 reg-names = "tsens_physical";
2303                 interrupts = <0 184 0>, <0 430 0>;
2304                 interrupt-names = "tsens-upper-lower", "tsens-critical";
2305                 qcom,client-id = <14 15 16 17 18 19 20 21>;
2306                 qcom,sensor-id = <0 1 3 4 5 6 7 2>;
2307                 qcom,sensors = <8>;
2308         };
2309
2310         qcom,qbt1000 {
2311                 compatible = "qcom,qbt1000";
2312                 clock-names = "core", "iface";
2313                 clocks = <&clock_gcc clk_gcc_blsp2_qup6_spi_apps_clk>,
2314                         <&clock_gcc clk_gcc_blsp2_ahb_clk>;
2315                 clock-frequency = <15000000>;
2316                 qcom,ipc-gpio = <&tlmm 121 0>;
2317                 qcom,finger-detect-gpio = <&pm8998_gpios 2 0>;
2318         };
2319
2320         qcom,sensor-information {
2321                 compatible = "qcom,sensor-information";
2322                 sensor_information0: qcom,sensor-information-0 {
2323                         qcom,sensor-type = "tsens";
2324                         qcom,sensor-name = "tsens_tz_sensor0";
2325                         qcom,scaling-factor = <10>;
2326                 };
2327                 sensor_information1: qcom,sensor-information-1 {
2328                         qcom,sensor-type =  "tsens";
2329                         qcom,sensor-name = "tsens_tz_sensor1";
2330                         qcom,scaling-factor = <10>;
2331                 };
2332                 sensor_information2: qcom,sensor-information-2 {
2333                         qcom,sensor-type =  "tsens";
2334                         qcom,sensor-name = "tsens_tz_sensor2";
2335                         qcom,scaling-factor = <10>;
2336                 };
2337                 sensor_information3: qcom,sensor-information-3 {
2338                         qcom,sensor-type =  "tsens";
2339                         qcom,sensor-name = "tsens_tz_sensor3";
2340                         qcom,scaling-factor = <10>;
2341                 };
2342                 sensor_information4: qcom,sensor-information-4 {
2343                         qcom,sensor-type = "tsens";
2344                         qcom,sensor-name = "tsens_tz_sensor4";
2345                         qcom,scaling-factor = <10>;
2346                 };
2347                 sensor_information7: qcom,sensor-information-7 {
2348                         qcom,sensor-type = "tsens";
2349                         qcom,sensor-name = "tsens_tz_sensor7";
2350                         qcom,scaling-factor = <10>;
2351                 };
2352                 sensor_information8: qcom,sensor-information-8 {
2353                         qcom,sensor-type = "tsens";
2354                         qcom,sensor-name = "tsens_tz_sensor8";
2355                         qcom,scaling-factor = <10>;
2356                 };
2357                 sensor_information9: qcom,sensor-information-9 {
2358                         qcom,sensor-type = "tsens";
2359                         qcom,sensor-name = "tsens_tz_sensor9";
2360                         qcom,scaling-factor = <10>;
2361                 };
2362                 sensor_information10: qcom,sensor-information-10 {
2363                         qcom,sensor-type = "tsens";
2364                         qcom,sensor-name = "tsens_tz_sensor10";
2365                         qcom,scaling-factor = <10>;
2366                 };
2367                 sensor_information11: qcom,sensor-information-11 {
2368                         qcom,sensor-type = "tsens";
2369                         qcom,sensor-name = "tsens_tz_sensor11";
2370                         qcom,scaling-factor = <10>;
2371                 };
2372                 sensor_information12: qcom,sensor-information-12 {
2373                         qcom,sensor-type = "tsens";
2374                         qcom,sensor-name = "tsens_tz_sensor12";
2375                         qcom,scaling-factor = <10>;
2376                         qcom,alias-name = "gpu_1";
2377                 };
2378                 sensor_information13: qcom,sensor-information-13 {
2379                         qcom,sensor-type = "tsens";
2380                         qcom,sensor-name = "tsens_tz_sensor13";
2381                         qcom,scaling-factor = <10>;
2382                         qcom,alias-name = "gpu";
2383                 };
2384                 sensor_information14: qcom,sensor-information-14 {
2385                         qcom,sensor-type = "tsens";
2386                         qcom,sensor-name = "tsens_tz_sensor14";
2387                         qcom,scaling-factor = <10>;
2388                 };
2389                 sensor_information15: qcom,sensor-information-15 {
2390                         qcom,sensor-type = "tsens";
2391                         qcom,sensor-name = "tsens_tz_sensor15";
2392                         qcom,scaling-factor = <10>;
2393                         qcom,alias-name = "modem_dsp";
2394                 };
2395                 sensor_information16: qcom,sensor-information-16 {
2396                         qcom,sensor-type = "tsens";
2397                         qcom,sensor-name = "tsens_tz_sensor16";
2398                         qcom,scaling-factor = <10>;
2399                 };
2400                 sensor_information17: qcom,sensor-information-17 {
2401                         qcom,sensor-type = "tsens";
2402                         qcom,sensor-name = "tsens_tz_sensor17";
2403                         qcom,scaling-factor = <10>;
2404                         qcom,alias-name = "hvx";
2405                 };
2406                 sensor_information18: qcom,sensor-information-18 {
2407                         qcom,sensor-type = "tsens";
2408                         qcom,sensor-name = "tsens_tz_sensor18";
2409                         qcom,scaling-factor = <10>;
2410                         qcom,alias-name = "camera";
2411                 };
2412                 sensor_information19: qcom,sensor-information-19 {
2413                         qcom,sensor-type = "tsens";
2414                         qcom,sensor-name = "tsens_tz_sensor19";
2415                         qcom,scaling-factor = <10>;
2416                         qcom,alias-name = "multi_media_ss";
2417                 };
2418                 sensor_information20: qcom,sensor-information-20 {
2419                         qcom,sensor-type = "tsens";
2420                         qcom,sensor-name = "tsens_tz_sensor20";
2421                         qcom,scaling-factor = <10>;
2422                         qcom,alias-name = "modem";
2423                 };
2424                 sensor_information21: qcom,sensor-information-21 {
2425                         qcom,sensor-type = "tsens";
2426                         qcom,sensor-name = "tsens_tz_sensor21";
2427                         qcom,scaling-factor = <10>;
2428                         qcom,alias-name = "pop_mem";
2429                 };
2430                 sensor_information22: qcom,sensor-information-22 {
2431                         qcom,sensor-type =  "alarm";
2432                         qcom,sensor-name = "pm8998_tz";
2433                         qcom,scaling-factor = <1000>;
2434                 };
2435                 sensor_information23: qcom,sensor-information-23 {
2436                         qcom,sensor-type =  "adc";
2437                         qcom,sensor-name = "msm_therm";
2438                 };
2439                 sensor_information24: qcom,sensor-information-24 {
2440                         qcom,sensor-type =  "adc";
2441                         qcom,sensor-name = "emmc_therm";
2442                 };
2443                 sensor_information25: qcom,sensor-information-25 {
2444                         qcom,sensor-type =  "adc";
2445                         qcom,sensor-name = "pa_therm0";
2446                 };
2447                 sensor_information26: qcom,sensor-information-26 {
2448                         qcom,sensor-type =  "adc";
2449                         qcom,sensor-name = "pa_therm1";
2450                 };
2451                 sensor_information27: qcom,sensor-information-27 {
2452                         qcom,sensor-type =  "adc";
2453                         qcom,sensor-name = "quiet_therm";
2454                 };
2455                 sensor_information28: qcom,sensor-information-28 {
2456                         qcom,sensor-type = "llm";
2457                         qcom,sensor-name = "limits_sensor-01";
2458                 };
2459                 sensor_information29: qcom,sensor-information-29 {
2460                         qcom,sensor-type = "llm";
2461                         qcom,sensor-name = "limits_sensor-02";
2462                 };
2463         };
2464
2465         qcom_seecom: qseecom@86600000 {
2466                 compatible = "qcom,qseecom";
2467                 reg = <0x86600000 0x2200000>;
2468                 reg-names = "secapp-region";
2469                 qcom,hlos-num-ce-hw-instances = <1>;
2470                 qcom,hlos-ce-hw-instance = <0>;
2471                 qcom,qsee-ce-hw-instance = <0>;
2472                 qcom,disk-encrypt-pipe-pair = <2>;
2473                 qcom,support-fde;
2474                 qcom,no-clock-support;
2475                 qcom,appsbl-qseecom-support;
2476                 qcom,fde-key-size;
2477                 qcom,commonlib64-loaded-by-uefi;
2478                 qcom,msm-bus,name = "qseecom-noc";
2479                 qcom,msm-bus,num-cases = <4>;
2480                 qcom,msm-bus,num-paths = <1>;
2481                 qcom,msm-bus,vectors-KBps =
2482                                 <55 512 0 0>,
2483                                 <55 512 0 0>,
2484                                 <55 512 120000 1200000>,
2485                                 <55 512 393600 3936000>;
2486                 clock-names = "core_clk_src", "core_clk",
2487                                 "iface_clk", "bus_clk";
2488                 clocks = <&clock_gcc clk_ce1_clk>,
2489                          <&clock_gcc clk_qseecom_ce1_clk>,
2490                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2491                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2492                 qcom,ce-opp-freq = <171430000>;
2493                 qcom,qsee-reentrancy-support = <2>;
2494         };
2495
2496         qcom_tzlog: tz-log@146BF720 {
2497                 compatible = "qcom,tz-log";
2498                 reg = <0x146BF720 0x3000>;
2499                 qcom,hyplog-enabled;
2500                 hyplog-address-offset = <0x410>; /* 0x066BFB30 */
2501                 hyplog-size-offset = <0x414>;    /* 0x066BFB34 */
2502         };
2503
2504         qcom_msmhdcp: qcom,msm_hdcp {
2505                 compatible = "qcom,msm-hdcp";
2506         };
2507
2508         qcom_crypto: qcrypto@1DE0000 {
2509                 compatible = "qcom,qcrypto";
2510                 reg = <0x1DE0000 0x20000>,
2511                       <0x1DC4000 0x24000>;
2512                 reg-names = "crypto-base","crypto-bam-base";
2513                 interrupts = <0 206 0>;
2514                 qcom,bam-pipe-pair = <2>;
2515                 qcom,ce-hw-instance = <0>;
2516                 qcom,ce-device = <0>;
2517                 qcom,bam-ee = <0>;
2518                 qcom,ce-hw-shared;
2519                 qcom,clk-mgmt-sus-res;
2520                 qcom,msm-bus,name = "qcrypto-noc";
2521                 qcom,msm-bus,num-cases = <2>;
2522                 qcom,msm-bus,num-paths = <1>;
2523                 qcom,msm-bus,vectors-KBps =
2524                                 <55 512 0 0>,
2525                                 <55 512 3936000 393600>;
2526                 clock-names = "core_clk_src", "core_clk",
2527                                 "iface_clk", "bus_clk";
2528                 clocks = <&clock_gcc clk_qcrypto_ce1_clk>,
2529                          <&clock_gcc clk_qcrypto_ce1_clk>,
2530                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2531                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2532                 qcom,ce-opp-freq = <171430000>;
2533                 qcom,use-sw-aes-cbc-ecb-ctr-algo;
2534                 qcom,use-sw-aes-xts-algo;
2535                 qcom,use-sw-aes-ccm-algo;
2536                 qcom,use-sw-ahash-algo;
2537                 qcom,use-sw-aead-algo;
2538                 qcom,use-sw-hmac-algo;
2539         };
2540
2541         qcom_cedev: qcedev@1DE0000{
2542                 compatible = "qcom,qcedev";
2543                 reg = <0x1DE0000 0x20000>,
2544                       <0x1DC4000 0x24000>;
2545                 reg-names = "crypto-base","crypto-bam-base";
2546                 interrupts = <0 206 0>;
2547                 qcom,bam-pipe-pair = <1>;
2548                 qcom,ce-hw-instance = <0>;
2549                 qcom,ce-device = <0>;
2550                 qcom,ce-hw-shared;
2551                 qcom,bam-ee = <0>;
2552                 qcom,msm-bus,name = "qcedev-noc";
2553                 qcom,msm-bus,num-cases = <2>;
2554                 qcom,msm-bus,num-paths = <1>;
2555                 qcom,msm-bus,vectors-KBps =
2556                                 <55 512 0 0>,
2557                                 <55 512 3936000 393600>;
2558                 clock-names = "core_clk_src", "core_clk",
2559                                 "iface_clk", "bus_clk";
2560                 clocks = <&clock_gcc clk_qcedev_ce1_clk>,
2561                          <&clock_gcc clk_qcedev_ce1_clk>,
2562                          <&clock_gcc clk_gcc_ce1_ahb_m_clk>,
2563                          <&clock_gcc clk_gcc_ce1_axi_m_clk>;
2564                 qcom,ce-opp-freq = <171430000>;
2565         };
2566
2567         qcom_rng: qrng@793000 {
2568                 compatible = "qcom,msm-rng";
2569                 reg = <0x793000 0x1000>;
2570                 qcom,msm-rng-iface-clk;
2571                 qcom,no-qrng-config;
2572                 qcom,msm-bus,name = "msm-rng-noc";
2573                 qcom,msm-bus,num-cases = <2>;
2574                 qcom,msm-bus,num-paths = <1>;
2575                 qcom,msm-bus,vectors-KBps =
2576                         <1 618 0 0>,    /* No vote */
2577                         <1 618 0 800>;  /* 100 MB/s */
2578                 clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
2579                 clock-names = "iface_clk";
2580         };
2581
2582         mitigation_profile0: qcom,limit_info-0 {
2583                 qcom,temperature-sensor = <&sensor_information1>;
2584                 qcom,hotplug-mitigation-enable;
2585         };
2586
2587         mitigation_profile1: qcom,limit_info-1 {
2588                 qcom,temperature-sensor = <&sensor_information2>;
2589                 qcom,hotplug-mitigation-enable;
2590         };
2591
2592         mitigation_profile2: qcom,limit_info-2 {
2593                 qcom,temperature-sensor = <&sensor_information3>;
2594                 qcom,hotplug-mitigation-enable;
2595         };
2596
2597         mitigation_profile3: qcom,limit_info-3 {
2598                 qcom,temperature-sensor = <&sensor_information4>;
2599                 qcom,hotplug-mitigation-enable;
2600         };
2601
2602         mitigation_profile4: qcom,limit_info-4 {
2603                 qcom,temperature-sensor = <&sensor_information7>;
2604                 qcom,hotplug-mitigation-enable;
2605         };
2606
2607         mitigation_profile5: qcom,limit_info-5 {
2608                 qcom,temperature-sensor = <&sensor_information8>;
2609                 qcom,hotplug-mitigation-enable;
2610         };
2611
2612         mitigation_profile6: qcom,limit_info-6 {
2613                 qcom,temperature-sensor = <&sensor_information9>;
2614                 qcom,hotplug-mitigation-enable;
2615         };
2616
2617         mitigation_profile7: qcom,limit_info-7 {
2618                 qcom,temperature-sensor = <&sensor_information10>;
2619                 qcom,hotplug-mitigation-enable;
2620         };
2621
2622         qcom,lmh {
2623                 compatible = "qcom,lmh_v1";
2624                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
2625         };
2626
2627         qcom,msm-thermal {
2628                 compatible = "qcom,msm-thermal";
2629                 qcom,sensor-id = <1>;
2630                 qcom,poll-ms = <200>;
2631                 qcom,therm-reset-temp = <115>;
2632                 qcom,core-limit-temp = <70>;
2633                 qcom,core-temp-hysteresis = <10>;
2634                 qcom,hotplug-temp = <105>;
2635                 qcom,hotplug-temp-hysteresis = <20>;
2636                 qcom,online-hotplug-core;
2637                 qcom,synchronous-cluster-id = <0 1>;
2638                 qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>,
2639                                                 <1 4 &CPU4 &CPU5 &CPU6 &CPU7>;
2640                 clock-names = "osm";
2641                 clocks = <&clock_cpu clk_pwrcl_clk>;
2642
2643                 qcom,vdd-restriction-temp = <5>;
2644                 qcom,vdd-restriction-temp-hysteresis = <10>;
2645
2646                 vdd-dig-supply = <&pm8998_s1_floor_level>;
2647                 vdd-gfx-supply = <&gfx_vreg>;
2648
2649                 qcom,vdd-dig-rstr{
2650                         qcom,vdd-rstr-reg = "vdd-dig";
2651                         qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM
2652                                         RPM_SMD_REGULATOR_LEVEL_TURBO
2653                                         RPM_SMD_REGULATOR_LEVEL_TURBO>;
2654                                 /* Nominal, Super Turbo, Super Turbo */
2655                         qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;
2656                                 /* No Request */
2657                 };
2658
2659                 qcom,vdd-gfx-rstr{
2660                         qcom,vdd-rstr-reg = "vdd-gfx";
2661                         qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */
2662                         qcom,min-level = <1>; /* No Request */
2663                 };
2664
2665                 msm_thermal_freq: qcom,vdd-apps-rstr{
2666                         qcom,vdd-rstr-reg = "vdd-apps";
2667                         qcom,levels = <1248000>;
2668                         qcom,freq-req;
2669                 };
2670         };
2671
2672         pcie0: qcom,pcie@01c00000 {
2673                 compatible = "qcom,pci-msm";
2674                 cell-index = <0>;
2675
2676                 reg = <0x1c00000 0x2000>,
2677                       <0x1c06000 0x1000>,
2678                       <0x1b000000 0xf1d>,
2679                       <0x1b000f20 0xa8>,
2680                       <0x1b100000 0x100000>,
2681                       <0x1b200000 0x100000>,
2682                       <0x1b300000 0xd00000>;
2683
2684                 reg-names = "parf", "phy", "dm_core", "elbi",
2685                                 "conf", "io", "bars";
2686
2687                 #address-cells = <3>;
2688                 #size-cells = <2>;
2689                 ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
2690                         <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
2691                 interrupt-parent = <&pcie0>;
2692                 interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
2693                                 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35
2694                                 36 37>;
2695                 #interrupt-cells = <1>;
2696                 interrupt-map-mask = <0 0 0 0xffffffff>;
2697                 interrupt-map = <0 0 0 0 &intc 0 0 405 0
2698                                 0 0 0 1 &intc 0 0 135 0
2699                                 0 0 0 2 &intc 0 0 136 0
2700                                 0 0 0 3 &intc 0 0 138 0
2701                                 0 0 0 4 &intc 0 0 139 0
2702                                 0 0 0 5 &intc 0 0 278 0
2703                                 0 0 0 6 &intc 0 0 576 0
2704                                 0 0 0 7 &intc 0 0 577 0
2705                                 0 0 0 8 &intc 0 0 578 0
2706                                 0 0 0 9 &intc 0 0 579 0
2707                                 0 0 0 10 &intc 0 0 580 0
2708                                 0 0 0 11 &intc 0 0 581 0
2709                                 0 0 0 12 &intc 0 0 582 0
2710                                 0 0 0 13 &intc 0 0 583 0
2711                                 0 0 0 14 &intc 0 0 584 0
2712                                 0 0 0 15 &intc 0 0 585 0
2713                                 0 0 0 16 &intc 0 0 586 0
2714                                 0 0 0 17 &intc 0 0 587 0
2715                                 0 0 0 18 &intc 0 0 588 0
2716                                 0 0 0 19 &intc 0 0 589 0
2717                                 0 0 0 20 &intc 0 0 590 0
2718                                 0 0 0 21 &intc 0 0 591 0
2719                                 0 0 0 22 &intc 0 0 592 0
2720                                 0 0 0 23 &intc 0 0 593 0
2721                                 0 0 0 24 &intc 0 0 594 0
2722                                 0 0 0 25 &intc 0 0 595 0
2723                                 0 0 0 26 &intc 0 0 596 0
2724                                 0 0 0 27 &intc 0 0 597 0
2725                                 0 0 0 28 &intc 0 0 598 0
2726                                 0 0 0 29 &intc 0 0 599 0
2727                                 0 0 0 30 &intc 0 0 600 0
2728                                 0 0 0 31 &intc 0 0 601 0
2729                                 0 0 0 32 &intc 0 0 602 0
2730                                 0 0 0 33 &intc 0 0 603 0
2731                                 0 0 0 34 &intc 0 0 604 0
2732                                 0 0 0 35 &intc 0 0 605 0
2733                                 0 0 0 36 &intc 0 0 606 0
2734                                 0 0 0 37 &intc 0 0 607 0>;
2735
2736                 interrupt-names = "int_msi", "int_a", "int_b", "int_c",
2737                                 "int_d", "int_global_int",
2738                                 "msi_0", "msi_1", "msi_2", "msi_3",
2739                                 "msi_4", "msi_5", "msi_6", "msi_7",
2740                                 "msi_8", "msi_9", "msi_10", "msi_11",
2741                                 "msi_12", "msi_13", "msi_14", "msi_15",
2742                                 "msi_16", "msi_17", "msi_18", "msi_19",
2743                                 "msi_20", "msi_21", "msi_22", "msi_23",
2744                                 "msi_24", "msi_25", "msi_26", "msi_27",
2745                                 "msi_28", "msi_29", "msi_30", "msi_31";
2746
2747                 qcom,phy-sequence = <0x804 0x01 0x00
2748                                         0x034 0x14 0x00
2749                                         0x138 0x30 0x00
2750                                         0x048 0x0f 0x00
2751                                         0x15c 0x06 0x00
2752                                         0x090 0x01 0x00
2753                                         0x088 0x20 0x00
2754                                         0x0f0 0x00 0x00
2755                                         0x0f8 0x01 0x00
2756                                         0x0f4 0xc9 0x00
2757                                         0x11c 0xff 0x00
2758                                         0x120 0x3f 0x00
2759                                         0x164 0x01 0x00
2760                                         0x154 0x00 0x00
2761                                         0x148 0x0a 0x00
2762                                         0x05C 0x19 0x00
2763                                         0x038 0x90 0x00
2764                                         0x0b0 0x82 0x00
2765                                         0x0c0 0x03 0x00
2766                                         0x0bc 0x55 0x00
2767                                         0x0b8 0x55 0x00
2768                                         0x0a0 0x00 0x00
2769                                         0x09c 0x0d 0x00
2770                                         0x098 0x04 0x00
2771                                         0x13c 0x00 0x00
2772                                         0x060 0x08 0x00
2773                                         0x068 0x16 0x00
2774                                         0x070 0x34 0x00
2775                                         0x15c 0x06 0x00
2776                                         0x138 0x33 0x00
2777                                         0x03c 0x02 0x00
2778                                         0x040 0x0e 0x00
2779                                         0x080 0x04 0x00
2780                                         0x0dc 0x00 0x00
2781                                         0x0d8 0x3f 0x00
2782                                         0x00c 0x09 0x00
2783                                         0x010 0x01 0x00
2784                                         0x01c 0x40 0x00
2785                                         0x020 0x01 0x00
2786                                         0x014 0x02 0x00
2787                                         0x018 0x00 0x00
2788                                         0x024 0x7e 0x00
2789                                         0x028 0x15 0x00
2790                                         0x244 0x02 0x00
2791                                         0x2a4 0x12 0x00
2792                                         0x260 0x10 0x00
2793                                         0x28c 0x06 0x00
2794                                         0x504 0x03 0x00
2795                                         0x500 0x10 0x00
2796                                         0x50c 0x14 0x00
2797                                         0x4d4 0x0a 0x00
2798                                         0x4d8 0x04 0x00
2799                                         0x4dc 0x1a 0x00
2800                                         0x434 0x4b 0x00
2801                                         0x414 0x04 0x00
2802                                         0x40c 0x04 0x00
2803                                         0x4f8 0x00 0x00
2804                                         0x4fc 0x80 0x00
2805                                         0x51c 0x40 0x00
2806                                         0x444 0x71 0x00
2807                                         0x43c 0x40 0x00
2808                                         0x854 0x04 0x00
2809                                         0x62c 0x52 0x00
2810                                         0x9ac 0x00 0x00
2811                                         0x8a0 0x01 0x00
2812                                         0x9e0 0x00 0x00
2813                                         0x9dc 0x20 0x00
2814                                         0x9a8 0x00 0x00
2815                                         0x8a4 0x01 0x00
2816                                         0x8a8 0x73 0x00
2817                                         0x9d8 0xaa 0x00
2818                                         0x9b0 0x03 0x00
2819                                         0x804 0x03 0x00
2820                                         0x800 0x00 0x00
2821                                         0x808 0x03 0x00>;
2822
2823                 pinctrl-names = "default", "sleep";
2824                 pinctrl-0 = <&pcie0_clkreq_default
2825                         &pcie0_perst_default
2826                         &pcie0_wake_default>;
2827                 pinctrl-1 = <&pcie0_clkreq_default
2828                         &pcie0_perst_default
2829                         &pcie0_wake_sleep>;
2830
2831                 perst-gpio = <&tlmm 35 0>;
2832                 wake-gpio = <&tlmm 37 0>;
2833
2834                 gdsc-vdd-supply = <&gdsc_pcie_0>;
2835                 vreg-1.8-supply = <&pm8998_l2>;
2836                 vreg-0.9-supply = <&pm8998_l1>;
2837                 vreg-cx-supply = <&pm8998_s1_level>;
2838
2839                 qcom,vreg-1.8-voltage-level = <1200000 1200000 24000>;
2840                 qcom,vreg-0.9-voltage-level = <880000 880000 24000>;
2841                 qcom,vreg-cx-voltage-level = <RPM_SMD_REGULATOR_LEVEL_BINNING
2842                                                 RPM_SMD_REGULATOR_LEVEL_SVS 0>;
2843
2844                 qcom,l1-supported;
2845                 qcom,l1ss-supported;
2846                 qcom,aux-clk-sync;
2847
2848                 qcom,ep-latency = <10>;
2849
2850                 qcom,boot-option = <0x1>;
2851
2852                 linux,pci-domain = <0>;
2853
2854                 qcom,msi-gicm-addr = <0x17a00040>;
2855                 qcom,msi-gicm-base = <0x260>;
2856
2857                 qcom,pcie-phy-ver = <0x20>;
2858                 qcom,use-19p2mhz-aux-clk;
2859
2860                 iommus = <&anoc1_smmu>;
2861                 qcom,smmu-exist;
2862                 qcom,smmu-sid-base = <0x1480>;
2863
2864                 qcom,msm-bus,name = "pcie0";
2865                 qcom,msm-bus,num-cases = <2>;
2866                 qcom,msm-bus,num-paths = <1>;
2867                 qcom,msm-bus,vectors-KBps =
2868                                 <45 512 0 0>,
2869                                 <45 512 500 800>;
2870
2871                 clocks = <&clock_gcc clk_gcc_pcie_0_pipe_clk>,
2872                         <&clock_gcc clk_ln_bb_clk1>,
2873                         <&clock_gcc clk_gcc_pcie_0_aux_clk>,
2874                         <&clock_gcc clk_gcc_pcie_0_cfg_ahb_clk>,
2875                         <&clock_gcc clk_gcc_pcie_0_mstr_axi_clk>,
2876                         <&clock_gcc clk_gcc_pcie_0_slv_axi_clk>,
2877                         <&clock_gcc clk_gcc_pcie_clkref_clk>;
2878
2879                 clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
2880                                 "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
2881                                 "pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
2882                                 "pcie_0_ldo";
2883
2884                 max-clock-frequency-hz = <0>, <0>, <19200000>,
2885                                         <0>, <0>, <0>, <0>, <0>, <0>,
2886                                         <0>, <0>, <0>, <0>, <0>, <0>,
2887                                         <0>, <0>;
2888
2889                 resets = <&clock_gcc PCIE_PHY_BCR>,
2890                          <&clock_gcc PCIE_0_PHY_BCR>,
2891                          <&clock_gcc PCIE_0_PHY_BCR>;
2892
2893                 reset-names = "pcie_phy_reset",
2894                                 "pcie_0_phy_reset",
2895                                 "pcie_0_phy_pipe_reset";
2896         };
2897
2898         qcom,bcl {
2899                 compatible = "qcom,bcl";
2900                 qcom,bcl-enable;
2901                 qcom,bcl-framework-interface;
2902                 qcom,bcl-freq-control-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
2903                 qcom,bcl-hotplug-list = <>;
2904                 qcom,bcl-soc-hotplug-list = <>;
2905                 qcom,ibat-monitor {
2906                         qcom,low-threshold-uamp = <3400000>;
2907                         qcom,high-threshold-uamp = <4200000>;
2908                         qcom,mitigation-freq-khz = <576000>;
2909                         qcom,vph-high-threshold-uv = <3500000>;
2910                         qcom,vph-low-threshold-uv = <3300000>;
2911                         qcom,soc-low-threshold = <10>;
2912                         qcom,thermal-handle = <&msm_thermal_freq>;
2913                 };
2914         };
2915
2916         qcom,ssc@5c00000 {
2917                 compatible = "qcom,pil-tz-generic";
2918                 reg = <0x5c00000 0x4000>;
2919                 interrupts = <0 390 1>;
2920
2921                 vdd_cx-supply = <&pm8998_l27_level>;
2922                 vdd_px-supply = <&pm8998_lvs2>;
2923                 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 0>;
2924                 qcom,proxy-reg-names = "vdd_cx", "vdd_px";
2925                 qcom,keep-proxy-regs-on;
2926
2927                 clocks = <&clock_gcc clk_cxo_pil_ssc_clk>,
2928                          <&clock_gcc clk_aggre2_noc_clk>;
2929                 clock-names = "xo", "aggre2";
2930                 qcom,proxy-clock-names = "xo", "aggre2";
2931
2932                 qcom,pas-id = <12>;
2933                 qcom,proxy-timeout-ms = <10000>;
2934                 qcom,smem-id = <424>;
2935                 qcom,sysmon-id = <3>;
2936                 qcom,ssctl-instance-id = <0x16>;
2937                 qcom,firmware-name = "slpi";
2938                 status = "ok";
2939                 memory-region = <&pil_slpi_mem>;
2940
2941                 /* GPIO inputs from ssc */
2942                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_3_in 0 0>;
2943                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_3_in 2 0>;
2944                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_3_in 1 0>;
2945                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_3_in 3 0>;
2946
2947                 /* GPIO output to ssc */
2948                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_3_out 0 0>;
2949         };
2950
2951         qcom,venus@cce0000 {
2952                 compatible = "qcom,pil-tz-generic";
2953                 reg = <0xcce0000 0x4000>;
2954
2955                 vdd-supply = <&gdsc_venus>;
2956                 qcom,proxy-reg-names = "vdd";
2957
2958                 clocks = <&clock_mmss clk_mmss_video_core_clk>,
2959                          <&clock_mmss clk_mmss_mnoc_ahb_clk>,
2960                          <&clock_mmss clk_mmss_video_ahb_clk>,
2961                          <&clock_gcc clk_mmssnoc_axi_clk>,
2962                          <&clock_mmss clk_mmss_video_axi_clk>,
2963                          <&clock_mmss clk_mmss_video_maxi_clk>;
2964                 clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk",
2965                               "noc_axi_clk", "bus_clk", "maxi_clk";
2966                 qcom,proxy-clock-names = "core_clk","mnoc_ahb_clk",
2967                  "iface_clk", "noc_axi_clk", "bus_clk", "maxi_clk";
2968
2969                 qcom,pas-id = <9>;
2970                 qcom,msm-bus,name = "pil-venus";
2971                 qcom,msm-bus,num-cases = <2>;
2972                 qcom,msm-bus,num-paths = <1>;
2973                 qcom,msm-bus,vectors-KBps =
2974                         <63 512 0 0>,
2975                         <63 512 0 304000>;
2976                 qcom,proxy-timeout-ms = <100>;
2977                 qcom,firmware-name = "venus";
2978                 memory-region = <&pil_video_mem>;
2979                 status = "ok";
2980         };
2981
2982         wdog: qcom,wdt@17817000 {
2983                 compatible = "qcom,msm-watchdog";
2984                 reg = <0x17817000 0x1000>;
2985                 reg-names = "wdt-base";
2986                 interrupts = <0 3 0>, <0 4 0>;
2987                 qcom,bark-time = <11000>;
2988                 qcom,pet-time = <10000>;
2989                 qcom,ipi-ping;
2990                 qcom,wakeup-enable;
2991                 qcom,scandump-size = <0x40000>;
2992         };
2993
2994         qcom,spss@1d00000 {
2995                 compatible = "qcom,pil-tz-generic";
2996                 reg = <0x1d0101c 0x4>,
2997                       <0x1d01024 0x4>,
2998                       <0x1d01028 0x4>,
2999                       <0x1d0103c 0x4>,
3000                       <0x1d02030 0x4>;
3001                 reg-names = "sp2soc_irq_status", "sp2soc_irq_clr",
3002                             "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2";
3003                 interrupts = <0 352 1>;
3004
3005                 vdd_cx-supply = <&pm8998_s1_level>;
3006                 qcom,proxy-reg-names = "vdd_cx";
3007                 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
3008
3009                 clocks = <&clock_gcc clk_cxo_pil_spss_clk>;
3010                 clock-names = "xo";
3011                 qcom,proxy-clock-names = "xo";
3012                 qcom,pil-generic-irq-handler;
3013                 status = "ok";
3014
3015                 qcom,pas-id = <14>;
3016                 qcom,proxy-timeout-ms = <10000>;
3017                 qcom,firmware-name = "spss";
3018                 memory-region = <&spss_mem>;
3019                 qcom,spss-scsr-bits = <24 25>;
3020         };
3021
3022         qcom,msm-rtb {
3023                 compatible = "qcom,msm-rtb";
3024                 qcom,rtb-size = <0x100000>;
3025         };
3026
3027         qcom,mpm2-sleep-counter@10a3000 {
3028                 compatible = "qcom,mpm2-sleep-counter";
3029                 reg = <0x010a3000 0x1000>;
3030                 clock-frequency = <32768>;
3031         };
3032
3033         qcom,msm-imem@146bf000 {
3034                 compatible = "qcom,msm-imem";
3035                 reg = <0x146bf000 0x1000>;
3036                 ranges = <0x0 0x146bf000 0x1000>;
3037                 #address-cells = <1>;
3038                 #size-cells = <1>;
3039
3040                 mem_dump_table@10 {
3041                         compatible = "qcom,msm-imem-mem_dump_table";
3042                         reg = <0x10 8>;
3043                 };
3044
3045                 dload_type@1c {
3046                         compatible = "qcom,msm-imem-dload-type";
3047                         reg = <0x1c 4>;
3048                 };
3049
3050                 restart_reason@65c {
3051                         compatible = "qcom,msm-imem-restart_reason";
3052                         reg = <0x65c 4>;
3053                 };
3054
3055                 boot_stats@6b0 {
3056                         compatible = "qcom,msm-imem-boot_stats";
3057                         reg = <0x6b0 32>;
3058                 };
3059
3060                 kaslr_offset@6d0 {
3061                         compatible = "qcom,msm-imem-kaslr_offset";
3062                         reg = <0x6d0 12>;
3063                 };
3064
3065                 pil@94c {
3066                         compatible = "qcom,msm-imem-pil";
3067                         reg = <0x94c 200>;
3068                 };
3069
3070                 diag_dload@c8 {
3071                         compatible = "qcom,msm-imem-diag-dload";
3072                         reg = <0xc8 200>;
3073                 };
3074         };
3075
3076         cpu_pmu: cpu-pmu {
3077                 compatible = "arm,armv8-pmuv3";
3078                 qcom,irq-is-percpu;
3079                 interrupts = <1 6 4>;
3080         };
3081
3082         cpuss_dump {
3083                 compatible = "qcom,cpuss-dump";
3084                 qcom,l1_i_cache0 {
3085                         qcom,dump-node = <&L1_I_0>;
3086                         qcom,dump-id = <0x60>;
3087                 };
3088                 qcom,l1_i_cache1 {
3089                         qcom,dump-node = <&L1_I_1>;
3090                         qcom,dump-id = <0x61>;
3091                 };
3092                 qcom,l1_i_cache2 {
3093                         qcom,dump-node = <&L1_I_2>;
3094                         qcom,dump-id = <0x62>;
3095                 };
3096                 qcom,l1_i_cache3 {
3097                         qcom,dump-node = <&L1_I_3>;
3098                         qcom,dump-id = <0x63>;
3099                 };
3100                 qcom,l1_i_cache100 {
3101                         qcom,dump-node = <&L1_I_100>;
3102                         qcom,dump-id = <0x64>;
3103                 };
3104                 qcom,l1_i_cache101 {
3105                         qcom,dump-node = <&L1_I_101>;
3106                         qcom,dump-id = <0x65>;
3107                 };
3108                 qcom,l1_i_cache102 {
3109                         qcom,dump-node = <&L1_I_102>;
3110                         qcom,dump-id = <0x66>;
3111                 };
3112                 qcom,l1_i_cache103 {
3113                         qcom,dump-node = <&L1_I_103>;
3114                         qcom,dump-id = <0x67>;
3115                 };
3116                 qcom,l1_d_cache0 {
3117                         qcom,dump-node = <&L1_D_0>;
3118                         qcom,dump-id = <0x80>;
3119                 };
3120                 qcom,l1_d_cache1 {
3121                         qcom,dump-node = <&L1_D_1>;
3122                         qcom,dump-id = <0x81>;
3123                 };
3124                 qcom,l1_d_cache2 {
3125                         qcom,dump-node = <&L1_D_2>;
3126                         qcom,dump-id = <0x82>;
3127                 };
3128                 qcom,l1_d_cache3 {
3129                         qcom,dump-node = <&L1_D_3>;
3130                         qcom,dump-id = <0x83>;
3131                 };
3132                 qcom,l1_d_cache100 {
3133                         qcom,dump-node = <&L1_D_100>;
3134                         qcom,dump-id = <0x84>;
3135                 };
3136                 qcom,l1_d_cache101 {
3137                         qcom,dump-node = <&L1_D_101>;
3138                         qcom,dump-id = <0x85>;
3139                 };
3140                 qcom,l1_d_cache102 {
3141                         qcom,dump-node = <&L1_D_102>;
3142                         qcom,dump-id = <0x86>;
3143                 };
3144                 qcom,l1_d_cache103 {
3145                         qcom,dump-node = <&L1_D_103>;
3146                         qcom,dump-id = <0x87>;
3147                 };
3148                 qcom,l1_tlb_dump0 {
3149                         qcom,dump-node = <&L1_TLB_0>;
3150                         qcom,dump-id = <0x20>;
3151                 };
3152                 qcom,l1_tlb_dump1 {
3153                         qcom,dump-node = <&L1_TLB_1>;
3154                         qcom,dump-id = <0x21>;
3155                 };
3156                 qcom,l1_tlb_dump2 {
3157                         qcom,dump-node = <&L1_TLB_2>;
3158                         qcom,dump-id = <0x22>;
3159                 };
3160                 qcom,l1_tlb_dump3 {
3161                         qcom,dump-node = <&L1_TLB_3>;
3162                         qcom,dump-id = <0x23>;
3163                 };
3164                 qcom,l1_tlb_dump100 {
3165                         qcom,dump-node = <&L1_TLB_100>;
3166                         qcom,dump-id = <0x24>;
3167                 };
3168                 qcom,l1_tlb_dump101 {
3169                         qcom,dump-node = <&L1_TLB_101>;
3170                         qcom,dump-id = <0x25>;
3171                 };
3172                 qcom,l1_tlb_dump102 {
3173                         qcom,dump-node = <&L1_TLB_102>;
3174                         qcom,dump-id = <0x26>;
3175                 };
3176                 qcom,l1_tlb_dump103 {
3177                         qcom,dump-node = <&L1_TLB_103>;
3178                         qcom,dump-id = <0x27>;
3179                 };
3180         };
3181
3182         ssc_sensors: qcom,msm-ssc-sensors {
3183                 compatible = "qcom,msm-ssc-sensors";
3184                 status = "ok";
3185                 qcom,firmware-name = "slpi_v1";
3186         };
3187
3188         dcc: dcc@10b3000 {
3189                 compatible = "qcom,dcc";
3190                 reg = <0x10b3000 0x1000>,
3191                       <0x10b4000 0x2000>;
3192                 reg-names = "dcc-base", "dcc-ram-base";
3193
3194                 clocks = <&clock_gcc clk_gcc_dcc_ahb_clk>;
3195                 clock-names = "dcc_clk";
3196         };
3197
3198         qcom,msm-core@780000 {
3199                 compatible = "qcom,apss-core-ea";
3200                 reg = <0x780000 0x1000>;
3201                 qcom,low-hyst-temp = <100>;
3202                 qcom,high-hyst-temp = <100>;
3203                 qcom,polling-interval = <50>;
3204
3205                 ea0: ea0 {
3206                         sensor = <&sensor_information1>;
3207                 };
3208
3209                 ea1: ea1 {
3210                         sensor = <&sensor_information2>;
3211                 };
3212
3213                 ea2: ea2 {
3214                         sensor = <&sensor_information3>;
3215                 };
3216
3217                 ea3: ea3 {
3218                         sensor = <&sensor_information4>;
3219                 };
3220
3221                 ea4: ea4 {
3222                         sensor = <&sensor_information7>;
3223                 };
3224
3225                 ea5: ea5 {
3226                         sensor = <&sensor_information8>;
3227                 };
3228
3229                 ea6: ea6 {
3230                         sensor = <&sensor_information9>;
3231                 };
3232
3233                 ea7: ea7 {
3234                         sensor = <&sensor_information10>;
3235                 };
3236
3237         };
3238
3239         msm_ath10k_wlan: qcom,msm_ath10k_wlan {
3240                 status = "disabled";
3241                 compatible = "qcom,wcn3990-wifi";
3242                 reg = <0x18800000 0x800000>;
3243                 reg-names = "membase";
3244                 clocks = <&clock_gcc clk_rf_clk2_pin>;
3245                 clock-names = "cxo_ref_clk_pin";
3246                 interrupts =
3247                         <0 413 0 /* CE0 */ >,
3248                         <0 414 0 /* CE1 */ >,
3249                         <0 415 0 /* CE2 */ >,
3250                         <0 416 0 /* CE3 */ >,
3251                         <0 417 0 /* CE4 */ >,
3252                         <0 418 0 /* CE5 */ >,
3253                         <0 420 0 /* CE6 */ >,
3254                         <0 421 0 /* CE7 */ >,
3255                         <0 422 0 /* CE8 */ >,
3256                         <0 423 0 /* CE9 */ >,
3257                         <0 424 0 /* CE10 */ >,
3258                         <0 425 0 /* CE11 */ >;
3259                 vdd-0.8-cx-mx-supply = <&pm8998_l5>;
3260                 vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>;
3261                 vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>;
3262                 vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>;
3263                 qcom,vdd-0.8-cx-mx-config = <800000 800000>;
3264                 qcom,vdd-3.3-ch0-config = <3104000 3312000>;
3265         };
3266
3267         qcom,icnss@18800000 {
3268                 compatible = "qcom,icnss";
3269                 reg = <0x18800000 0x800000>,
3270                       <0xa0000000 0x10000000>,
3271                       <0xb0000000 0x10000>;
3272                 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
3273                 clocks = <&clock_gcc clk_rf_clk2_pin>;
3274                 clock-names = "cxo_ref_clk_pin";
3275                 iommus = <&anoc2_smmu 0x1900>,
3276                          <&anoc2_smmu 0x1901>;
3277                 interrupts = <0 413 0 /* CE0 */ >,
3278                              <0 414 0 /* CE1 */ >,
3279                              <0 415 0 /* CE2 */ >,
3280                              <0 416 0 /* CE3 */ >,
3281                              <0 417 0 /* CE4 */ >,
3282                              <0 418 0 /* CE5 */ >,
3283                              <0 420 0 /* CE6 */ >,
3284                              <0 421 0 /* CE7 */ >,
3285                              <0 422 0 /* CE8 */ >,
3286                              <0 423 0 /* CE9 */ >,
3287                              <0 424 0 /* CE10 */ >,
3288                              <0 425 0 /* CE11 */ >;
3289                 qcom,wlan-msa-memory = <0x100000>;
3290                 vdd-0.8-cx-mx-supply = <&pm8998_l5>;
3291                 vdd-1.8-xo-supply = <&pm8998_l7_pin_ctrl>;
3292                 vdd-1.3-rfa-supply = <&pm8998_l17_pin_ctrl>;
3293                 vdd-3.3-ch0-supply = <&pm8998_l25_pin_ctrl>;
3294                 qcom,vdd-0.8-cx-mx-config = <800000 800000>;
3295                 qcom,vdd-3.3-ch0-config = <3104000 3312000>;
3296                 qcom,icnss-vadc = <&pm8998_vadc>;
3297                 qcom,icnss-adc_tm = <&pm8998_adc_tm>;
3298         };
3299
3300         tspp: msm_tspp@0c1e7000 {
3301                 compatible = "qcom,msm_tspp";
3302                 reg = <0x0c1e7000 0x200>, /* MSM_TSIF0_PHYS */
3303                       <0x0c1e8000 0x200>, /* MSM_TSIF1_PHYS */
3304                       <0x0c1e9000 0x1000>, /* MSM_TSPP_PHYS  */
3305                       <0x0c1c4000 0x23000>; /* MSM_TSPP_BAM_PHYS */
3306                 reg-names = "MSM_TSIF0_PHYS",
3307                         "MSM_TSIF1_PHYS",
3308                         "MSM_TSPP_PHYS",
3309                         "MSM_TSPP_BAM_PHYS";
3310                 interrupts = <0 121 0>, /* TSIF_TSPP_IRQ */
3311                         <0 119 0>, /* TSIF0_IRQ */
3312                         <0 120 0>, /* TSIF1_IRQ */
3313                         <0 122 0>; /* TSIF_BAM_IRQ */
3314                 interrupt-names = "TSIF_TSPP_IRQ",
3315                         "TSIF0_IRQ",
3316                         "TSIF1_IRQ",
3317                         "TSIF_BAM_IRQ";
3318
3319                 clock-names = "iface_clk", "ref_clk";
3320                 clocks = <&clock_gcc clk_gcc_tsif_ahb_clk>,
3321                         <&clock_gcc clk_gcc_tsif_ref_clk>;
3322
3323                 qcom,msm-bus,name = "tsif";
3324                 qcom,msm-bus,num-cases = <2>;
3325                 qcom,msm-bus,num-paths = <1>;
3326                 qcom,msm-bus,vectors-KBps =
3327                                 <82 512 0 0>, /* No vote */
3328                                 <82 512 12288 24576>;
3329                                 /* Max. bandwidth, 2xTSIF, each max of 96Mbps */
3330
3331                 pinctrl-names = "disabled",
3332                         "tsif0-mode1", "tsif0-mode2",
3333                         "tsif1-mode1", "tsif1-mode2",
3334                         "dual-tsif-mode1", "dual-tsif-mode2";
3335
3336                 pinctrl-0 = <>;                         /* disabled */
3337                 pinctrl-1 = <&tsif0_signals_active>;    /* tsif0-mode1 */
3338                 pinctrl-2 = <&tsif0_signals_active
3339                         &tsif0_sync_active>;            /* tsif0-mode2 */
3340                 pinctrl-3 = <&tsif1_signals_active>;    /* tsif1-mode1 */
3341                 pinctrl-4 = <&tsif1_signals_active
3342                         &tsif1_sync_active>;            /* tsif1-mode2 */
3343                 pinctrl-5 = <&tsif0_signals_active
3344                         &tsif1_signals_active>;         /* dual-tsif-mode1 */
3345                 pinctrl-6 = <&tsif0_signals_active
3346                         &tsif0_sync_active
3347                         &tsif1_signals_active
3348                         &tsif1_sync_active>;            /* dual-tsif-mode2 */
3349         };
3350
3351         wil6210: qcom,wil6210 {
3352                 compatible = "qcom,wil6210";
3353                 qcom,pcie-parent = <&pcie0>;
3354                 qcom,wigig-en = <&tlmm 80 0>;
3355                 qcom,msm-bus,name = "wil6210";
3356                 qcom,msm-bus,num-cases = <2>;
3357                 qcom,msm-bus,num-paths = <1>;
3358                 qcom,msm-bus,vectors-KBps =
3359                         <45 512 0 0>,
3360                         <45 512 600000 800000>; /* ~4.6Gbps (MCS12) */
3361                 qcom,use-ext-supply;
3362                 vdd-supply= <&pm8998_s7>;
3363                 vddio-supply= <&pm8998_s5>;
3364                 qcom,use-ext-clocks;
3365                 clocks = <&clock_gcc clk_rf_clk3>,
3366                          <&clock_gcc clk_rf_clk3_pin>;
3367                 clock-names = "rf_clk3_clk", "rf_clk3_pin_clk";
3368                 qcom,smmu-support;
3369                 qcom,smmu-s1-en;
3370                 qcom,smmu-fast-map;
3371                 qcom,smmu-coherent;
3372                 qcom,smmu-mapping = <0x20000000 0xe0000000>;
3373                 qcom,keep-radio-on-during-sleep;
3374                 status = "disabled";
3375         };
3376
3377         qcom,qsee_ipc_irq_bridge {
3378                 compatible = "qcom,qsee-ipc-irq-bridge";
3379
3380                 qcom,qsee-ipc-irq-spss {
3381                         qcom,rx-irq-clr = <0x1d08008 0x4>;
3382                         qcom,rx-irq-clr-mask = <0x1>;
3383                         qcom,dev-name = "qsee_ipc_irq_spss";
3384                         interrupts = <0 349 4>;
3385                         label = "spss";
3386                 };
3387         };
3388 };
3389
3390 &clock_cpu {
3391         lmh_dcvs0: qcom,limits-dcvs@0 {
3392                 compatible = "qcom,msm-hw-limits";
3393                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
3394         };
3395
3396         lmh_dcvs1: qcom,limits-dcvs@1 {
3397                 compatible = "qcom,msm-hw-limits";
3398                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
3399         };
3400 };
3401
3402 &gdsc_usb30 {
3403         status = "ok";
3404 };
3405
3406 &gdsc_pcie_0 {
3407         status = "ok";
3408 };
3409
3410 &gdsc_ufs {
3411         status = "ok";
3412 };
3413
3414 &gdsc_bimc_smmu {
3415         clock-names = "bus_clk";
3416         clocks = <&clock_mmss clk_mmss_bimc_smmu_axi_clk>;
3417         proxy-supply = <&gdsc_bimc_smmu>;
3418         qcom,proxy-consumer-enable;
3419         status = "ok";
3420 };
3421
3422 &gdsc_hlos1_vote_lpass_adsp {
3423         status = "ok";
3424 };
3425
3426 &gdsc_hlos1_vote_lpass_core {
3427         status = "ok";
3428 };
3429
3430 &gdsc_venus {
3431         status = "ok";
3432 };
3433
3434 &gdsc_venus_core0 {
3435         status = "ok";
3436         qcom,support-hw-trigger;
3437 };
3438
3439 &gdsc_venus_core1 {
3440         status = "ok";
3441         qcom,support-hw-trigger;
3442 };
3443
3444 &gdsc_camss_top {
3445         status = "ok";
3446 };
3447
3448 &gdsc_vfe0 {
3449         parent-supply = <&gdsc_camss_top>;
3450         status = "ok";
3451 };
3452
3453 &gdsc_vfe1 {
3454         parent-supply = <&gdsc_camss_top>;
3455         status = "ok";
3456 };
3457
3458 &gdsc_cpp {
3459         parent-supply = <&gdsc_camss_top>;
3460         qcom,support-hw-trigger;
3461         status = "ok";
3462 };
3463
3464 &gdsc_mdss {
3465         proxy-supply = <&gdsc_mdss>;
3466         qcom,proxy-consumer-enable;
3467         status = "ok";
3468 };
3469
3470 &gdsc_gpu_gx {
3471         clock-names = "core_root_clk";
3472         clocks = <&clock_gfx clk_gfx3d_clk_src>;
3473         qcom,force-enable-root-clk;
3474         parent-supply = <&gfx_vreg>;
3475         status = "ok";
3476 };
3477
3478 &gdsc_gpu_cx {
3479         status = "ok";
3480 };
3481
3482 #include "msm-pm8998.dtsi"
3483 #include "msm-pmi8998.dtsi"
3484 #include "msm-pm8005.dtsi"
3485 #include "msm-pm8998-rpm-regulator.dtsi"
3486 #include "msm8998-regulator.dtsi"
3487
3488 #include "msm8998-pm.dtsi"
3489 #include "msm-arm-smmu-8998.dtsi"
3490 #include "msm-arm-smmu-impl-defs-8998.dtsi"
3491 #include "msm8998-ion.dtsi"
3492 #include "msm8998-camera.dtsi"
3493 #include "msm8998-vidc.dtsi"
3494 #include "msm8998-coresight.dtsi"
3495 #include "msm8998-bus.dtsi"
3496 #include "msm8998-gpu.dtsi"
3497 #include "msm8998-pinctrl.dtsi"
3498 #include "msm-audio-lpass.dtsi"
3499 #include "msm8998-mdss.dtsi"
3500 #include "msm8998-mdss-pll.dtsi"
3501 #include "msm-rdbg.dtsi"
3502 #include "msm8998-blsp.dtsi"
3503 #include "msm8998-audio.dtsi"
3504 #include "msm-smb138x.dtsi"
3505 #include "msm8998-sde.dtsi"