arch/arm/boot/dts/qcom/sdm660.dtsi

   1 /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include "skeleton64.dtsi"
  14 #include <dt-bindings/clock/qcom,gcc-sdm660.h>
  15 #include <dt-bindings/clock/qcom,gpu-sdm660.h>
  16 #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
  17 #include <dt-bindings/clock/qcom,rpmcc.h>
  18 #include <dt-bindings/clock/audio-ext-clk.h>
  19 #include <dt-bindings/interrupt-controller/arm-gic.h>
  20 #include <dt-bindings/regulator/qcom,rpm-smd-regulator.h>
  21 #include <dt-bindings/clock/qcom,cpu-osm.h>
  22
  23 / {
  24         model = "Qualcomm Technologies, Inc. SDM 660";
  25         compatible = "qcom,sdm660";
  26         qcom,msm-id = <317 0x0>;
  27         interrupt-parent = <&intc>;
  28
  29         aliases {
  30                 serial0 = &uartblsp1dm1;
  31                 sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
  32                 sdhc2 = &sdhc_2; /* SDC2 for SD card */
  33         };
  34
  35         chosen {
  36                 stdout-path = "serial0";
  37                 bootargs = "rcupdate.rcu_expedited=1";
  38         };
  39
  40         psci {
  41                 compatible = "arm,psci-1.0";
  42                 method = "smc";
  43         };
  44
  45         cpus {
  46                 #address-cells = <2>;
  47                 #size-cells = <0>;
  48
  49                 CPU0: cpu@0 {
  50                         device_type = "cpu";
  51                         compatible = "arm,armv8";
  52                         reg = <0x0 0x0>;
  53                         enable-method = "psci";
  54                         qcom,limits-info = <&mitigation_profile0>;
  55                         qcom,lmh-dcvs = <&lmh_dcvs0>;
  56                         qcom,ea = <&ea0>;
  57                         efficiency = <1024>;
  58                         next-level-cache = <&L2_0>;
  59                         L2_0: l2-cache {
  60                                 compatible = "arm,arch-cache";
  61                                 cache-level = <2>;
  62                                 /* A53 L2 dump not supported */
  63                                 qcom,dump-size = <0x0>;
  64                         };
  65                         L1_I_0: l1-icache {
  66                                 compatible = "arm,arch-cache";
  67                                 qcom,dump-size = <0x9040>;
  68                         };
  69                         L1_D_0: l1-dcache {
  70                                 compatible = "arm,arch-cache";
  71                                 qcom,dump-size = <0x9040>;
  72                         };
  73                         L1_TLB_0: l1-tlb {
  74                                 qcom,dump-size = <0x2800>;
  75                         };
  76                 };
  77
  78                 CPU1: cpu@1 {
  79                         device_type = "cpu";
  80                         compatible = "arm,armv8";
  81                         reg = <0x0 0x1>;
  82                         enable-method = "psci";
  83                         qcom,limits-info = <&mitigation_profile0>;
  84                         qcom,lmh-dcvs = <&lmh_dcvs0>;
  85                         qcom,ea = <&ea1>;
  86                         efficiency = <1024>;
  87                         next-level-cache = <&L2_0>;
  88                         L1_I_1: l1-icache {
  89                                 compatible = "arm,arch-cache";
  90                                 qcom,dump-size = <0x9040>;
  91                         };
  92                         L1_D_1: l1-dcache {
  93                                 compatible = "arm,arch-cache";
  94                                 qcom,dump-size = <0x9040>;
  95                         };
  96                         L1_TLB_1: l1-tlb {
  97                                 qcom,dump-size = <0x2800>;
  98                         };
  99                 };
 100
 101                 CPU2: cpu@2 {
 102                         device_type = "cpu";
 103                         compatible = "arm,armv8";
 104                         reg = <0x0 0x2>;
 105                         enable-method = "psci";
 106                         qcom,limits-info = <&mitigation_profile0>;
 107                         qcom,lmh-dcvs = <&lmh_dcvs0>;
 108                         qcom,ea = <&ea2>;
 109                         efficiency = <1024>;
 110                         next-level-cache = <&L2_0>;
 111                         L1_I_2: l1-icache {
 112                                 compatible = "arm,arch-cache";
 113                                 qcom,dump-size = <0x9040>;
 114                         };
 115                         L1_D_2: l1-dcache {
 116                                 compatible = "arm,arch-cache";
 117                                 qcom,dump-size = <0x9040>;
 118                         };
 119                         L1_TLB_2: l1-tlb {
 120                                 qcom,dump-size = <0x2800>;
 121                         };
 122                 };
 123
 124                 CPU3: cpu@3 {
 125                         device_type = "cpu";
 126                         compatible = "arm,armv8";
 127                         reg = <0x0 0x3>;
 128                         enable-method = "psci";
 129                         qcom,limits-info = <&mitigation_profile0>;
 130                         qcom,lmh-dcvs = <&lmh_dcvs0>;
 131                         qcom,ea = <&ea3>;
 132                         efficiency = <1024>;
 133                         next-level-cache = <&L2_0>;
 134                         L1_I_3: l1-icache {
 135                                 compatible = "arm,arch-cache";
 136                                 qcom,dump-size = <0x9040>;
 137                         };
 138                         L1_D_3: l1-dcache {
 139                                 compatible = "arm,arch-cache";
 140                                 qcom,dump-size = <0x9040>;
 141                         };
 142                         L1_TLB_3: l1-tlb {
 143                                 qcom,dump-size = <0x2800>;
 144                         };
 145                 };
 146
 147                 CPU4: cpu@100 {
 148                         device_type = "cpu";
 149                         compatible = "arm,armv8";
 150                         reg = <0x0 0x100>;
 151                         enable-method = "psci";
 152                         qcom,limits-info = <&mitigation_profile1>;
 153                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 154                         qcom,ea = <&ea4>;
 155                         efficiency = <1638>;
 156                         next-level-cache = <&L2_1>;
 157                         L2_1: l2-cache {
 158                                 compatible = "arm,arch-cache";
 159                                 cache-level = <2>;
 160                         };
 161                         L1_I_100: l1-icache {
 162                                 compatible = "arm,arch-cache";
 163                                 qcom,dump-size = <0x12000>;
 164                         };
 165                         L1_D_100: l1-dcache {
 166                                 compatible = "arm,arch-cache";
 167                                 qcom,dump-size = <0x12000>;
 168                         };
 169                         L1_TLB_100: l1-tlb {
 170                                 qcom,dump-size = <0x4800>;
 171                         };
 172                 };
 173
 174                 CPU5: cpu@101 {
 175                         device_type = "cpu";
 176                         compatible = "arm,armv8";
 177                         reg = <0x0 0x101>;
 178                         enable-method = "psci";
 179                         qcom,limits-info = <&mitigation_profile2>;
 180                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 181                         qcom,ea = <&ea5>;
 182                         efficiency = <1638>;
 183                         next-level-cache = <&L2_1>;
 184                         L1_I_101: l1-icache {
 185                                 compatible = "arm,arch-cache";
 186                                 qcom,dump-size = <0x12000>;
 187                         };
 188                         L1_D_101: l1-dcache {
 189                                 compatible = "arm,arch-cache";
 190                                 qcom,dump-size = <0x12000>;
 191                         };
 192                         L1_TLB_101: l1-tlb {
 193                                 qcom,dump-size = <0x4800>;
 194                         };
 195                 };
 196
 197                 CPU6: cpu@102 {
 198                         device_type = "cpu";
 199                         compatible = "arm,armv8";
 200                         reg = <0x0 0x102>;
 201                         enable-method = "psci";
 202                         qcom,limits-info = <&mitigation_profile3>;
 203                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 204                         qcom,ea = <&ea6>;
 205                         efficiency = <1638>;
 206                         next-level-cache = <&L2_1>;
 207                         L1_I_102: l1-icache {
 208                                 compatible = "arm,arch-cache";
 209                                 qcom,dump-size = <0x12000>;
 210                         };
 211                         L1_D_102: l1-dcache {
 212                                 compatible = "arm,arch-cache";
 213                                 qcom,dump-size = <0x12000>;
 214                         };
 215                         L1_TLB_102: l1-tlb {
 216                                 qcom,dump-size = <0x4800>;
 217                         };
 218                 };
 219
 220                 CPU7: cpu@103 {
 221                         device_type = "cpu";
 222                         compatible = "arm,armv8";
 223                         reg = <0x0 0x103>;
 224                         enable-method = "psci";
 225                         qcom,limits-info = <&mitigation_profile4>;
 226                         qcom,lmh-dcvs = <&lmh_dcvs1>;
 227                         qcom,ea = <&ea7>;
 228                         efficiency = <1638>;
 229                         next-level-cache = <&L2_1>;
 230                         L1_I_103: l1-icache {
 231                                 compatible = "arm,arch-cache";
 232                                 qcom,dump-size = <0x12000>;
 233                         };
 234                         L1_D_103: l1-dcache {
 235                                 compatible = "arm,arch-cache";
 236                                 qcom,dump-size = <0x12000>;
 237                         };
 238                         L1_TLB_103: l1-tlb {
 239                                 qcom,dump-size = <0x4800>;
 240                         };
 241                 };
 242
 243                 cpu-map {
 244                         cluster0 {
 245                                 core0 {
 246                                         cpu = <&CPU0>;
 247                                 };
 248
 249                                 core1 {
 250                                         cpu = <&CPU1>;
 251                                 };
 252
 253                                 core2 {
 254                                         cpu = <&CPU2>;
 255                                 };
 256
 257                                 core3 {
 258                                         cpu = <&CPU3>;
 259                                 };
 260                         };
 261
 262                         cluster1 {
 263                                 core0 {
 264                                         cpu = <&CPU4>;
 265                                 };
 266
 267                                 core1 {
 268                                         cpu = <&CPU5>;
 269                                 };
 270
 271                                 core2 {
 272                                         cpu = <&CPU6>;
 273                                 };
 274
 275                                 core3 {
 276                                         cpu = <&CPU7>;
 277                                 };
 278                         };
 279                 };
 280         };
 281
 282         clocks {
 283                 xo_board {
 284                         compatible = "fixed-clock";
 285                         #clock-cells = <0>;
 286                         clock-frequency = <19200000>;
 287                         clock-output-names = "xo_board";
 288                 };
 289
 290                 sleep_clk {
 291                         compatible = "fixed-clock";
 292                         #clock-cells = <0>;
 293                         clock-frequency = <32764>;
 294                         clock-output-names = "sleep_clk";
 295                 };
 296         };
 297
 298         soc: soc { };
 299
 300         firmware: firmware {
 301                 android {
 302                         compatible = "android,firmware";
 303                         fstab {
 304                                 compatible = "android,fstab";
 305                                 vendor {
 306                                         compatible = "android,vendor";
 307                                         dev = "/dev/block/platform/soc/c0c4000.sdhci/by-name/vendor";
 308                                         type = "ext4";
 309                                         mnt_flags = "ro,barrier=1,discard";
 310                                         fsmgr_flags = "wait,slotselect,verify";
 311                                         status = "ok";
 312                                 };
 313                         };
 314                 };
 315         };
 316
 317         reserved-memory {
 318                 #address-cells = <2>;
 319                 #size-cells = <2>;
 320                 ranges;
 321
 322                 wlan_msa_guard: wlan_msa_guard@85600000 {
 323                         compatible = "removed-dma-pool";
 324                         no-map;
 325                         reg = <0x0 0x85600000 0x0 0x100000>;
 326                 };
 327
 328                 wlan_msa_mem: wlan_msa_mem@85700000 {
 329                         compatible = "removed-dma-pool";
 330                         no-map;
 331                         reg = <0x0 0x85700000 0x0 0x100000>;
 332                 };
 333
 334                 removed_regions: removed_regions@85800000 {
 335                         compatible = "removed-dma-pool";
 336                         no-map;
 337                         reg = <0x0 0x85800000 0x0 0x3700000>;
 338                 };
 339
 340                 modem_fw_mem: modem_fw_region@8ac00000 {
 341                         compatible = "removed-dma-pool";
 342                         no-map;
 343                         reg = <0x0 0x8ac00000 0x0 0x7e00000>;
 344                 };
 345
 346                 adsp_fw_mem: adsp_fw_region@92a00000 {
 347                         compatible = "removed-dma-pool";
 348                         no-map;
 349                         reg = <0x0 0x92a00000 0x0 0x1e00000>;
 350                 };
 351
 352                 pil_mba_mem: pil_mba_region@94800000 {
 353                         compatible = "removed-dma-pool";
 354                         no-map;
 355                         reg = <0x0 0x94800000 0x0 0x200000>;
 356                 };
 357
 358                 cdsp_fw_mem: cdsp_fw_region@94a00000 {
 359                         compatible = "removed-dma-pool";
 360                         no-map;
 361                         reg = <0x0 0x94a00000 0x0 0x600000>;
 362                 };
 363
 364                 venus_fw_mem: venus_fw_region {
 365                         compatible = "shared-dma-pool";
 366                         alloc-ranges = <0x0 0x80000000 0x0 0x20000000>;
 367                         reusable;
 368                         alignment = <0x0 0x400000>;
 369                         size = <0x0 0x800000>;
 370                 };
 371
 372                 adsp_mem: adsp_region {
 373                         compatible = "shared-dma-pool";
 374                         alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 375                         reusable;
 376                         alignment = <0x0 0x400000>;
 377                         size = <0x0 0x800000>;
 378                 };
 379
 380                 qseecom_mem: qseecom_region {
 381                         compatible = "shared-dma-pool";
 382                         alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 383                         reusable;
 384                         alignment = <0x0 0x400000>;
 385                         size = <0x0 0x1400000>;
 386                 };
 387
 388                 secure_display_memory: secure_region {
 389                         compatible = "shared-dma-pool";
 390                         alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
 391                         reusable;
 392                         alignment = <0x0 0x400000>;
 393                         size = <0x0 0x5c00000>;
 394                 };
 395
 396                 /* global autoconfigured region for contiguous allocations */
 397                 linux,cma {
 398                         compatible = "shared-dma-pool";
 399                         alloc-ranges = <0 0x00000000 0 0xffffffff>;
 400                         reusable;
 401                         alignment = <0 0x400000>;
 402                         size = <0 0x2c00000>;
 403                         linux,cma-default;
 404                 };
 405
 406                 cont_splash_mem: splash_region@9d400000 {
 407                         reg = <0x0 0x9d400000 0x0 0x02400000>;
 408                         label = "cont_splash_mem";
 409                 };
 410         };
 411
 412         bluetooth: bt_wcn3990 {
 413                 compatible = "qca,wcn3990";
 414                 qca,bt-vdd-core-supply = <&pm660_l9>;
 415                 qca,bt-vdd-pa-supply = <&pm660_l6>;
 416                 qca,bt-vdd-ldo-supply = <&pm660_l19>;
 417                 qca,bt-chip-pwd-supply = <&pm660l_bob_pin1>;
 418                 clocks = <&clock_rpmcc RPM_RF_CLK1_PIN>;
 419                 clock-names = "rf_clk1";
 420
 421                 qca,bt-vdd-core-voltage-level = <1800000 1900000>;
 422                 qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
 423                 qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
 424                 qca,bt-chip-pwd-voltage-level = <3600000 3600000>;
 425
 426                 qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
 427                 qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
 428                 qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
 429         };
 430 };
 431
 432 #include "sdm660-smp2p.dtsi"
 433 #include "sdm660-coresight.dtsi"
 434 &soc {
 435         #address-cells = <1>;
 436         #size-cells = <1>;
 437         ranges = <0 0 0 0xffffffff>;
 438         compatible = "simple-bus";
 439
 440         intc: interrupt-controller@17a00000 {
 441                 compatible = "arm,gic-v3";
 442                 reg = <0x17a00000 0x10000>,       /* GICD */
 443                       <0x17b00000 0x100000>;      /* GICR * 8 */
 444                 #interrupt-cells = <3>;
 445                 #address-cells = <1>;
 446                 #size-cells = <1>;
 447                 ranges;
 448                 interrupt-controller;
 449                 #redistributor-regions = <1>;
 450                 redistributor-stride = <0x0 0x20000>;
 451                 interrupts = <1 9 4>;
 452         };
 453
 454         timer {
 455                 compatible = "arm,armv8-timer";
 456                 interrupts = <1 1 0xf08>,
 457                              <1 2 0xf08>,
 458                              <1 3 0xf08>,
 459                              <1 0 0xf08>;
 460                 clock-frequency = <19200000>;
 461         };
 462
 463         dma_blsp1: qcom,sps-dma@0xc144000{ /* BLSP1 */
 464                 #dma-cells = <4>;
 465                 compatible = "qcom,sps-dma";
 466                 reg = <0xc144000 0x1F000>;
 467                 interrupts = <0 238 0>;
 468                 qcom,summing-threshold = <0x10>;
 469         };
 470
 471         dma_blsp2: qcom,sps-dma@0xc184000{ /* BLSP2 */
 472                 #dma-cells = <4>;
 473                 compatible = "qcom,sps-dma";
 474                 reg = <0xc184000 0x1F000>;
 475                 interrupts = <0 239 0>;
 476                 qcom,summing-threshold = <0x10>;
 477         };
 478
 479         restart@10ac000 {
 480                 compatible = "qcom,pshold";
 481                 reg = <0x10ac000 0x4>,
 482                       <0x1fd3000 0x4>;
 483                 reg-names = "pshold-base", "tcsr-boot-misc-detect";
 484         };
 485
 486         spmi_bus: qcom,spmi@800f000 {
 487                 compatible = "qcom,spmi-pmic-arb";
 488                 reg = <0x800f000 0x1000>,
 489                         <0x8400000 0x1000000>,
 490                         <0x9400000 0x1000000>,
 491                         <0xa400000 0x220000>,
 492                         <0x800a000 0x3000>;
 493                 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 494                 interrupt-names = "periph_irq";
 495                 interrupts = <GIC_SPI 326 IRQ_TYPE_NONE>;
 496                 qcom,ee = <0>;
 497                 qcom,channel = <0>;
 498                 qcom,reserved-chan = <511>;
 499                 #address-cells = <2>;
 500                 #size-cells = <0>;
 501                 interrupt-controller;
 502                 #interrupt-cells = <4>;
 503                 cell-index = <0>;
 504                 status = "ok";
 505         };
 506
 507         cpuss_dump {
 508                 compatible = "qcom,cpuss-dump";
 509                 qcom,l1_i_cache0 {
 510                         qcom,dump-node = <&L1_I_0>;
 511                         qcom,dump-id = <0x60>;
 512                 };
 513                 qcom,l1_i_cache1 {
 514                         qcom,dump-node = <&L1_I_1>;
 515                         qcom,dump-id = <0x61>;
 516                 };
 517                 qcom,l1_i_cache2 {
 518                         qcom,dump-node = <&L1_I_2>;
 519                         qcom,dump-id = <0x62>;
 520                 };
 521                 qcom,l1_i_cache3 {
 522                         qcom,dump-node = <&L1_I_3>;
 523                         qcom,dump-id = <0x63>;
 524                 };
 525                 qcom,l1_i_cache100 {
 526                         qcom,dump-node = <&L1_I_100>;
 527                         qcom,dump-id = <0x64>;
 528                 };
 529                 qcom,l1_i_cache101 {
 530                         qcom,dump-node = <&L1_I_101>;
 531                         qcom,dump-id = <0x65>;
 532                 };
 533                 qcom,l1_i_cache102 {
 534                         qcom,dump-node = <&L1_I_102>;
 535                         qcom,dump-id = <0x66>;
 536                 };
 537                 qcom,l1_i_cache103 {
 538                         qcom,dump-node = <&L1_I_103>;
 539                         qcom,dump-id = <0x67>;
 540                 };
 541                 qcom,l1_d_cache0 {
 542                         qcom,dump-node = <&L1_D_0>;
 543                         qcom,dump-id = <0x80>;
 544                 };
 545                 qcom,l1_d_cache1 {
 546                         qcom,dump-node = <&L1_D_1>;
 547                         qcom,dump-id = <0x81>;
 548                 };
 549                 qcom,l1_d_cache2 {
 550                         qcom,dump-node = <&L1_D_2>;
 551                         qcom,dump-id = <0x82>;
 552                 };
 553                 qcom,l1_d_cache3 {
 554                         qcom,dump-node = <&L1_D_3>;
 555                         qcom,dump-id = <0x83>;
 556                 };
 557                 qcom,l1_d_cache100 {
 558                         qcom,dump-node = <&L1_D_100>;
 559                         qcom,dump-id = <0x84>;
 560                 };
 561                 qcom,l1_d_cache101 {
 562                         qcom,dump-node = <&L1_D_101>;
 563                         qcom,dump-id = <0x85>;
 564                 };
 565                 qcom,l1_d_cache102 {
 566                         qcom,dump-node = <&L1_D_102>;
 567                         qcom,dump-id = <0x86>;
 568                 };
 569                 qcom,l1_d_cache103 {
 570                         qcom,dump-node = <&L1_D_103>;
 571                         qcom,dump-id = <0x87>;
 572                 };
 573                 qcom,l1_tlb_dump0 {
 574                         qcom,dump-node = <&L1_TLB_0>;
 575                         qcom,dump-id = <0x20>;
 576                 };
 577                 qcom,l1_tlb_dump1 {
 578                         qcom,dump-node = <&L1_TLB_1>;
 579                         qcom,dump-id = <0x21>;
 580                 };
 581                 qcom,l1_tlb_dump2 {
 582                         qcom,dump-node = <&L1_TLB_2>;
 583                         qcom,dump-id = <0x22>;
 584                 };
 585                 qcom,l1_tlb_dump3 {
 586                         qcom,dump-node = <&L1_TLB_3>;
 587                         qcom,dump-id = <0x23>;
 588                 };
 589                 qcom,l1_tlb_dump100 {
 590                         qcom,dump-node = <&L1_TLB_100>;
 591                         qcom,dump-id = <0x24>;
 592                 };
 593                 qcom,l1_tlb_dump101 {
 594                         qcom,dump-node = <&L1_TLB_101>;
 595                         qcom,dump-id = <0x25>;
 596                 };
 597                 qcom,l1_tlb_dump102 {
 598                         qcom,dump-node = <&L1_TLB_102>;
 599                         qcom,dump-id = <0x26>;
 600                 };
 601                 qcom,l1_tlb_dump103 {
 602                         qcom,dump-node = <&L1_TLB_103>;
 603                         qcom,dump-id = <0x27>;
 604                 };
 605         };
 606
 607         wdog: qcom,wdt@17817000 {
 608                 compatible = "qcom,msm-watchdog";
 609                 reg = <0x17817000 0x1000>;
 610                 reg-names = "wdt-base";
 611                 interrupts = <0 3 0>, <0 4 0>;
 612                 qcom,bark-time = <11000>;
 613                 qcom,pet-time = <10000>;
 614                 qcom,ipi-ping;
 615                 qcom,wakeup-enable;
 616                 qcom,scandump-size = <0x40000>;
 617         };
 618
 619         qcom,sps {
 620                 compatible = "qcom,msm_sps_4k";
 621                 qcom,pipe-attr-ee;
 622         };
 623
 624         qcom,memshare {
 625                 compatible = "qcom,memshare";
 626
 627                 qcom,client_1 {
 628                         compatible = "qcom,memshare-peripheral";
 629                         qcom,peripheral-size = <0x200000>;
 630                         qcom,client-id = <0>;
 631                         qcom,allocate-boot-time;
 632                         label = "modem";
 633                 };
 634
 635                 qcom,client_2 {
 636                         compatible = "qcom,memshare-peripheral";
 637                         qcom,peripheral-size = <0x300000>;
 638                         qcom,client-id = <2>;
 639                         label = "modem";
 640                 };
 641
 642                 mem_client_3_size: qcom,client_3 {
 643                         compatible = "qcom,memshare-peripheral";
 644                         qcom,peripheral-size = <0x0>;
 645                         qcom,client-id = <1>;
 646                         qcom,allocate-boot-time;
 647                         label = "modem";
 648                 };
 649         };
 650
 651         tsens: tsens@10ad000 {
 652                 compatible = "qcom,sdm660-tsens";
 653                 reg = <0x10ad000 0x2000>,
 654                         <0x784240 0x1000>;
 655                 reg-names = "tsens_physical", "tsens_eeprom_physical";
 656                 interrupts = <0 184 0>, <0 430 0>;
 657                 interrupt-names = "tsens-upper-lower", "tsens-critical";
 658                 qcom,client-id = <0 1 2 3 4 5 6 7 8 9 10 11 12 13>;
 659                 qcom,sensor-id = <0 10 11 4 5 6 7 8 13 2 3 12 9 1>;
 660                 qcom,sensors = <14>;
 661                 qcom,slope = <3200 3200 3200 3200 3200 3200 3200 3200
 662                                         3200 3200 3200 3200 3200 3200>;
 663         };
 664
 665         uartblsp1dm1: serial@0c170000 {
 666                 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 667                 reg = <0xc170000 0x1000>;
 668                 interrupts = <0 108 0>;
 669                 status = "disabled";
 670                 clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
 671                          <&clock_gcc GCC_BLSP1_AHB_CLK>;
 672                 clock-names = "core", "iface";
 673         };
 674
 675         qcom,qbt1000 {
 676                 compatible = "qcom,qbt1000";
 677                 clock-names = "core", "iface";
 678                 clocks = <&clock_gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
 679                         <&clock_gcc GCC_BLSP1_AHB_CLK>;
 680                 clock-frequency = <15000000>;
 681                 qcom,ipc-gpio = <&tlmm 72 0>;
 682                 qcom,finger-detect-gpio = <&pm660_gpios 11 0>;
 683         };
 684
 685         qcom,sensor-information {
 686                 compatible = "qcom,sensor-information";
 687                 sensor_information0: qcom,sensor-information-0 {
 688                         qcom,sensor-type = "tsens";
 689                         qcom,sensor-name = "tsens_tz_sensor0";
 690                         qcom,scaling-factor = <10>;
 691                 };
 692                 sensor_information1: qcom,sensor-information-1 {
 693                         qcom,sensor-type =  "tsens";
 694                         qcom,sensor-name = "tsens_tz_sensor1";
 695                         qcom,scaling-factor = <10>;
 696                 };
 697                 sensor_information2: qcom,sensor-information-2 {
 698                         qcom,sensor-type =  "tsens";
 699                         qcom,sensor-name = "tsens_tz_sensor2";
 700                         qcom,scaling-factor = <10>;
 701                 };
 702                 sensor_information3: qcom,sensor-information-3 {
 703                         qcom,sensor-type =  "tsens";
 704                         qcom,sensor-name = "tsens_tz_sensor3";
 705                         qcom,scaling-factor = <10>;
 706                 };
 707                 sensor_information4: qcom,sensor-information-4 {
 708                         qcom,sensor-type = "tsens";
 709                         qcom,sensor-name = "tsens_tz_sensor4";
 710                         qcom,scaling-factor = <10>;
 711                 };
 712                 sensor_information5: qcom,sensor-information-5 {
 713                         qcom,sensor-type = "tsens";
 714                         qcom,sensor-name = "tsens_tz_sensor5";
 715                         qcom,scaling-factor = <10>;
 716                 };
 717                 sensor_information6: qcom,sensor-information-6 {
 718                         qcom,sensor-type = "tsens";
 719                         qcom,sensor-name = "tsens_tz_sensor6";
 720                         qcom,scaling-factor = <10>;
 721                 };
 722                 sensor_information7: qcom,sensor-information-7 {
 723                         qcom,sensor-type = "tsens";
 724                         qcom,sensor-name = "tsens_tz_sensor7";
 725                         qcom,scaling-factor = <10>;
 726                 };
 727                 sensor_information8: qcom,sensor-information-8 {
 728                         qcom,sensor-type = "tsens";
 729                         qcom,sensor-name = "tsens_tz_sensor8";
 730                         qcom,scaling-factor = <10>;
 731                         qcom,alias-name = "gpu";
 732                 };
 733                 sensor_information9: qcom,sensor-information-9 {
 734                         qcom,sensor-type = "tsens";
 735                         qcom,sensor-name = "tsens_tz_sensor9";
 736                         qcom,scaling-factor = <10>;
 737                 };
 738                 sensor_information10: qcom,sensor-information-10 {
 739                         qcom,sensor-type = "tsens";
 740                         qcom,sensor-name = "tsens_tz_sensor10";
 741                         qcom,scaling-factor = <10>;
 742                 };
 743                 sensor_information11: qcom,sensor-information-11 {
 744                         qcom,sensor-type = "tsens";
 745                         qcom,sensor-name = "tsens_tz_sensor11";
 746                         qcom,scaling-factor = <10>;
 747                 };
 748                 sensor_information12: qcom,sensor-information-12 {
 749                         qcom,sensor-type = "tsens";
 750                         qcom,sensor-name = "tsens_tz_sensor12";
 751                         qcom,scaling-factor = <10>;
 752                 };
 753                 sensor_information13: qcom,sensor-information-13 {
 754                         qcom,sensor-type = "tsens";
 755                         qcom,sensor-name = "tsens_tz_sensor13";
 756                         qcom,scaling-factor = <10>;
 757                 };
 758                 sensor_information14: qcom,sensor-information-14 {
 759                         qcom,sensor-type =  "alarm";
 760                         qcom,sensor-name = "pm660_tz";
 761                         qcom,scaling-factor = <1000>;
 762                 };
 763                 sensor_information15: qcom,sensor-information-15 {
 764                         qcom,sensor-type =  "adc";
 765                         qcom,sensor-name = "msm_therm";
 766                 };
 767                 sensor_information16: qcom,sensor-information-16 {
 768                         qcom,sensor-type =  "adc";
 769                         qcom,sensor-name = "xo_therm";
 770                 };
 771                 sensor_information17: qcom,sensor-information-17 {
 772                         qcom,sensor-type =  "adc";
 773                         qcom,sensor-name = "pa_therm0";
 774                 };
 775                 sensor_information18: qcom,sensor-information-18 {
 776                         qcom,sensor-type =  "adc";
 777                         qcom,sensor-name = "pa_therm1";
 778                 };
 779                 sensor_information19: qcom,sensor-information-19 {
 780                         qcom,sensor-type =  "adc";
 781                         qcom,sensor-name = "quiet_therm";
 782                 };
 783                 sensor_information20: qcom,sensor-information-20 {
 784                         qcom,sensor-type = "llm";
 785                         qcom,sensor-name = "limits_sensor-00";
 786                 };
 787                 sensor_information21: qcom,sensor-information-21 {
 788                         qcom,sensor-type = "llm";
 789                         qcom,sensor-name = "limits_sensor-01";
 790                 };
 791         };
 792
 793         mitigation_profile0: qcom,limit_info-0 {
 794                 qcom,temperature-sensor = <&sensor_information1>;
 795                 qcom,hotplug-mitigation-enable;
 796         };
 797
 798         mitigation_profile1: qcom,limit_info-1 {
 799                 qcom,temperature-sensor = <&sensor_information3>;
 800                 qcom,hotplug-mitigation-enable;
 801         };
 802
 803         mitigation_profile2: qcom,limit_info-2 {
 804                 qcom,temperature-sensor = <&sensor_information4>;
 805                 qcom,hotplug-mitigation-enable;
 806         };
 807
 808         mitigation_profile3: qcom,limit_info-3 {
 809                 qcom,temperature-sensor = <&sensor_information5>;
 810                 qcom,hotplug-mitigation-enable;
 811         };
 812
 813         mitigation_profile4: qcom,limit_info-4 {
 814                 qcom,temperature-sensor = <&sensor_information6>;
 815                 qcom,hotplug-mitigation-enable;
 816         };
 817
 818         qcom,msm-thermal {
 819                 compatible = "qcom,msm-thermal";
 820                 qcom,sensor-id = <1>;
 821                 qcom,poll-ms = <100>;
 822                 qcom,therm-reset-temp = <115>;
 823                 qcom,core-limit-temp = <70>;
 824                 qcom,core-temp-hysteresis = <10>;
 825                 qcom,hotplug-temp = <105>;
 826                 qcom,hotplug-temp-hysteresis = <20>;
 827                 qcom,online-hotplug-core;
 828                 qcom,synchronous-cluster-id = <0 1>;
 829                 qcom,synchronous-cluster-map = <0 4 &CPU0 &CPU1 &CPU2 &CPU3>,
 830                                                 <1 4 &CPU4 &CPU5 &CPU6 &CPU7>;
 831
 832                 clock-names = "osm";
 833                 clocks = <&clock_cpu PWRCL_CLK>;
 834                 qcom,cxip-lm-enable = <1>;
 835                 qcom,vdd-restriction-temp = <5>;
 836                 qcom,vdd-restriction-temp-hysteresis = <10>;
 837
 838                 vdd-dig-supply = <&pm660l_s3_floor_level>;
 839                 vdd-gfx-supply = <&gfx_vreg_corner>;
 840
 841                 qcom,vdd-dig-rstr{
 842                         qcom,vdd-rstr-reg = "vdd-dig";
 843                         qcom,levels = <RPM_SMD_REGULATOR_LEVEL_NOM
 844                                         RPM_SMD_REGULATOR_LEVEL_TURBO
 845                                         RPM_SMD_REGULATOR_LEVEL_TURBO>;
 846                         qcom,min-level = <RPM_SMD_REGULATOR_LEVEL_NONE>;
 847                 };
 848
 849                 qcom,vdd-gfx-rstr{
 850                         qcom,vdd-rstr-reg = "vdd-gfx";
 851                         qcom,levels = <5 6 6>; /* Nominal, Turbo, Turbo */
 852                         qcom,min-level = <1>; /* No Request */
 853                 };
 854
 855                 msm_thermal_freq: qcom,vdd-apps-rstr{
 856                         qcom,vdd-rstr-reg = "vdd-apps";
 857                         qcom,levels = <1248000>;
 858                         qcom,freq-req;
 859                 };
 860         };
 861
 862         cx_ipeak_lm: cx_ipeak@1fe5040 {
 863                 compatible = "qcom,cx-ipeak-sdm660";
 864                 reg = <0x1fe5040 0x28>;
 865         };
 866
 867         qcom,bcl {
 868                 compatible = "qcom,bcl";
 869                 qcom,bcl-enable;
 870                 qcom,bcl-framework-interface;
 871                 qcom,bcl-hotplug-list = <&CPU6 &CPU7>;
 872                 qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5 &CPU6 &CPU7>;
 873                 qcom,ibat-monitor {
 874                         qcom,low-threshold-uamp = <3400000>;
 875                         qcom,high-threshold-uamp = <4200000>;
 876                         qcom,vph-high-threshold-uv = <3500000>;
 877                         qcom,vph-low-threshold-uv = <3300000>;
 878                         qcom,soc-low-threshold = <10>;
 879                 };
 880         };
 881
 882         qcom,lmh {
 883                 compatible = "qcom,lmh_v1";
 884                 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
 885         };
 886
 887         qcom,msm-core@780000 {
 888                 compatible = "qcom,apss-core-ea";
 889                 reg = <0x780000 0x1000>;
 890                 qcom,low-hyst-temp = <100>;
 891                 qcom,high-hyst-temp = <100>;
 892
 893                 ea0: ea0 {
 894                         sensor = <&sensor_information1>;
 895                 };
 896
 897                 ea1: ea1 {
 898                         sensor = <&sensor_information1>;
 899                 };
 900
 901                 ea2: ea2 {
 902                         sensor = <&sensor_information1>;
 903                 };
 904
 905                 ea3: ea3 {
 906                         sensor = <&sensor_information1>;
 907                 };
 908
 909                 ea4: ea4 {
 910                         sensor = <&sensor_information3>;
 911                 };
 912
 913                 ea5: ea5 {
 914                         sensor = <&sensor_information4>;
 915                 };
 916
 917                 ea6: ea6 {
 918                         sensor = <&sensor_information5>;
 919                 };
 920
 921                 ea7: ea7 {
 922                         sensor = <&sensor_information6>;
 923                 };
 924         };
 925
 926         uartblsp2dm1: serial@0c1b0000 {
 927                 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 928                 reg = <0xc1b0000 0x1000>;
 929                 interrupts = <0 114 0>;
 930                 status = "disabled";
 931                 clocks = <&clock_gcc GCC_BLSP2_UART2_APPS_CLK>,
 932                          <&clock_gcc GCC_BLSP2_AHB_CLK>;
 933                 clock-names = "core", "iface";
 934         };
 935
 936         slim_aud: slim@151c0000 {
 937                 cell-index = <1>;
 938                 compatible = "qcom,slim-ngd";
 939                 reg = <0x151c0000 0x2c000>,
 940                         <0x15184000 0x2a000>;
 941                 reg-names = "slimbus_physical", "slimbus_bam_physical";
 942                 interrupts = <0 163 0>, <0 164 0>;
 943                 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
 944                 qcom,apps-ch-pipes = <0x7e0000>;
 945                 qcom,ea-pc = <0x260>;
 946                 status = "disabled";
 947         };
 948
 949         slim_qca: slim@15240000 {
 950                 cell-index = <3>;
 951                 compatible = "qcom,slim-ngd";
 952                 reg = <0x15240000 0x2c000>,
 953                         <0x15204000 0x20000>;
 954                 reg-names = "slimbus_physical", "slimbus_bam_physical";
 955                 interrupts = <0 291 0>, <0 292 0>;
 956                 interrupt-names = "slimbus_irq", "slimbus_bam_irq";
 957                 qcom,apps-ch-pipes = <0x1800>;
 958
 959                 /* Slimbus Slave DT for WCN3990 */
 960                 btfmslim_codec: wcn3990 {
 961                         compatible = "qcom,btfmslim_slave";
 962                         elemental-addr = [00 01 20 02 17 02];
 963                         qcom,btfm-slim-ifd = "btfmslim_slave_ifd";
 964                         qcom,btfm-slim-ifd-elemental-addr = [00 00 20 02 17 02];
 965                 };
 966         };
 967
 968         timer@17920000 {
 969                 #address-cells = <1>;
 970                 #size-cells = <1>;
 971                 ranges;
 972                 compatible = "arm,armv7-timer-mem";
 973                 reg = <0x17920000 0x1000>;
 974                 clock-frequency = <19200000>;
 975
 976                 frame@17921000 {
 977                         frame-number = <0>;
 978                         interrupts = <0 8 0x4>,
 979                                      <0 7 0x4>;
 980                         reg = <0x17921000 0x1000>,
 981                               <0x17922000 0x1000>;
 982                 };
 983
 984                 frame@17923000 {
 985                         frame-number = <1>;
 986                         interrupts = <0 9 0x4>;
 987                         reg = <0x17923000 0x1000>;
 988                         status = "disabled";
 989                 };
 990
 991                 frame@17924000 {
 992                         frame-number = <2>;
 993                         interrupts = <0 10 0x4>;
 994                         reg = <0x17924000 0x1000>;
 995                         status = "disabled";
 996                 };
 997
 998                 frame@17925000 {
 999                         frame-number = <3>;
1000                         interrupts = <0 11 0x4>;
1001                         reg = <0x17925000 0x1000>;
1002                         status = "disabled";
1003                 };
1004
1005                 frame@17926000 {
1006                         frame-number = <4>;
1007                         interrupts = <0 12 0x4>;
1008                         reg = <0x17926000 0x1000>;
1009                         status = "disabled";
1010                 };
1011
1012                 frame@17927000 {
1013                         frame-number = <5>;
1014                         interrupts = <0 13 0x4>;
1015                         reg = <0x17927000 0x1000>;
1016                         status = "disabled";
1017                 };
1018
1019                 frame@17928000 {
1020                         frame-number = <6>;
1021                         interrupts = <0 14 0x4>;
1022                         reg = <0x17928000 0x1000>;
1023                         status = "disabled";
1024                 };
1025         };
1026
1027         arm64-cpu-erp {
1028                 compatible = "arm,arm64-cpu-erp";
1029                 interrupts = <0 43 4>,
1030                              <0 44 4>,
1031                              <0 41 4>,
1032                              <0 42 4>;
1033
1034                 interrupt-names = "pri-dbe-irq",
1035                                   "sec-dbe-irq",
1036                                   "pri-ext-irq",
1037                                   "sec-ext-irq";
1038
1039                 poll-delay-ms = <5000>;
1040         };
1041
1042         clock_rpmcc: qcom,rpmcc {
1043                 compatible = "qcom,rpmcc-sdm660", "qcom,rpmcc";
1044                 #clock-cells = <1>;
1045         };
1046
1047         clock_gcc: clock-controller@100000 {
1048                 compatible = "qcom,gcc-sdm660", "syscon";
1049                 reg = <0x100000 0x94000>;
1050                 vdd_dig-supply = <&pm660l_s3_level>;
1051                 vdd_dig_ao-supply = <&pm660l_s3_level_ao>;
1052                 #clock-cells = <1>;
1053                 #reset-cells = <1>;
1054         };
1055
1056         clock_mmss: clock-controller@c8c0000 {
1057                 compatible = "qcom,mmcc-sdm660";
1058                 reg = <0xc8c0000 0x40000>;
1059                 vdd_mx_mmss-supply = <&pm660l_s5_level>;
1060                 vdd_dig_mmss-supply = <&pm660l_s3_level>;
1061                 vdda-supply = <&pm660_l10>;
1062                 #clock-cells = <1>;
1063                 #reset-cells = <1>;
1064         };
1065
1066         clock_gpu: clock-controller@5065000 {
1067                 compatible = "qcom,gpu-sdm660";
1068                 reg = <0x5065000 0x10000>;
1069                 #clock-cells = <1>;
1070                 #reset-cells = <1>;
1071         };
1072
1073         clock_gfx: gfx@5065000 {
1074                 compatible = "qcom,gpucc-sdm660";
1075                 reg = <0x5065000 0x10000>;
1076                 vdd_dig_gfx-supply = <&pm660l_s3_level>;
1077                 vdd_mx_gfx-supply = <&pm660l_s5_level>;
1078                 vdd_gfx-supply = <&gfx_vreg_corner>;
1079                 qcom,gfxfreq-corner =
1080                         < 0         0>,
1081                         < 160000000 1>,  /* MinSVS */
1082                         < 266000000 2>,  /* LowSVS */
1083                         < 370000000 3>,  /* SVS    */
1084                         < 465000000 4>,  /* SVS_L1 */
1085                         < 588000000 5>,  /* NOM    */
1086                         < 647000000 6>,  /* NOM_L1 */
1087                         < 700000000 7>,  /* TURBO */
1088                         < 750000000 7>;  /* TURBO  */
1089                 #clock-cells = <1>;
1090                 #reset-cells = <1>;
1091         };
1092
1093         cpu_debug: syscon@1791101c {
1094                 compatible = "syscon";
1095                 reg = <0x1791101c 0x4>;
1096         };
1097
1098         gpu_debug: syscon@05065120 {
1099                 compatible = "syscon";
1100                 reg = <0x05065120 0x4>;
1101         };
1102
1103         mmss_debug: syscon@c8c0900 {
1104                 compatible = "syscon";
1105                 reg = <0xc8c0900 0x4>;
1106         };
1107
1108         clock_debug: qcom,cc-debug@62000 {
1109                 compatible = "qcom,gcc-debug-sdm660";
1110                 reg = <0x62000 0x4>;
1111                 reg-names = "dbg_offset";
1112                 clocks = <&clock_rpmcc  RPM_XO_CLK_SRC>;
1113                 clock-names = "xo_clk_src";
1114                 qcom,cc-count = <4>;
1115                 qcom,gcc = <&clock_gcc>;
1116                 qcom,cpu = <&cpu_debug>;
1117                 qcom,mmss = <&mmss_debug>;
1118                 qcom,gpu = <&gpu_debug>;
1119                 #clock-cells = <1>;
1120         };
1121
1122         cpubw: qcom,cpubw {
1123                 compatible = "qcom,devbw";
1124                 governor = "performance";
1125                 qcom,src-dst-ports = <1 512>;
1126                 qcom,active-only;
1127                 qcom,bw-tbl =
1128                         <  381  /*  100 MHz */ >,
1129                         <  572  /*  150 MHz */ >,
1130                         <  762  /*  200 MHz */ >,
1131                         <  1144 /*  300 MHz */ >,
1132                         <  1571 /*  412 MHz */ >,
1133                         <  2086 /*  547 MHz */ >,
1134                         <  2597 /*  681 MHz */ >,
1135                         <  2929 /*  768 MHz */ >,
1136                         <  3879 /* 1017 MHz */ >,
1137                         <  4943 /* 1296 MHz */ >,
1138                         <  5163 /* 1353 MHz */ >,
1139                         <  5931 /* 1555 MHz */ >,
1140                         <  6881 /* 1804 MHz */ >;
1141         };
1142
1143         bwmon: qcom,cpu-bwmon {
1144                 compatible = "qcom,bimc-bwmon4";
1145                 reg = <0x01008000 0x300>, <0x01001000 0x200>;
1146                 reg-names = "base", "global_base";
1147                 interrupts = <0 183 4>;
1148                 qcom,mport = <0>;
1149                 qcom,hw-timer-hz = <19200000>;
1150                 qcom,target-dev = <&cpubw>;
1151         };
1152
1153         mincpubw: qcom,mincpubw {
1154                 compatible = "qcom,devbw";
1155                 governor = "powersave";
1156                 qcom,src-dst-ports = <1 512>;
1157                 qcom,active-only;
1158                 qcom,bw-tbl =
1159                         <  381  /*  100 MHz */ >,
1160                         <  572  /*  150 MHz */ >,
1161                         <  762  /*  200 MHz */ >,
1162                         <  1144 /*  300 MHz */ >,
1163                         <  1571 /*  412 MHz */ >,
1164                         <  2086 /*  547 MHz */ >,
1165                         <  2597 /*  681 MHz */ >,
1166                         <  2929 /*  768 MHz */ >,
1167                         <  3879 /* 1017 MHz */ >,
1168                         <  4943 /* 1296 MHz */ >,
1169                         <  5163 /* 1353 MHz */ >,
1170                         <  5931 /* 1555 MHz */ >,
1171                         <  6881 /* 1804 MHz */ >;
1172         };
1173
1174         memlat_cpu0: qcom,memlat-cpu0 {
1175                 compatible = "qcom,devbw";
1176                 governor = "powersave";
1177                 qcom,src-dst-ports = <1 512>;
1178                 qcom,active-only;
1179                 qcom,bw-tbl =
1180                         <  381  /*  100 MHz */ >,
1181                         <  572  /*  150 MHz */ >,
1182                         <  762  /*  200 MHz */ >,
1183                         <  1144 /*  300 MHz */ >,
1184                         <  1571 /*  412 MHz */ >,
1185                         <  2086 /*  547 MHz */ >,
1186                         <  2597 /*  681 MHz */ >,
1187                         <  2929 /*  768 MHz */ >,
1188                         <  3879 /* 1017 MHz */ >,
1189                         <  4943 /* 1296 MHz */ >,
1190                         <  5163 /* 1353 MHz */ >,
1191                         <  5931 /* 1555 MHz */ >,
1192                         <  6881 /* 1804 MHz */ >;
1193         };
1194
1195         memlat_cpu4: qcom,memlat-cpu4 {
1196                 compatible = "qcom,devbw";
1197                 governor = "powersave";
1198                 qcom,src-dst-ports = <1 512>;
1199                 qcom,active-only;
1200                 qcom,bw-tbl =
1201                         <  381  /*  100 MHz */ >,
1202                         <  572  /*  150 MHz */ >,
1203                         <  762  /*  200 MHz */ >,
1204                         <  1144 /*  300 MHz */ >,
1205                         <  1571 /*  412 MHz */ >,
1206                         <  2086 /*  547 MHz */ >,
1207                         <  2597 /*  681 MHz */ >,
1208                         <  2929 /*  768 MHz */ >,
1209                         <  3879 /* 1017 MHz */ >,
1210                         <  4943 /* 1296 MHz */ >,
1211                         <  5163 /* 1353 MHz */ >,
1212                         <  5931 /* 1555 MHz */ >,
1213                         <  6881 /* 1804 MHz */ >;
1214         };
1215
1216         devfreq_memlat_0: qcom,arm-memlat-mon-0 {
1217                 compatible = "qcom,arm-memlat-mon";
1218                 qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
1219                 qcom,target-dev = <&memlat_cpu0>;
1220                 qcom,core-dev-table =
1221                         < 902400 762 >,
1222                         < 1401600 2086 >,
1223                         < 1881600 3879 >;
1224         };
1225
1226         devfreq_memlat_4: qcom,arm-memlat-mon-4 {
1227                 compatible = "qcom,arm-memlat-mon";
1228                 qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
1229                 qcom,target-dev = <&memlat_cpu4>;
1230                 qcom,core-dev-table =
1231                         < 1113600 762 >,
1232                         < 1401600 3879 >,
1233                         < 2150400 5931 >,
1234                         < 2457600 6881 >;
1235         };
1236
1237         devfreq_cpufreq: devfreq-cpufreq {
1238                 mincpubw-cpufreq {
1239                         target-dev = <&mincpubw>;
1240                         cpu-to-dev-map-0 =
1241                                 < 633600 762 >,
1242                                 < 1401600 1571 >,
1243                                 < 1881600 2929 >;
1244                         cpu-to-dev-map-4 =
1245                                 < 1113600 762 >,
1246                                 < 1401600 2086 >,
1247                                 < 1747200 2929 >,
1248                                 < 2150400 3879 >,
1249                                 < 2457600 6881 >;
1250                 };
1251         };
1252
1253         clock_cpu: qcom,clk-cpu-660@179c0000 {
1254                 compatible = "qcom,clk-cpu-osm";
1255                 reg = <0x179c0000 0x4000>, <0x17916000 0x1000>,
1256                       <0x17816000 0x1000>, <0x179d1000 0x1000>,
1257                       <0x00784130 0x8>, <0x00784130 0x8>;
1258                 reg-names = "osm", "pwrcl_pll", "perfcl_pll",
1259                             "apcs_common", "pwrcl_efuse",
1260                             "perfcl_efuse";
1261
1262                 vdd-pwrcl-supply = <&apc0_pwrcl_vreg>;
1263                 vdd-perfcl-supply = <&apc1_perfcl_vreg>;
1264
1265                 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
1266                              <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>;
1267                 interrupt-names = "pwrcl-irq", "perfcl-irq";
1268
1269                 qcom,pwrcl-speedbin0-v0 =
1270                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1271                         <   633600000 0x05040021 0x03200020 0x1 2 >,
1272                         <   902400000 0x0404002f 0x04260026 0x1 3 >,
1273                         <  1113600000 0x0404003a 0x052e002e 0x2 4 >,
1274                         <  1401600000 0x04040049 0x073a003a 0x2 5 >,
1275                         <  1536000000 0x04040050 0x08400040 0x2 6 >,
1276                         <  1747200000 0x0404005b 0x09480048 0x2 7 >,
1277                         <  1843200000 0x04040060 0x094c004c 0x3 8 >;
1278
1279                 qcom,pwrcl-speedbin1-v0 =
1280                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1281                         <   633600000 0x05040021 0x03200020 0x1 2 >,
1282                         <   902400000 0x0404002f 0x04260026 0x1 3 >,
1283                         <  1113600000 0x0404003a 0x052e002e 0x2 4 >,
1284                         <  1401600000 0x04040049 0x073a003a 0x2 5 >,
1285                         <  1536000000 0x04040050 0x08400040 0x2 6 >,
1286                         <  1747200000 0x0404005b 0x09480048 0x2 7 >,
1287                         <  1843200000 0x04040060 0x094c004c 0x3 8 >;
1288
1289                 qcom,pwrcl-speedbin3-v0 =
1290                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1291                         <   633600000 0x05040021 0x03200020 0x1 2 >,
1292                         <   902400000 0x0404002f 0x04260026 0x1 3 >,
1293                         <  1113600000 0x0404003a 0x052e002e 0x2 4 >,
1294                         <  1401600000 0x04040049 0x073a003a 0x2 5 >,
1295                         <  1536000000 0x04040050 0x08400040 0x2 6 >,
1296                         <  1612800000 0x04040054 0x09430043 0x2 7 >;
1297
1298                 qcom,pwrcl-speedbin4-v0 =
1299                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1300                         <   633600000 0x05040021 0x03200020 0x1 2 >,
1301                         <   902400000 0x0404002f 0x04260026 0x1 3 >,
1302                         <  1113600000 0x0404003a 0x052e002e 0x2 4 >,
1303                         <  1401600000 0x04040049 0x073a003a 0x2 5 >,
1304                         <  1536000000 0x04040050 0x08400040 0x2 6 >,
1305                         <  1747200000 0x0404005b 0x09480048 0x2 7 >,
1306                         <  1843200000 0x04040060 0x094c004c 0x3 8 >;
1307
1308                 qcom,perfcl-speedbin0-v0 =
1309                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1310                         <  1113600000 0x0404003a 0x052e002e 0x1 2 >,
1311                         <  1401600000 0x04040049 0x073a003a 0x2 3 >,
1312                         <  1747200000 0x0404005b 0x09480048 0x2 4 >,
1313                         <  1958400000 0x04040066 0x0a510051 0x2 5 >,
1314                         <  2150400000 0x04040070 0x0b590059 0x2 6 >,
1315                         <  2457600000 0x04040080 0x0c660066 0x3 7 >;
1316
1317                 qcom,perfcl-speedbin1-v0 =
1318                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1319                         <  1113600000 0x0404003a 0x052e002e 0x1 2 >,
1320                         <  1401600000 0x04040049 0x073a003a 0x2 3 >,
1321                         <  1747200000 0x0404005b 0x09480048 0x2 4 >,
1322                         <  1958400000 0x04040066 0x0a510051 0x2 5 >,
1323                         <  2150400000 0x04040070 0x0b590059 0x2 6 >,
1324                         <  2208000000 0x04040073 0x0b5c005c 0x3 7 >;
1325
1326                 qcom,perfcl-speedbin3-v0 =
1327                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1328                         <  1113600000 0x0404003a 0x052e002e 0x1 2 >,
1329                         <  1401600000 0x04040049 0x073a003a 0x2 3 >,
1330                         <  1747200000 0x0404005b 0x09480048 0x2 4 >,
1331                         <  1804800000 0x0404005e 0x094b004b 0x2 5 >;
1332
1333                 qcom,perfcl-speedbin4-v0 =
1334                         <   300000000 0x0004000f 0x01200020 0x1 1 >,
1335                         <  1113600000 0x0404003a 0x052e002e 0x1 2 >,
1336                         <  1401600000 0x04040049 0x073a003a 0x2 3 >,
1337                         <  1747200000 0x0404005b 0x09480048 0x2 4 >,
1338                         <  1958400000 0x04040066 0x0a510051 0x2 5 >;
1339
1340                 qcom,up-timer = <1000 1000>;
1341                 qcom,down-timer = <1000 1000>;
1342                 qcom,set-ret-inactive;
1343                 qcom,enable-llm-freq-vote;
1344                 qcom,llm-freq-up-timer = <327675 327675>;
1345                 qcom,llm-freq-down-timer = <327675 327675>;
1346                 qcom,enable-llm-volt-vote;
1347                 qcom,llm-volt-up-timer = <327675 327675>;
1348                 qcom,llm-volt-down-timer = <327675 327675>;
1349                 qcom,cc-reads = <10>;
1350                 qcom,cc-delay = <5>;
1351                 qcom,cc-factor = <100>;
1352                 qcom,osm-clk-rate = <200000000>;
1353                 qcom,xo-clk-rate = <19200000>;
1354
1355                 qcom,l-val-base = <0x17916004 0x17816004>;
1356                 qcom,apcs-itm-present = <0x179d143c 0x179d143c>;
1357                 qcom,apcs-pll-user-ctl = <0x1791600c 0x1781600c>;
1358                 qcom,apcs-cfg-rcgr = <0x17911054 0x17811054>;
1359                 qcom,apcs-cmd-rcgr = <0x17911050 0x17811050>;
1360                 qcom,apm-mode-ctl = <0x179d0004 0x179d0010>;
1361                 qcom,apm-ctrl-status = <0x179d000c 0x179d0018>;
1362
1363                 qcom,apm-threshold-voltage = <872000>;
1364                 qcom,boost-fsm-en;
1365                 qcom,safe-fsm-en;
1366                 qcom,ps-fsm-en;
1367                 qcom,droop-fsm-en;
1368                 qcom,wfx-fsm-en;
1369                 qcom,pc-fsm-en;
1370
1371                 clock-names = "aux_clk", "xo_a";
1372                 clocks = <&clock_gcc HMSS_GPLL0_CLK_SRC>,
1373                         <&clock_rpmcc RPM_XO_A_CLK_SRC>;
1374
1375                 #clock-cells = <1>;
1376         };
1377
1378         msm_cpufreq: qcom,msm-cpufreq {
1379                 compatible = "qcom,msm-cpufreq";
1380                 clock-names = "cpu0_clk", "cpu4_clk";
1381                 clocks = <&clock_cpu PWRCL_CLK>,
1382                          <&clock_cpu PERFCL_CLK>;
1383
1384                 qcom,governor-per-policy;
1385
1386                 qcom,cpufreq-table-0 =
1387                         <  633600 >,
1388                         <  902400 >,
1389                         < 1113600 >,
1390                         < 1401600 >,
1391                         < 1536000 >,
1392                         < 1612800 >,
1393                         < 1747200 >,
1394                         < 1843200 >;
1395
1396                 qcom,cpufreq-table-4 =
1397                         < 1113600 >,
1398                         < 1401600 >,
1399                         < 1747200 >,
1400                         < 1804800 >,
1401                         < 1958400 >,
1402                         < 2150400 >,
1403                         < 2208000 >,
1404                         < 2457600 >;
1405         };
1406
1407         sdhc_1: sdhci@c0c4000 {
1408                 compatible = "qcom,sdhci-msm-v5";
1409                 reg = <0xc0c4000 0x1000>, <0xc0c5000 0x1000>;
1410                 reg-names = "hc_mem", "cmdq_mem";
1411
1412                 interrupts = <0 110 0>, <0 112 0>;
1413                 interrupt-names = "hc_irq", "pwr_irq";
1414
1415                 qcom,bus-width = <8>;
1416                 qcom,large-address-bus;
1417                 sdhc-msm-crypto = <&sdcc1_ice>;
1418
1419                 qcom,devfreq,freq-table = <50000000 200000000>;
1420
1421                 qcom,msm-bus,name = "sdhc1";
1422                 qcom,msm-bus,num-cases = <9>;
1423                 qcom,msm-bus,num-paths = <2>;
1424                 qcom,msm-bus,vectors-KBps =
1425                         /* No vote */
1426                         <78 512 0 0>, <1 606 0 0>,
1427                         /* 400 KB/s*/
1428                         <78 512 1046 1600>,
1429                         <1 606 1600 1600>,
1430                         /* 20 MB/s */
1431                         <78 512 52286 80000>,
1432                         <1 606 80000 80000>,
1433                         /* 25 MB/s */
1434                         <78 512 65360 100000>,
1435                         <1 606 100000 100000>,
1436                         /* 50 MB/s */
1437                         <78 512 130718 200000>,
1438                         <1 606 133320 133320>,
1439                         /* 100 MB/s */
1440                         <78 512 130718 200000>,
1441                         <1 606 150000 150000>,
1442                         /* 200 MB/s */
1443                         <78 512 261438 400000>,
1444                         <1 606 300000 300000>,
1445                         /* 400 MB/s */
1446                         <78 512 261438 400000>,
1447                         <1 606 300000 300000>,
1448                         /* Max. bandwidth */
1449                         <78 512 1338562 4096000>,
1450                         <1 606 1338562 4096000>;
1451                 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1452                         100000000 200000000 400000000 4294967295>;
1453
1454                 clocks = <&clock_gcc GCC_SDCC1_AHB_CLK>,
1455                          <&clock_gcc GCC_SDCC1_APPS_CLK>,
1456                          <&clock_gcc GCC_SDCC1_ICE_CORE_CLK>;
1457                 clock-names = "iface_clk", "core_clk", "ice_core_clk";
1458                 qcom,ice-clk-rates = <300000000 75000000>;
1459
1460                 status = "disabled";
1461         };
1462
1463         sdhc_2: sdhci@c084000 {
1464                 compatible = "qcom,sdhci-msm-v5";
1465                 reg = <0xc084000 0x1000>;
1466                 reg-names = "hc_mem";
1467
1468                 interrupts = <0 125 0>, <0 221 0>;
1469                 interrupt-names = "hc_irq", "pwr_irq";
1470
1471                 qcom,bus-width = <4>;
1472                 qcom,large-address-bus;
1473
1474                 qcom,msm-bus,name = "sdhc2";
1475                 qcom,msm-bus,num-cases = <8>;
1476                 qcom,msm-bus,num-paths = <2>;
1477                 qcom,msm-bus,vectors-KBps =
1478                         /* No vote */
1479                         <81 512 0 0>, <1 608 0 0>,
1480                         /* 400 KB/s*/
1481                         <81 512 1046 1600>,
1482                         <1 608 1600 1600>,
1483                         /* 20 MB/s */
1484                         <81 512 52286 80000>,
1485                         <1 608 80000 80000>,
1486                         /* 25 MB/s */
1487                         <81 512 65360 100000>,
1488                         <1 608 100000 100000>,
1489                         /* 50 MB/s */
1490                         <81 512 130718 200000>,
1491                         <1 608 133320 133320>,
1492                         /* 100 MB/s */
1493                         <81 512 261438 200000>,
1494                         <1 608 150000 150000>,
1495                         /* 200 MB/s */
1496                         <81 512 261438 400000>,
1497                         <1 608 300000 300000>,
1498                         /* Max. bandwidth */
1499                         <81 512 1338562 4096000>,
1500                         <1 608 1338562 4096000>;
1501                 qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
1502                         100000000 200000000 4294967295>;
1503
1504                 qcom,devfreq,freq-table = <50000000 200000000>;
1505                 clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
1506                         <&clock_gcc GCC_SDCC2_APPS_CLK>;
1507                 clock-names = "iface_clk", "core_clk";
1508
1509                 status = "disabled";
1510         };
1511
1512         ipa_hw: qcom,ipa@14780000 {
1513                 compatible = "qcom,ipa";
1514                 reg = <0x14780000 0x4effc>, <0x14784000 0x26934>;
1515                 reg-names = "ipa-base", "bam-base";
1516                 interrupts = <0 333 0>,
1517                                 <0 432 0>;
1518                 interrupt-names = "ipa-irq", "bam-irq";
1519                 qcom,ipa-hw-ver = <6>; /* IPA core version = IPAv2.6L */
1520                 qcom,ipa-hw-mode = <0>; /* IPA hw type = Normal */
1521                 qcom,wan-rx-ring-size = <192>; /* IPA WAN-rx-ring-size*/
1522                 qcom,lan-rx-ring-size = <192>; /* IPA LAN-rx-ring-size*/
1523                 clocks = <&clock_rpmcc RPM_IPA_CLK>,
1524                         <&clock_rpmcc AGGR2_NOC_SMMU_CLK>;
1525                 clock-names = "core_clk", "smmu_clk";
1526                 qcom,arm-smmu;
1527                 qcom,smmu-disable-htw;
1528                 qcom,smmu-s1-bypass;
1529                 qcom,ee = <0>;
1530                 qcom,use-ipa-tethering-bridge;
1531                 qcom,modem-cfg-emb-pipe-flt;
1532                 qcom,ipa-wdi2;
1533                 qcom,use-dma-zone;
1534                 qcom,msm-bus,name = "ipa";
1535                 qcom,msm-bus,num-cases = <4>;
1536                 qcom,msm-bus,num-paths = <2>;
1537                 qcom,msm-bus,vectors-KBps =
1538                 /* No vote */
1539                 <90 512 0 0>,
1540                 <1 676 0 0>,
1541                 /* SVS */
1542                 <90 512 80000 640000>,
1543                 <1 676 80000 80000>,
1544                 /* NOMINAL */
1545                 <90 512 206000 960000>,
1546                 <1 676 206000 160000>,
1547                 /* TURBO */
1548                 <90 512 206000 960000>,
1549                 <1 676 206000 160000>;
1550                 qcom,bus-vector-names = "MIN", "SVS", "PERF", "TURBO";
1551                 qcom,rx-polling-sleep-ms = <1>; /* Polling sleep interval */
1552                 qcom,ipa-polling-iteration = <40>; /* Polling Iteration */
1553
1554                 ipa_smmu_ap: ipa_smmu_ap {
1555                         compatible = "qcom,ipa-smmu-ap-cb";
1556                         iommus = <&anoc2_smmu 0x19C0>;
1557                         qcom,iova-mapping = <0x10000000 0x40000000>;
1558                 };
1559
1560                 ipa_smmu_wlan: ipa_smmu_wlan {
1561                         status = "disabled";
1562                         compatible = "qcom,ipa-smmu-wlan-cb";
1563                         iommus = <&anoc2_smmu 0x19C1>;
1564                 };
1565
1566                 ipa_smmu_uc: ipa_smmu_uc {
1567                         compatible = "qcom,ipa-smmu-uc-cb";
1568                         iommus = <&anoc2_smmu 0x19C2>;
1569                         qcom,iova-mapping = <0x40000000 0x20000000>;
1570                 };
1571         };
1572
1573         qcom,rmtfs_sharedmem@85e00000 {
1574                 compatible = "qcom,sharedmem-uio";
1575                 reg = <0x85e00000 0x200000>;
1576                 reg-names = "rmtfs";
1577                 qcom,client-id = <0x00000001>;
1578         };
1579
1580         qcom,rmnet-ipa {
1581                 compatible = "qcom,rmnet-ipa";
1582                 qcom,rmnet-ipa-ssr;
1583                 qcom,ipa-loaduC;
1584                 qcom,ipa-advertise-sg-support;
1585         };
1586
1587         qcom,ipc-spinlock@1f40000 {
1588                 compatible = "qcom,ipc-spinlock-sfpb";
1589                 reg = <0x1f40000 0x8000>;
1590                 qcom,num-locks = <8>;
1591         };
1592
1593         qcom,smem@86000000 {
1594                 compatible = "qcom,smem";
1595                 reg = <0x86000000 0x200000>,
1596                         <0x17911008 0x4>,
1597                         <0x778000 0x7000>,
1598                         <0x1fd4000 0x8>;
1599                 reg-names = "smem", "irq-reg-base", "aux-mem1",
1600                         "smem_targ_info_reg";
1601                 qcom,mpu-enabled;
1602         };
1603
1604         qcom,msm-cdsp-loader {
1605                 compatible = "qcom,cdsp-loader";
1606                 qcom,proc-img-to-load = "cdsp";
1607         };
1608
1609         qcom,msm-adsprpc-mem {
1610                 compatible = "qcom,msm-adsprpc-mem-region";
1611                 memory-region = <&adsp_mem>;
1612         };
1613
1614         qcom,msm_fastrpc {
1615                 compatible = "qcom,msm-fastrpc-adsp";
1616                 qcom,fastrpc-glink;
1617                 qcom,fastrpc-vmid-heap-shared;
1618
1619                 qcom,msm_fastrpc_compute_cb1 {
1620                         compatible = "qcom,msm-fastrpc-compute-cb";
1621                         label = "adsprpc-smd";
1622                         iommus = <&lpass_q6_smmu 3>;
1623                         dma-coherent;
1624                 };
1625                 qcom,msm_fastrpc_compute_cb2 {
1626                         compatible = "qcom,msm-fastrpc-compute-cb";
1627                         label = "adsprpc-smd";
1628                         iommus = <&lpass_q6_smmu 7>;
1629                         dma-coherent;
1630                 };
1631                 qcom,msm_fastrpc_compute_cb3 {
1632                         compatible = "qcom,msm-fastrpc-compute-cb";
1633                         label = "adsprpc-smd";
1634                         iommus = <&lpass_q6_smmu 8>;
1635                         dma-coherent;
1636                 };
1637                 qcom,msm_fastrpc_compute_cb4 {
1638                         compatible = "qcom,msm-fastrpc-compute-cb";
1639                         label = "adsprpc-smd";
1640                         iommus = <&lpass_q6_smmu 9>;
1641                         dma-coherent;
1642                 };
1643                 qcom,msm_fastrpc_compute_cb5 {
1644                         compatible = "qcom,msm-fastrpc-compute-cb";
1645                         label = "cdsprpc-smd";
1646                         iommus = <&turing_q6_smmu 3>;
1647                         dma-coherent;
1648                 };
1649                 qcom,msm_fastrpc_compute_cb6 {
1650                         compatible = "qcom,msm-fastrpc-compute-cb";
1651                         label = "cdsprpc-smd";
1652                         iommus = <&turing_q6_smmu 4>;
1653                         dma-coherent;
1654                 };
1655                 qcom,msm_fastrpc_compute_cb7 {
1656                         compatible = "qcom,msm-fastrpc-compute-cb";
1657                         label = "cdsprpc-smd";
1658                         iommus = <&turing_q6_smmu 5>;
1659                         dma-coherent;
1660                 };
1661
1662                 qcom,msm_fastrpc_compute_cb8 {
1663                         compatible = "qcom,msm-fastrpc-compute-cb";
1664                         label = "cdsprpc-smd";
1665                         iommus = <&turing_q6_smmu 6>;
1666                         dma-coherent;
1667                 };
1668                 qcom,msm_fastrpc_compute_cb9 {
1669                         compatible = "qcom,msm-fastrpc-compute-cb";
1670                         label = "cdsprpc-smd";
1671                         iommus = <&turing_q6_smmu 7>;
1672                         dma-coherent;
1673                 };
1674                 qcom,msm_fastrpc_compute_cb10 {
1675                         compatible = "qcom,msm-fastrpc-compute-cb";
1676                         label = "cdsprpc-smd";
1677                         iommus = <&turing_q6_smmu 8>;
1678                         dma-coherent;
1679                 };
1680                 qcom,msm_fastrpc_compute_cb11 {
1681                         compatible = "qcom,msm-fastrpc-compute-cb";
1682                         label = "cdsprpc-smd";
1683                         iommus = <&turing_q6_smmu 9>;
1684                         dma-coherent;
1685                 };
1686                 qcom,msm_fastrpc_compute_cb12 {
1687                         compatible = "qcom,msm-fastrpc-compute-cb";
1688                         label = "cdsprpc-smd";
1689                         iommus = <&turing_q6_smmu 10>;
1690                         dma-coherent;
1691                 };
1692                 qcom,msm_fastrpc_compute_cb13 {
1693                         compatible = "qcom,msm-fastrpc-compute-cb";
1694                         label = "cdsprpc-smd";
1695                         iommus = <&turing_q6_smmu 11>;
1696                         dma-coherent;
1697                 };
1698         };
1699
1700
1701         dcc: dcc@10b3000 {
1702                 compatible = "qcom,dcc";
1703                 reg = <0x10b3000 0x1000>,
1704                       <0x10b4000 0x2000>;
1705                 reg-names = "dcc-base", "dcc-ram-base";
1706
1707                 clocks = <&clock_gcc GCC_DCC_AHB_CLK>;
1708                 clock-names = "dcc_clk";
1709         };
1710
1711         qcom,glink-smem-native-xprt-modem@86000000 {
1712                 compatible = "qcom,glink-smem-native-xprt";
1713                 reg = <0x86000000 0x200000>,
1714                         <0x17911008 0x4>;
1715                 reg-names = "smem", "irq-reg-base";
1716                 qcom,irq-mask = <0x8000>;
1717                 interrupts = <0 452 1>;
1718                 label = "mpss";
1719         };
1720
1721         qcom,glink-smem-native-xprt-adsp@86000000 {
1722                 compatible = "qcom,glink-smem-native-xprt";
1723                 reg = <0x86000000 0x200000>,
1724                         <0x17911008 0x4>;
1725                 reg-names = "smem", "irq-reg-base";
1726                 qcom,irq-mask = <0x200>;
1727                 interrupts = <0 157 1>;
1728                 label = "lpass";
1729                 qcom,qos-config = <&glink_qos_adsp>;
1730                 qcom,ramp-time = <0xaf>;
1731         };
1732
1733         glink_qos_adsp: qcom,glink-qos-config-adsp {
1734                 compatible = "qcom,glink-qos-config";
1735                 qcom,flow-info = <0x3c 0x0>,
1736                                 <0x3c 0x0>,
1737                                 <0x3c 0x0>,
1738                                 <0x3c 0x0>;
1739                 qcom,mtu-size = <0x800>;
1740                 qcom,tput-stats-cycle = <0xa>;
1741         };
1742
1743         qcom,glink-smem-native-xprt-cdsp@86000000 {
1744                 compatible = "qcom,glink-smem-native-xprt";
1745                 reg = <0x86000000 0x200000>,
1746                         <0x17911008 0x4>;
1747                 reg-names = "smem", "irq-reg-base";
1748                 qcom,irq-mask = <0x20000000>;
1749                 interrupts = <0 513 1>;
1750                 label = "cdsp";
1751         };
1752
1753         qcom,glink-smem-native-xprt-rpm@778000 {
1754                 compatible = "qcom,glink-rpm-native-xprt";
1755                 reg = <0x778000 0x7000>,
1756                         <0x17911008 0x4>;
1757                 reg-names = "msgram", "irq-reg-base";
1758                 qcom,irq-mask = <0x1>;
1759                 interrupts = <0 168 1>;
1760                 label = "rpm";
1761         };
1762
1763         glink_mpss: qcom,glink-ssr-modem {
1764                 compatible = "qcom,glink_ssr";
1765                 label = "modem";
1766                 qcom,edge = "mpss";
1767                 qcom,notify-edges = <&glink_lpass>, <&glink_rpm>,
1768                                 <&glink_cdsp>;
1769                 qcom,xprt = "smem";
1770         };
1771
1772         glink_lpass: qcom,glink-ssr-adsp {
1773                 compatible = "qcom,glink_ssr";
1774                 label = "adsp";
1775                 qcom,edge = "lpass";
1776                 qcom,notify-edges = <&glink_mpss>, <&glink_rpm>,
1777                                 <&glink_cdsp>;
1778                 qcom,xprt = "smem";
1779         };
1780
1781         glink_rpm: qcom,glink-ssr-rpm {
1782                 compatible = "qcom,glink_ssr";
1783                 label = "rpm";
1784                 qcom,edge = "rpm";
1785                 qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
1786                                 <&glink_cdsp>;
1787                 qcom,xprt = "smem";
1788         };
1789
1790         glink_cdsp: qcom,glink-ssr-cdsp {
1791                 compatible = "qcom,glink_ssr";
1792                 label = "cdsp";
1793                 qcom,edge = "cdsp";
1794                 qcom,notify-edges = <&glink_lpass>, <&glink_mpss>,
1795                                 <&glink_rpm>;
1796                 qcom,xprt = "smem";
1797         };
1798
1799         glink_spi_xprt_wdsp: qcom,glink-spi-xprt-wdsp {
1800                 compatible = "qcom,glink-spi-xprt";
1801                 label = "wdsp";
1802                 qcom,remote-fifo-config = <&glink_fifo_wdsp>;
1803                 qcom,qos-config = <&glink_qos_wdsp>;
1804                 qcom,ramp-time = <0x10>,
1805                                      <0x20>,
1806                                      <0x30>,
1807                                      <0x40>;
1808         };
1809
1810         glink_fifo_wdsp: qcom,glink-fifo-config-wdsp {
1811                 compatible = "qcom,glink-fifo-config";
1812                 qcom,out-read-idx-reg = <0x12000>;
1813                 qcom,out-write-idx-reg = <0x12004>;
1814                 qcom,in-read-idx-reg = <0x1200c>;
1815                 qcom,in-write-idx-reg = <0x12010>;
1816         };
1817
1818         glink_qos_wdsp: qcom,glink-qos-config-wdsp {
1819                 compatible = "qcom,glink-qos-config";
1820                 qcom,flow-info = <0x80 0x0>,
1821                                  <0x70 0x1>,
1822                                  <0x60 0x2>,
1823                                  <0x50 0x3>;
1824                 qcom,mtu-size = <0x800>;
1825                 qcom,tput-stats-cycle = <0xa>;
1826         };
1827
1828         qcom,glink_pkt {
1829                 compatible = "qcom,glinkpkt";
1830
1831                 qcom,glinkpkt-at-mdm0 {
1832                         qcom,glinkpkt-transport = "smem";
1833                         qcom,glinkpkt-edge = "mpss";
1834                         qcom,glinkpkt-ch-name = "DS";
1835                         qcom,glinkpkt-dev-name = "at_mdm0";
1836                 };
1837
1838                 qcom,glinkpkt-loopback_cntl {
1839                         qcom,glinkpkt-transport = "lloop";
1840                         qcom,glinkpkt-edge = "local";
1841                         qcom,glinkpkt-ch-name = "LOCAL_LOOPBACK_CLNT";
1842                         qcom,glinkpkt-dev-name = "glink_pkt_loopback_ctrl";
1843                 };
1844
1845                 qcom,glinkpkt-loopback_data {
1846                         qcom,glinkpkt-transport = "lloop";
1847                         qcom,glinkpkt-edge = "local";
1848                         qcom,glinkpkt-ch-name = "glink_pkt_lloop_CLNT";
1849                         qcom,glinkpkt-dev-name = "glink_pkt_loopback";
1850                 };
1851
1852                 qcom,glinkpkt-apr-apps2 {
1853                         qcom,glinkpkt-transport = "smem";
1854                         qcom,glinkpkt-edge = "adsp";
1855                         qcom,glinkpkt-ch-name = "apr_apps2";
1856                         qcom,glinkpkt-dev-name = "apr_apps2";
1857                 };
1858
1859                 qcom,glinkpkt-data40-cntl {
1860                         qcom,glinkpkt-transport = "smem";
1861                         qcom,glinkpkt-edge = "mpss";
1862                         qcom,glinkpkt-ch-name = "DATA40_CNTL";
1863                         qcom,glinkpkt-dev-name = "smdcntl8";
1864                 };
1865
1866                 qcom,glinkpkt-data1 {
1867                         qcom,glinkpkt-transport = "smem";
1868                         qcom,glinkpkt-edge = "mpss";
1869                         qcom,glinkpkt-ch-name = "DATA1";
1870                         qcom,glinkpkt-dev-name = "smd7";
1871                 };
1872
1873                 qcom,glinkpkt-data4 {
1874                         qcom,glinkpkt-transport = "smem";
1875                         qcom,glinkpkt-edge = "mpss";
1876                         qcom,glinkpkt-ch-name = "DATA4";
1877                         qcom,glinkpkt-dev-name = "smd8";
1878                 };
1879
1880                 qcom,glinkpkt-data11 {
1881                         qcom,glinkpkt-transport = "smem";
1882                         qcom,glinkpkt-edge = "mpss";
1883                         qcom,glinkpkt-ch-name = "DATA11";
1884                         qcom,glinkpkt-dev-name = "smd11";
1885                 };
1886         };
1887
1888         rpm_bus: qcom,rpm-smd {
1889                 compatible = "qcom,rpm-glink";
1890                 qcom,glink-edge = "rpm";
1891                 rpm-channel-name = "rpm_requests";
1892         };
1893
1894         qcom,ipc_router {
1895                 compatible = "qcom,ipc_router";
1896                 qcom,node-id = <1>;
1897         };
1898
1899         qcom,ipc_router_modem_xprt {
1900                 compatible = "qcom,ipc_router_glink_xprt";
1901                 qcom,ch-name = "IPCRTR";
1902                 qcom,xprt-remote = "mpss";
1903                 qcom,glink-xprt = "smem";
1904                 qcom,xprt-linkid = <1>;
1905                 qcom,xprt-version = <1>;
1906                 qcom,fragmented-data;
1907         };
1908
1909         qcom,ipc_router_q6_xprt {
1910                 compatible = "qcom,ipc_router_glink_xprt";
1911                 qcom,ch-name = "IPCRTR";
1912                 qcom,xprt-remote = "lpass";
1913                 qcom,glink-xprt = "smem";
1914                 qcom,xprt-linkid = <1>;
1915                 qcom,xprt-version = <1>;
1916                 qcom,fragmented-data;
1917         };
1918
1919         qcom,ipc_router_cdsp_xprt {
1920                 compatible = "qcom,ipc_router_glink_xprt";
1921                 qcom,ch-name = "IPCRTR";
1922                 qcom,xprt-remote = "cdsp";
1923                 qcom,glink-xprt = "smem";
1924                 qcom,xprt-linkid = <1>;
1925                 qcom,xprt-version = <1>;
1926                 qcom,fragmented-data;
1927         };
1928
1929         qcom,venus@cce0000 {
1930                 compatible = "qcom,pil-tz-generic";
1931                 reg = <0xcce0000 0x4000>;
1932
1933                 vdd-supply = <&gdsc_venus>;
1934                 qcom,proxy-reg-names = "vdd";
1935
1936                 clocks = <&clock_mmss MMSS_VIDEO_CORE_CLK>,
1937                         <&clock_mmss MMSS_MNOC_AHB_CLK>,
1938                         <&clock_mmss MMSS_VIDEO_AHB_CLK>,
1939                         <&clock_rpmcc MMSSNOC_AXI_CLK>,
1940                         <&clock_mmss MMSS_VIDEO_AXI_CLK>;
1941                 clock-names = "core_clk", "mnoc_ahb_clk", "iface_clk",
1942                         "noc_axi_clk", "bus_clk";
1943                 qcom,proxy-clock-names = "core_clk", "mnoc_ahb_clk",
1944                         "iface_clk", "noc_axi_clk", "bus_clk";
1945
1946                 qcom,msm-bus,name = "pil-venus";
1947                 qcom,msm-bus,num-cases = <2>;
1948                 qcom,msm-bus,num-paths = <1>;
1949                 qcom,msm-bus,vectors-KBps =
1950                                 <63 512 0 0>,
1951                                 <63 512 0 304000>;
1952
1953                 qcom,pas-id = <9>;
1954                 qcom,proxy-timeout-ms = <100>;
1955                 qcom,firmware-name = "venus";
1956                 memory-region = <&venus_fw_mem>;
1957                 status = "ok";
1958         };
1959
1960         qcom,icnss@18800000 {
1961                 compatible = "qcom,icnss";
1962                 reg = <0x18800000 0x800000>,
1963                       <0xa0000000 0x10000000>,
1964                       <0xb0000000 0x10000>;
1965                 reg-names = "membase", "smmu_iova_base", "smmu_iova_ipa";
1966                 iommus = <&anoc2_smmu 0x1a00>,
1967                          <&anoc2_smmu 0x1a01>;
1968                 clocks = <&clock_rpmcc RPM_RF_CLK1_PIN>;
1969                 clock-names = "cxo_ref_clk_pin";
1970                 interrupts = <0 413 0>,   /* CE0 */
1971                              <0 414 0>,   /* CE1 */
1972                              <0 415 0>,   /* CE2 */
1973                              <0 416 0>,   /* CE3 */
1974                              <0 417 0>,   /* CE4 */
1975                              <0 418 0>,   /* CE5 */
1976                              <0 420 0>,   /* CE6 */
1977                              <0 421 0>,   /* CE7 */
1978                              <0 422 0>,   /* CE8 */
1979                              <0 423 0>,   /* CE9 */
1980                              <0 424 0>,   /* CE10 */
1981                              <0 425 0>;   /* CE11 */
1982                 vdd-0.8-cx-mx-supply = <&pm660_l5>;
1983                 vdd-1.8-xo-supply = <&pm660_l9_pin_ctrl>;
1984                 vdd-1.3-rfa-supply = <&pm660_l6_pin_ctrl>;
1985                 vdd-3.3-ch0-supply = <&pm660_l19_pin_ctrl>;
1986                 qcom,vdd-0.8-cx-mx-config = <848000 848000>;
1987                 qcom,vdd-1.8-xo-config = <1750000 1900000>;
1988                 qcom,vdd-1.3-rfa-config = <1200000 1370000>;
1989                 qcom,vdd-3.3-ch0-config = <3200000 3400000>;
1990                 qcom,wlan-msa-memory = <0x100000>;
1991                 qcom,wlan-msa-fixed-region = <&wlan_msa_mem>;
1992                 qcom,smmu-s1-bypass;
1993         };
1994
1995         qcom,lpass@15700000 {
1996                 compatible = "qcom,pil-tz-generic";
1997                 reg = <0x15700000 0x00100>;
1998                 reg-names = "base_reg";
1999                 interrupts = <0 162 1>;
2000
2001                 vdd_cx-supply = <&pm660l_l9_level>;
2002                 qcom,proxy-reg-names = "vdd_cx";
2003                 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
2004
2005                 clocks = <&clock_rpmcc CXO_PIL_LPASS_CLK>;
2006                 clock-names = "xo";
2007                 qcom,proxy-clock-names = "xo";
2008
2009                 qcom,pas-id = <1>;
2010                 qcom,proxy-timeout-ms = <10000>;
2011                 qcom,smem-id = <423>;
2012                 qcom,sysmon-id = <1>;
2013                 qcom,ssctl-instance-id = <0x14>;
2014                 qcom,firmware-name = "adsp";
2015                 memory-region = <&adsp_fw_mem>;
2016
2017                 /* GPIO inputs from lpass */
2018                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_2_in 0 0>;
2019                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_2_in 2 0>;
2020                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_2_in 1 0>;
2021                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_2_in 3 0>;
2022
2023                 /* GPIO output to lpass */
2024                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_2_out 0 0>;
2025                 status = "ok";
2026         };
2027
2028         qcom,turing@1a300000 {
2029                 compatible = "qcom,pil-tz-generic";
2030                 reg = <0x1a300000 0x00100>;
2031                 reg-names = "base_reg";
2032                 interrupts = <0 518 1>;
2033
2034                 vdd_cx-supply = <&pm660l_s3_level>;
2035                 qcom,proxy-reg-names = "vdd_cx";
2036                 qcom,vdd_cx-uV-uA = <RPM_SMD_REGULATOR_LEVEL_TURBO 100000>;
2037
2038                 clocks = <&clock_rpmcc CXO_PIL_CDSP_CLK>;
2039                 clock-names = "xo";
2040                 qcom,proxy-clock-names = "xo";
2041
2042                 qcom,pas-id = <18>;
2043                 qcom,proxy-timeout-ms = <10000>;
2044                 qcom,smem-id = <601>;
2045                 qcom,sysmon-id = <7>;
2046                 qcom,ssctl-instance-id = <0x17>;
2047                 qcom,firmware-name = "cdsp";
2048                 memory-region = <&cdsp_fw_mem>;
2049
2050                 /* GPIO inputs from turing */
2051                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_5_in 0 0>;
2052                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_5_in 2 0>;
2053                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_5_in 1 0>;
2054                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_5_in 3 0>;
2055
2056                 /* GPIO output to turing*/
2057                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_5_out 0 0>;
2058                 status = "ok";
2059         };
2060
2061         pil_modem: qcom,mss@4080000 {
2062                 compatible = "qcom,pil-q6v55-mss";
2063                 reg = <0x4080000 0x100>,
2064                       <0x1f63000 0x008>,
2065                       <0x1f65000 0x008>,
2066                       <0x1f64000 0x008>,
2067                       <0x4180000 0x040>,
2068                       <0x00179000 0x004>,
2069                       <0x01fe5048 0x004>;
2070                 reg-names = "qdsp6_base", "halt_q6", "halt_modem",
2071                             "halt_nc", "rmb_base", "restart_reg",
2072                             "cxip_lm_vote_clear";
2073
2074                 clocks = <&clock_rpmcc RPM_XO_CLK_SRC>,
2075                          <&clock_gcc GCC_MSS_CFG_AHB_CLK>,
2076                          <&clock_gcc GCC_BIMC_MSS_Q6_AXI_CLK>,
2077                          <&clock_gcc GCC_BOOT_ROM_AHB_CLK>,
2078                          <&clock_gcc GPLL0_OUT_MSSCC>,
2079                          <&clock_gcc GCC_MSS_SNOC_AXI_CLK>,
2080                          <&clock_gcc GCC_MSS_MNOC_BIMC_AXI_CLK>,
2081                          <&clock_rpmcc RPM_QDSS_CLK>;
2082                 clock-names = "xo", "iface_clk", "bus_clk",
2083                               "mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
2084                               "mnoc_axi_clk", "qdss_clk";
2085                 qcom,proxy-clock-names = "xo", "qdss_clk";
2086                 qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
2087                                          "gpll0_mss_clk", "snoc_axi_clk",
2088                                          "mnoc_axi_clk";
2089
2090                 interrupts = <0 448 1>;
2091                 vdd_cx-supply = <&pm660l_s3_level>;
2092                 vdd_cx-voltage = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
2093                 vdd_mx-supply = <&pm660l_s5_level>;
2094                 vdd_mx-uV = <RPM_SMD_REGULATOR_LEVEL_TURBO>;
2095                 qcom,firmware-name = "modem";
2096                 qcom,pil-self-auth;
2097                 qcom,sysmon-id = <0>;
2098                 qcom,minidump-id = <0>;
2099                 qcom,ssctl-instance-id = <0x12>;
2100                 qcom,qdsp6v62-1-5;
2101                 memory-region = <&modem_fw_mem>;
2102                 qcom,mem-protect-id = <0xF>;
2103                 qcom,cx-ipeak-vote;
2104
2105                 /* GPIO inputs from mss */
2106                 qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
2107                 qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
2108                 qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
2109                 qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
2110                 qcom,gpio-shutdown-ack = <&smp2pgpio_ssr_smp2p_1_in 7 0>;
2111
2112                 /* GPIO output to mss */
2113                 qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
2114                 status = "ok";
2115                 qcom,mba-mem@0 {
2116                         compatible = "qcom,pil-mba-mem";
2117                         memory-region = <&pil_mba_mem>;
2118                 };
2119         };
2120
2121         qcom,msm-rtb {
2122                 compatible = "qcom,msm-rtb";
2123                 qcom,rtb-size = <0x100000>;
2124         };
2125
2126         qcom,mpm2-sleep-counter@10a3000 {
2127                 compatible = "qcom,mpm2-sleep-counter";
2128                 reg = <0x10a3000 0x1000>;
2129                 clock-frequency = <32768>;
2130         };
2131
2132         qcom,msm-imem@146bf000 {
2133                 compatible = "qcom,msm-imem";
2134                 reg = <0x146bf000 0x1000>;
2135                 ranges = <0x0 0x146bf000 0x1000>;
2136                 #address-cells = <1>;
2137                 #size-cells = <1>;
2138
2139                 mem_dump_table@10 {
2140                         compatible = "qcom,msm-imem-mem_dump_table";
2141                         reg = <0x10 8>;
2142                 };
2143
2144                 dload_type@1c {
2145                         compatible = "qcom,msm-imem-dload-type";
2146                         reg = <0x1c 4>;
2147                 };
2148
2149                 restart_reason@65c {
2150                         compatible = "qcom,msm-imem-restart_reason";
2151                         reg = <0x65c 4>;
2152                 };
2153
2154                 boot_stats@6b0 {
2155                         compatible = "qcom,msm-imem-boot_stats";
2156                         reg = <0x6b0 32>;
2157                 };
2158
2159                 kaslr_offset@6d0 {
2160                         compatible = "qcom,msm-imem-kaslr_offset";
2161                         reg = <0x6d0 12>;
2162                 };
2163
2164                 pil@94c {
2165                         compatible = "qcom,msm-imem-pil";
2166                         reg = <0x94c 200>;
2167                 };
2168
2169                 diag_dload@c8 {
2170                         compatible = "qcom,msm-imem-diag-dload";
2171                         reg = <0xc8 200>;
2172                 };
2173
2174                 ss_mdump@b88 {
2175                         compatible = "qcom,msm-imem-minidump";
2176                         reg = <0xb88 28>;
2177                 };
2178         };
2179
2180         qcom,ghd {
2181                 compatible = "qcom,gladiator-hang-detect";
2182                 qcom,threshold-arr = <0x179d141c 0x179d1420
2183                                       0x179d1424 0x179d1428
2184                                       0x179d142c 0x179d1430>;
2185                 qcom,config-reg = <0x179d1434>;
2186         };
2187
2188         qcom,msm-gladiator-v2@17900000 {
2189                 compatible = "qcom,msm-gladiator-v2";
2190                 reg = <0x17900000 0xe000>;
2191                 reg-names = "gladiator_base";
2192                 interrupts = <0 22 0>;
2193                 clock-names = "atb_clk";
2194                 clocks = <&clock_rpmcc RPM_QDSS_CLK>;
2195         };
2196
2197         cpu_pmu: cpu-pmu {
2198                 compatible = "arm,armv8-pmuv3";
2199                 qcom,irq-is-percpu;
2200                 interrupts = <1 6 4>;
2201         };
2202
2203         qcom_seecom: qseecom@86d00000 {
2204                 compatible = "qcom,qseecom";
2205                 reg = <0x86d00000 0x2200000>;
2206                 reg-names = "secapp-region";
2207                 qcom,hlos-num-ce-hw-instances = <1>;
2208                 qcom,hlos-ce-hw-instance = <0>;
2209                 qcom,qsee-ce-hw-instance = <0>;
2210                 qcom,disk-encrypt-pipe-pair = <2>;
2211                 qcom,support-fde;
2212                 qcom,fde-key-size;
2213                 qcom,no-clock-support;
2214                 qcom,msm-bus,name = "qseecom-noc";
2215                 qcom,msm-bus,num-cases = <4>;
2216                 qcom,msm-bus,num-paths = <1>;
2217                 qcom,msm-bus,vectors-KBps =
2218                         <55 512 0 0>,
2219                         <55 512 200000 400000>,
2220                         <55 512 300000 800000>,
2221                         <55 512 400000 1000000>;
2222                 clock-names = "core_clk_src", "core_clk",
2223                                 "iface_clk", "bus_clk";
2224                 clocks = <&clock_rpmcc QSEECOM_CE1_CLK>,
2225                         <&clock_rpmcc QSEECOM_CE1_CLK>,
2226                         <&clock_rpmcc QSEECOM_CE1_CLK>,
2227                         <&clock_rpmcc QSEECOM_CE1_CLK>;
2228                 qcom,ce-opp-freq = <171430000>;
2229                 qcom,qsee-reentrancy-support = <2>;
2230         };
2231
2232         qcom_cedev: qcedev@1de0000{
2233                 compatible = "qcom,qcedev";
2234                 reg = <0x1de0000 0x20000>,
2235                         <0x1dc4000 0x24000>;
2236                 reg-names = "crypto-base","crypto-bam-base";
2237                 interrupts = <0 206 0>;
2238                 qcom,bam-pipe-pair = <1>;
2239                 qcom,ce-hw-instance = <0>;
2240                 qcom,ce-device = <0>;
2241                 qcom,ce-hw-shared;
2242                 qcom,bam-ee = <0>;
2243                 qcom,msm-bus,name = "qcedev-noc";
2244                 qcom,msm-bus,num-cases = <2>;
2245                 qcom,msm-bus,num-paths = <1>;
2246                 qcom,msm-bus,vectors-KBps =
2247                                 <55 512 0 0>,
2248                                 <55 512 393600 393600>;
2249                 clock-names = "core_clk_src", "core_clk",
2250                                 "iface_clk", "bus_clk";
2251                 clocks = <&clock_rpmcc QCEDEV_CE1_CLK>,
2252                          <&clock_rpmcc QCEDEV_CE1_CLK>,
2253                          <&clock_rpmcc QCEDEV_CE1_CLK>,
2254                          <&clock_rpmcc QCEDEV_CE1_CLK>;
2255                 qcom,ce-opp-freq = <171430000>;
2256         };
2257
2258         qcom_crypto: qcrypto@1de0000 {
2259                 compatible = "qcom,qcrypto";
2260                 reg = <0x1de0000 0x20000>,
2261                          <0x1dc4000 0x24000>;
2262                 reg-names = "crypto-base","crypto-bam-base";
2263                 interrupts = <0 206 0>;
2264                 qcom,bam-pipe-pair = <2>;
2265                 qcom,ce-hw-instance = <0>;
2266                 qcom,ce-device = <0>;
2267                 qcom,bam-ee = <0>;
2268                 qcom,ce-hw-shared;
2269                 qcom,clk-mgmt-sus-res;
2270                 qcom,msm-bus,name = "qcrypto-noc";
2271                 qcom,msm-bus,num-cases = <2>;
2272                 qcom,msm-bus,num-paths = <1>;
2273                 qcom,msm-bus,vectors-KBps =
2274                         <55 512 0 0>,
2275                         <55 512 393600 393600>;
2276                 clock-names = "core_clk_src", "core_clk",
2277                                 "iface_clk", "bus_clk";
2278                 clocks = <&clock_rpmcc QCRYPTO_CE1_CLK>,
2279                          <&clock_rpmcc QCRYPTO_CE1_CLK>,
2280                          <&clock_rpmcc QCRYPTO_CE1_CLK>,
2281                          <&clock_rpmcc QCRYPTO_CE1_CLK>;
2282                 qcom,ce-opp-freq = <171430000>;
2283                 qcom,use-sw-aes-cbc-ecb-ctr-algo;
2284                 qcom,use-sw-aes-xts-algo;
2285                 qcom,use-sw-aes-ccm-algo;
2286                 qcom,use-sw-ahash-algo;
2287                 qcom,use-sw-aead-algo;
2288                 qcom,use-sw-hmac-algo;
2289         };
2290
2291         qcom_tzlog: tz-log@146bf720 {
2292                 compatible = "qcom,tz-log";
2293                 reg = <0x146bf720 0x3000>;
2294                 qcom,hyplog-enabled;
2295                 hyplog-address-offset = <0x410>;
2296                 hyplog-size-offset = <0x414>;
2297         };
2298
2299         qcom_rng: qrng@793000 {
2300                 compatible = "qcom,msm-rng";
2301                 reg = <0x793000 0x1000>;
2302                 qcom,msm-rng-iface-clk;
2303                 qcom,no-qrng-config;
2304                 qcom,msm-bus,name = "msm-rng-noc";
2305                 qcom,msm-bus,num-cases = <2>;
2306                 qcom,msm-bus,num-paths = <1>;
2307                 qcom,msm-bus,vectors-KBps =
2308                         <1 618 0 0>,    /* No vote */
2309                         <1 618 0 800>;  /* 100 KHz */
2310                 clocks = <&clock_gcc GCC_PRNG_AHB_CLK>;
2311                 clock-names = "iface_clk";
2312         };
2313
2314         qcom,chd_silver {
2315                 compatible = "qcom,core-hang-detect";
2316                 label = "silver";
2317                 qcom,threshold-arr = <0x179880b0 0x179980b0
2318                                       0x179a80b0 0x179b80b0>;
2319                 qcom,config-arr = <0x179880b8 0x179980b8
2320                                    0x179a80b8 0x179b80b8>;
2321         };
2322
2323         qcom,chd_gold {
2324                 compatible = "qcom,core-hang-detect";
2325                 label = "gold";
2326                 qcom,threshold-arr = <0x178880b0 0x178980b0
2327                                       0x178a80b0 0x178b80b0>;
2328                 qcom,config-arr = <0x178880b8  0x178980b8
2329                                    0x178a80b8  0x178b80b8>;
2330         };
2331
2332         ufsphy1: ufsphy@1da7000 {
2333                 compatible = "qcom,ufs-phy-qmp-v3-660";
2334                 reg = <0x1da7000 0xdb8>;
2335                 reg-names = "phy_mem";
2336                 #phy-cells = <0>;
2337                 clock-names = "ref_clk_src",
2338                         "ref_clk",
2339                         "ref_aux_clk";
2340                 clocks = <&clock_rpmcc RPM_LN_BB_CLK1>,
2341                         <&clock_gcc GCC_UFS_CLKREF_CLK>,
2342                         <&clock_gcc GCC_UFS_PHY_AUX_CLK>;
2343                 status = "disabled";
2344         };
2345
2346         ufs1: ufshc@1da4000 {
2347                 compatible = "qcom,ufshc";
2348                 reg = <0x1da4000 0x3000>;
2349                 interrupts = <0 265 0>;
2350                 phys = <&ufsphy1>;
2351                 phy-names = "ufsphy";
2352                 ufs-qcom-crypto = <&ufs_ice>;
2353
2354                 clock-names =
2355                         "core_clk",
2356                         "bus_aggr_clk",
2357                         "iface_clk",
2358                         "core_clk_unipro",
2359                         "core_clk_ice",
2360                         "ref_clk",
2361                         "tx_lane0_sync_clk",
2362                         "rx_lane0_sync_clk";
2363                 clocks =
2364                         <&clock_gcc GCC_UFS_AXI_CLK>,
2365                         <&clock_gcc GCC_AGGRE2_UFS_AXI_CLK>,
2366                         <&clock_gcc GCC_UFS_AHB_CLK>,
2367                         <&clock_gcc GCC_UFS_UNIPRO_CORE_CLK>,
2368                         <&clock_gcc GCC_UFS_ICE_CORE_CLK>,
2369                         <&clock_rpmcc RPM_LN_BB_CLK1>,
2370                         <&clock_gcc GCC_UFS_TX_SYMBOL_0_CLK>,
2371                         <&clock_gcc GCC_UFS_RX_SYMBOL_0_CLK>;
2372                 freq-table-hz =
2373                         <50000000 200000000>,
2374                         <0 0>,
2375                         <0 0>,
2376                         <37500000 150000000>,
2377                         <75000000 300000000>,
2378                         <0 0>,
2379                         <0 0>,
2380                         <0 0>;
2381
2382                 lanes-per-direction = <1>;
2383                 spm-level = <5>;
2384
2385                 non-removable;
2386                 qcom,msm-bus,name = "ufs1";
2387                 qcom,msm-bus,num-cases = <12>;
2388                 qcom,msm-bus,num-paths = <2>;
2389                 qcom,msm-bus,vectors-KBps =
2390                 <95 512 0 0>, <1 650 0 0>,          /* No vote */
2391                 <95 512 922 0>, <1 650 1000 0>,     /* PWM G1 */
2392                 <95 512 1844 0>, <1 650 1000 0>,    /* PWM G2 */
2393                 <95 512 3688 0>, <1 650 1000 0>,    /* PWM G3 */
2394                 <95 512 7376 0>, <1 650 1000 0>,    /* PWM G4 */
2395                 <95 512 127796 0>, <1 650 1000 0>,  /* HS G1 RA */
2396                 <95 512 255591 0>, <1 650 1000 0>,  /* HS G2 RA */
2397                 <95 512 2097152 0>, <1 650 102400 0>,  /* HS G3 RA */
2398                 <95 512 149422 0>, <1 650 1000 0>,  /* HS G1 RB */
2399                 <95 512 298189 0>, <1 650 1000 0>,  /* HS G2 RB */
2400                 <95 512 2097152 0>, <1 650 102400 0>,  /* HS G3 RB */
2401                 <95 512 7643136 0>, <1 650 307200 0>; /* Max. bandwidth */
2402                 qcom,bus-vector-names = "MIN",
2403                 "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
2404                 "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
2405                 "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
2406                 "MAX";
2407
2408                 resets = <&clock_gcc GCC_UFS_BCR>;
2409                 reset-names = "core_reset";
2410
2411                 status = "disabled";
2412         };
2413
2414         jtag_fuse: jtagfuse@786040 {
2415                 compatible = "qcom,jtag-fuse-v4";
2416                 reg = <0x786040 0x8>;
2417                 reg-names = "fuse-base";
2418         };
2419
2420         jtag_mm0: jtagmm@7840000 {
2421                 compatible = "qcom,jtagv8-mm";
2422                 reg = <0x7840000 0x1000>;
2423                 reg-names = "etm-base";
2424
2425                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2426                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2427                 clock-names = "core_clk", "core_a_clk";
2428
2429                 qcom,coresight-jtagmm-cpu = <&CPU0>;
2430         };
2431
2432         jtag_mm1: jtagmm@7940000 {
2433                 compatible = "qcom,jtagv8-mm";
2434                 reg = <0x7940000 0x1000>;
2435                 reg-names = "etm-base";
2436
2437                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2438                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2439                 clock-names = "core_clk", "core_a_clk";
2440
2441                 qcom,coresight-jtagmm-cpu = <&CPU1>;
2442         };
2443
2444         jtag_mm2: jtagmm@7a40000 {
2445                 compatible = "qcom,jtagv8-mm";
2446                 reg = <0x7a40000 0x1000>;
2447                 reg-names = "etm-base";
2448
2449                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2450                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2451                 clock-names = "core_clk", "core_a_clk";
2452
2453                 qcom,coresight-jtagmm-cpu = <&CPU2>;
2454         };
2455
2456         jtag_mm3: jtagmm@7b40000 {
2457                 compatible = "qcom,jtagv8-mm";
2458                 reg = <0x7b40000 0x1000>;
2459                 reg-names = "etm-base";
2460
2461                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2462                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2463                 clock-names = "core_clk", "core_a_clk";
2464
2465                 qcom,coresight-jtagmm-cpu = <&CPU3>;
2466         };
2467
2468         jtag_mm4: jtagmm@7c40000 {
2469                 compatible = "qcom,jtagv8-mm";
2470                 reg = <0x7c40000 0x1000>;
2471                 reg-names = "etm-base";
2472
2473                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2474                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2475                 clock-names = "core_clk", "core_a_clk";
2476
2477                 qcom,coresight-jtagmm-cpu = <&CPU4>;
2478         };
2479
2480         jtag_mm5: jtagmm@7d40000 {
2481                 compatible = "qcom,jtagv8-mm";
2482                 reg = <0x7d40000 0x1000>;
2483                 reg-names = "etm-base";
2484
2485                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2486                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2487                 clock-names = "core_clk", "core_a_clk";
2488
2489                 qcom,coresight-jtagmm-cpu = <&CPU5>;
2490         };
2491
2492         jtag_mm6: jtagmm@7e40000 {
2493                 compatible = "qcom,jtagv8-mm";
2494                 reg = <0x7e40000 0x1000>;
2495                 reg-names = "etm-base";
2496
2497                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2498                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2499                 clock-names = "core_clk", "core_a_clk";
2500
2501                 qcom,coresight-jtagmm-cpu = <&CPU6>;
2502         };
2503
2504         jtag_mm7: jtagmm@7f40000 {
2505                 compatible = "qcom,jtagv8-mm";
2506                 reg = <0x7f40000 0x1000>;
2507                 reg-names = "etm-base";
2508
2509                 clocks = <&clock_rpmcc RPM_QDSS_CLK>,
2510                          <&clock_rpmcc RPM_QDSS_A_CLK>;
2511                 clock-names = "core_clk", "core_a_clk";
2512
2513                 qcom,coresight-jtagmm-cpu = <&CPU7>;
2514         };
2515 };
2516
2517 #include "sdm660-ion.dtsi"
2518 #include "sdm660-bus.dtsi"
2519 #include "msm-pm660.dtsi"
2520 #include "msm-pm660l.dtsi"
2521 #include "msm-pm660-rpm-regulator.dtsi"
2522 #include "msm-pm660l-rpm-regulator.dtsi"
2523 #include "sdm660-regulator.dtsi"
2524 #include "msm-gdsc-660.dtsi"
2525 #include "sdm660-gpu.dtsi"
2526 #include "sdm660-pm.dtsi"
2527
2528 &gdsc_usb30 {
2529         status = "ok";
2530 };
2531
2532 &gdsc_ufs {
2533         status = "ok";
2534 };
2535
2536 &gdsc_bimc_smmu {
2537         clock-names = "bus_clk";
2538         clocks = <&clock_mmss MMSS_BIMC_SMMU_AXI_CLK>;
2539         proxy-supply = <&gdsc_bimc_smmu>;
2540         qcom,proxy-consumer-enable;
2541         status = "ok";
2542 };
2543
2544 &gdsc_hlos1_vote_lpass_adsp {
2545         status = "ok";
2546 };
2547
2548 &gdsc_hlos1_vote_turing_adsp {
2549         status = "ok";
2550 };
2551
2552 &gdsc_hlos2_vote_turing_adsp {
2553         status = "ok";
2554 };
2555
2556 &gdsc_venus {
2557         status = "ok";
2558 };
2559
2560 &gdsc_venus_core0 {
2561         qcom,support-hw-trigger;
2562         status = "ok";
2563 };
2564
2565 &gdsc_camss_top {
2566         status = "ok";
2567 };
2568
2569 &gdsc_vfe0 {
2570         parent-supply = <&gdsc_camss_top>;
2571         status = "ok";
2572 };
2573
2574 &gdsc_vfe1 {
2575         parent-supply = <&gdsc_camss_top>;
2576         status = "ok";
2577 };
2578
2579 &gdsc_cpp {
2580         parent-supply = <&gdsc_camss_top>;
2581         qcom,support-hw-trigger;
2582         status = "ok";
2583 };
2584
2585 &gdsc_mdss {
2586         proxy-supply = <&gdsc_mdss>;
2587         qcom,proxy-consumer-enable;
2588         status = "ok";
2589 };
2590
2591 &gdsc_gpu_gx {
2592         clock-names = "core_root_clk";
2593         clocks = <&clock_gfx GFX3D_CLK_SRC>;
2594         qcom,force-enable-root-clk;
2595         parent-supply = <&gfx_vreg_corner>;
2596         status = "ok";
2597 };
2598
2599 &gdsc_gpu_cx {
2600         status = "ok";
2601 };
2602
2603 &clock_cpu {
2604         lmh_dcvs0: qcom,limits-dcvs@0 {
2605                 compatible = "qcom,msm-hw-limits";
2606                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
2607         };
2608
2609         lmh_dcvs1: qcom,limits-dcvs@1 {
2610                 compatible = "qcom,msm-hw-limits";
2611                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2612         };
2613 };
2614
2615 #include "msm-arm-smmu-660.dtsi"
2616 #include "msm-arm-smmu-impl-defs-660.dtsi"
2617 #include "sdm660-common.dtsi"
2618 #include "sdm660-blsp.dtsi"
2619 #include "msm-rdbg.dtsi"
2620 #include "sdm660-camera.dtsi"
2621 #include "sdm660-vidc.dtsi"
2622 #include "msm-audio.dtsi"
2623 #include "sdm660-audio.dtsi"
2624
2625 &pm660l_gpios {
2626         /* GPIO 7 for VOL_UP */
2627         gpio@c600 {
2628                 status = "okay";
2629                 qcom,mode = <0>;
2630                 qcom,pull = <0>;
2631                 qcom,vin-sel = <0>;
2632                 qcom,src-sel = <0>;
2633                 qcom,out-strength = <1>;
2634         };
2635 };
2636
2637 &msm_vidc {
2638         qcom,cx-ipeak-data = <&cx_ipeak_lm 4>;
2639         qcom,clock-freq-threshold = <518400000>;
2640 };
2641
2642 &soc {
2643         gpio_keys {
2644                 status = "okay";
2645                 compatible = "gpio-keys";
2646                 input-name = "gpio-keys";
2647                 pinctrl-names = "tlmm_gpio_key_active","tlmm_gpio_key_suspend";
2648                 pinctrl-0 = <&gpio_key_active>;
2649                 pinctrl-1 = <&gpio_key_suspend>;
2650
2651                 camera_focus {
2652                         label = "camera_focus";
2653                         gpios = <&tlmm 64 0x1>;
2654                         linux,input-type = <1>;
2655                         linux,code = <0x210>;
2656                         debounce-interval = <15>;
2657                 };
2658
2659                 camera_snapshot {
2660                         label = "camera_snapshot";
2661                         gpios = <&tlmm 113 0x1>;
2662                         linux,input-type = <1>;
2663                         linux,code = <0x2fe>;
2664                         debounce-interval = <15>;
2665                 };
2666
2667                 vol_up {
2668                         label = "volume_up";
2669                         gpios = <&pm660l_gpios 7 0x1>;
2670                         linux,input-type = <1>;
2671                         linux,code = <115>;
2672                         gpio-key,wakeup;
2673                         debounce-interval = <15>;
2674                 };
2675         };
2676 };
2677
2678 &blsp2_uart1_hs {
2679         status = "ok";
2680 };
2681
2682 #include "sdm660-mdss.dtsi"
2683 #include "sdm660-mdss-pll.dtsi"