arch/arm/boot/dts/r8a7792.dtsi

   1 /*
   2  * Device Tree Source for the r8a7792 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
  12 #include <dt-bindings/interrupt-controller/irq.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/power/r8a7792-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7792";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 i2c0 = &i2c0;
  23                 i2c1 = &i2c1;
  24                 i2c2 = &i2c2;
  25                 i2c3 = &i2c3;
  26                 i2c4 = &i2c4;
  27                 i2c5 = &i2c5;
  28                 spi0 = &qspi;
  29                 spi1 = &msiof0;
  30                 spi2 = &msiof1;
  31                 vin0 = &vin0;
  32                 vin1 = &vin1;
  33                 vin2 = &vin2;
  34                 vin3 = &vin3;
  35                 vin4 = &vin4;
  36                 vin5 = &vin5;
  37         };
  38
  39         /* External CAN clock */
  40         can_clk: can {
  41                 compatible = "fixed-clock";
  42                 #clock-cells = <0>;
  43                 /* This value must be overridden by the board. */
  44                 clock-frequency = <0>;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50                 enable-method = "renesas,apmu";
  51
  52                 cpu0: cpu@0 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <0>;
  56                         clock-frequency = <1000000000>;
  57                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  58                         power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
  59                         next-level-cache = <&L2_CA15>;
  60                 };
  61
  62                 cpu1: cpu@1 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a15";
  65                         reg = <1>;
  66                         clock-frequency = <1000000000>;
  67                         clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
  68                         power-domains = <&sysc R8A7792_PD_CA15_CPU1>;
  69                         next-level-cache = <&L2_CA15>;
  70                 };
  71
  72                 L2_CA15: cache-controller-0 {
  73                         compatible = "cache";
  74                         cache-unified;
  75                         cache-level = <2>;
  76                         power-domains = <&sysc R8A7792_PD_CA15_SCU>;
  77                 };
  78         };
  79
  80         /* External root clock */
  81         extal_clk: extal {
  82                 compatible = "fixed-clock";
  83                 #clock-cells = <0>;
  84                 /* This value must be overridden by the board. */
  85                 clock-frequency = <0>;
  86         };
  87
  88         /* External SCIF clock */
  89         scif_clk: scif {
  90                 compatible = "fixed-clock";
  91                 #clock-cells = <0>;
  92                 /* This value must be overridden by the board. */
  93                 clock-frequency = <0>;
  94         };
  95
  96         soc {
  97                 compatible = "simple-bus";
  98                 interrupt-parent = <&gic>;
  99
 100                 #address-cells = <2>;
 101                 #size-cells = <2>;
 102                 ranges;
 103
 104                 apmu@e6152000 {
 105                         compatible = "renesas,r8a7792-apmu", "renesas,apmu";
 106                         reg = <0 0xe6152000 0 0x188>;
 107                         cpus = <&cpu0 &cpu1>;
 108                 };
 109
 110                 gic: interrupt-controller@f1001000 {
 111                         compatible = "arm,gic-400";
 112                         #interrupt-cells = <3>;
 113                         interrupt-controller;
 114                         reg = <0 0xf1001000 0 0x1000>,
 115                               <0 0xf1002000 0 0x2000>,
 116                               <0 0xf1004000 0 0x2000>,
 117                               <0 0xf1006000 0 0x2000>;
 118                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
 119                                       IRQ_TYPE_LEVEL_HIGH)>;
 120                         clocks = <&cpg CPG_MOD 408>;
 121                         clock-names = "clk";
 122                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 123                         resets = <&cpg 408>;
 124                 };
 125
 126                 irqc: interrupt-controller@e61c0000 {
 127                         compatible = "renesas,irqc-r8a7792", "renesas,irqc";
 128                         #interrupt-cells = <2>;
 129                         interrupt-controller;
 130                         reg = <0 0xe61c0000 0 0x200>;
 131                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 132                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 133                                      <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 134                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 135                         clocks = <&cpg CPG_MOD 407>;
 136                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 137                         resets = <&cpg 407>;
 138                 };
 139
 140                 timer {
 141                         compatible = "arm,armv7-timer";
 142                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
 143                                       IRQ_TYPE_LEVEL_LOW)>,
 144                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
 145                                       IRQ_TYPE_LEVEL_LOW)>,
 146                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
 147                                       IRQ_TYPE_LEVEL_LOW)>,
 148                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
 149                                       IRQ_TYPE_LEVEL_LOW)>;
 150                 };
 151
 152                 rst: reset-controller@e6160000 {
 153                         compatible = "renesas,r8a7792-rst";
 154                         reg = <0 0xe6160000 0 0x0100>;
 155                 };
 156
 157                 prr: chipid@ff000044 {
 158                         compatible = "renesas,prr";
 159                         reg = <0 0xff000044 0 4>;
 160                 };
 161
 162                 sysc: system-controller@e6180000 {
 163                         compatible = "renesas,r8a7792-sysc";
 164                         reg = <0 0xe6180000 0 0x0200>;
 165                         #power-domain-cells = <1>;
 166                 };
 167
 168                 pfc: pin-controller@e6060000 {
 169                         compatible = "renesas,pfc-r8a7792";
 170                         reg = <0 0xe6060000 0 0x144>;
 171                 };
 172
 173                 gpio0: gpio@e6050000 {
 174                         compatible = "renesas,gpio-r8a7792",
 175                                      "renesas,rcar-gen2-gpio";
 176                         reg = <0 0xe6050000 0 0x50>;
 177                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 178                         #gpio-cells = <2>;
 179                         gpio-controller;
 180                         gpio-ranges = <&pfc 0 0 29>;
 181                         #interrupt-cells = <2>;
 182                         interrupt-controller;
 183                         clocks = <&cpg CPG_MOD 912>;
 184                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 185                         resets = <&cpg 912>;
 186                 };
 187
 188                 gpio1: gpio@e6051000 {
 189                         compatible = "renesas,gpio-r8a7792",
 190                                      "renesas,rcar-gen2-gpio";
 191                         reg = <0 0xe6051000 0 0x50>;
 192                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 193                         #gpio-cells = <2>;
 194                         gpio-controller;
 195                         gpio-ranges = <&pfc 0 32 23>;
 196                         #interrupt-cells = <2>;
 197                         interrupt-controller;
 198                         clocks = <&cpg CPG_MOD 911>;
 199                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 200                         resets = <&cpg 911>;
 201                 };
 202
 203                 gpio2: gpio@e6052000 {
 204                         compatible = "renesas,gpio-r8a7792",
 205                                      "renesas,rcar-gen2-gpio";
 206                         reg = <0 0xe6052000 0 0x50>;
 207                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 208                         #gpio-cells = <2>;
 209                         gpio-controller;
 210                         gpio-ranges = <&pfc 0 64 32>;
 211                         #interrupt-cells = <2>;
 212                         interrupt-controller;
 213                         clocks = <&cpg CPG_MOD 910>;
 214                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 215                         resets = <&cpg 910>;
 216                 };
 217
 218                 gpio3: gpio@e6053000 {
 219                         compatible = "renesas,gpio-r8a7792",
 220                                      "renesas,rcar-gen2-gpio";
 221                         reg = <0 0xe6053000 0 0x50>;
 222                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 223                         #gpio-cells = <2>;
 224                         gpio-controller;
 225                         gpio-ranges = <&pfc 0 96 28>;
 226                         #interrupt-cells = <2>;
 227                         interrupt-controller;
 228                         clocks = <&cpg CPG_MOD 909>;
 229                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 230                         resets = <&cpg 909>;
 231                 };
 232
 233                 gpio4: gpio@e6054000 {
 234                         compatible = "renesas,gpio-r8a7792",
 235                                      "renesas,rcar-gen2-gpio";
 236                         reg = <0 0xe6054000 0 0x50>;
 237                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 238                         #gpio-cells = <2>;
 239                         gpio-controller;
 240                         gpio-ranges = <&pfc 0 128 17>;
 241                         #interrupt-cells = <2>;
 242                         interrupt-controller;
 243                         clocks = <&cpg CPG_MOD 908>;
 244                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 245                         resets = <&cpg 908>;
 246                 };
 247
 248                 gpio5: gpio@e6055000 {
 249                         compatible = "renesas,gpio-r8a7792",
 250                                      "renesas,rcar-gen2-gpio";
 251                         reg = <0 0xe6055000 0 0x50>;
 252                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 253                         #gpio-cells = <2>;
 254                         gpio-controller;
 255                         gpio-ranges = <&pfc 0 160 17>;
 256                         #interrupt-cells = <2>;
 257                         interrupt-controller;
 258                         clocks = <&cpg CPG_MOD 907>;
 259                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 260                         resets = <&cpg 907>;
 261                 };
 262
 263                 gpio6: gpio@e6055100 {
 264                         compatible = "renesas,gpio-r8a7792",
 265                                      "renesas,rcar-gen2-gpio";
 266                         reg = <0 0xe6055100 0 0x50>;
 267                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 268                         #gpio-cells = <2>;
 269                         gpio-controller;
 270                         gpio-ranges = <&pfc 0 192 17>;
 271                         #interrupt-cells = <2>;
 272                         interrupt-controller;
 273                         clocks = <&cpg CPG_MOD 905>;
 274                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 275                         resets = <&cpg 905>;
 276                 };
 277
 278                 gpio7: gpio@e6055200 {
 279                         compatible = "renesas,gpio-r8a7792",
 280                                      "renesas,rcar-gen2-gpio";
 281                         reg = <0 0xe6055200 0 0x50>;
 282                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 283                         #gpio-cells = <2>;
 284                         gpio-controller;
 285                         gpio-ranges = <&pfc 0 224 17>;
 286                         #interrupt-cells = <2>;
 287                         interrupt-controller;
 288                         clocks = <&cpg CPG_MOD 904>;
 289                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 290                         resets = <&cpg 904>;
 291                 };
 292
 293                 gpio8: gpio@e6055300 {
 294                         compatible = "renesas,gpio-r8a7792",
 295                                      "renesas,rcar-gen2-gpio";
 296                         reg = <0 0xe6055300 0 0x50>;
 297                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 298                         #gpio-cells = <2>;
 299                         gpio-controller;
 300                         gpio-ranges = <&pfc 0 256 17>;
 301                         #interrupt-cells = <2>;
 302                         interrupt-controller;
 303                         clocks = <&cpg CPG_MOD 921>;
 304                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 305                         resets = <&cpg 921>;
 306                 };
 307
 308                 gpio9: gpio@e6055400 {
 309                         compatible = "renesas,gpio-r8a7792",
 310                                      "renesas,rcar-gen2-gpio";
 311                         reg = <0 0xe6055400 0 0x50>;
 312                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 313                         #gpio-cells = <2>;
 314                         gpio-controller;
 315                         gpio-ranges = <&pfc 0 288 17>;
 316                         #interrupt-cells = <2>;
 317                         interrupt-controller;
 318                         clocks = <&cpg CPG_MOD 919>;
 319                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 320                         resets = <&cpg 919>;
 321                 };
 322
 323                 gpio10: gpio@e6055500 {
 324                         compatible = "renesas,gpio-r8a7792",
 325                                      "renesas,rcar-gen2-gpio";
 326                         reg = <0 0xe6055500 0 0x50>;
 327                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 328                         #gpio-cells = <2>;
 329                         gpio-controller;
 330                         gpio-ranges = <&pfc 0 320 32>;
 331                         #interrupt-cells = <2>;
 332                         interrupt-controller;
 333                         clocks = <&cpg CPG_MOD 914>;
 334                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 335                         resets = <&cpg 914>;
 336                 };
 337
 338                 gpio11: gpio@e6055600 {
 339                         compatible = "renesas,gpio-r8a7792",
 340                                      "renesas,rcar-gen2-gpio";
 341                         reg = <0 0xe6055600 0 0x50>;
 342                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 343                         #gpio-cells = <2>;
 344                         gpio-controller;
 345                         gpio-ranges = <&pfc 0 352 30>;
 346                         #interrupt-cells = <2>;
 347                         interrupt-controller;
 348                         clocks = <&cpg CPG_MOD 913>;
 349                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 350                         resets = <&cpg 913>;
 351                 };
 352
 353                 dmac0: dma-controller@e6700000 {
 354                         compatible = "renesas,dmac-r8a7792",
 355                                      "renesas,rcar-dmac";
 356                         reg = <0 0xe6700000 0 0x20000>;
 357                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 358                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 359                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 360                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 361                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 362                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 363                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 364                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 365                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 366                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 367                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 368                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 369                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 370                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 371                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 372                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 373                         interrupt-names = "error",
 374                                           "ch0", "ch1", "ch2", "ch3",
 375                                           "ch4", "ch5", "ch6", "ch7",
 376                                           "ch8", "ch9", "ch10", "ch11",
 377                                           "ch12", "ch13", "ch14";
 378                         clocks = <&cpg CPG_MOD 219>;
 379                         clock-names = "fck";
 380                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 381                         resets = <&cpg 219>;
 382                         #dma-cells = <1>;
 383                         dma-channels = <15>;
 384                 };
 385
 386                 dmac1: dma-controller@e6720000 {
 387                         compatible = "renesas,dmac-r8a7792",
 388                                      "renesas,rcar-dmac";
 389                         reg = <0 0xe6720000 0 0x20000>;
 390                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 391                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 392                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 393                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 394                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 395                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 396                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 397                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 398                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 399                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 400                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 401                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 402                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 403                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 404                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 405                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 406                         interrupt-names = "error",
 407                                           "ch0", "ch1", "ch2", "ch3",
 408                                           "ch4", "ch5", "ch6", "ch7",
 409                                           "ch8", "ch9", "ch10", "ch11",
 410                                           "ch12", "ch13", "ch14";
 411                         clocks = <&cpg CPG_MOD 218>;
 412                         clock-names = "fck";
 413                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 414                         resets = <&cpg 218>;
 415                         #dma-cells = <1>;
 416                         dma-channels = <15>;
 417                 };
 418
 419                 scif0: serial@e6e60000 {
 420                         compatible = "renesas,scif-r8a7792",
 421                                      "renesas,rcar-gen2-scif", "renesas,scif";
 422                         reg = <0 0xe6e60000 0 64>;
 423                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 424                         clocks = <&cpg CPG_MOD 721>,
 425                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 426                         clock-names = "fck", "brg_int", "scif_clk";
 427                         dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
 428                                <&dmac1 0x29>, <&dmac1 0x2a>;
 429                         dma-names = "tx", "rx", "tx", "rx";
 430                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 431                         resets = <&cpg 721>;
 432                         status = "disabled";
 433                 };
 434
 435                 scif1: serial@e6e68000 {
 436                         compatible = "renesas,scif-r8a7792",
 437                                      "renesas,rcar-gen2-scif", "renesas,scif";
 438                         reg = <0 0xe6e68000 0 64>;
 439                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&cpg CPG_MOD 720>,
 441                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 442                         clock-names = "fck", "brg_int", "scif_clk";
 443                         dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
 444                                <&dmac1 0x2d>, <&dmac1 0x2e>;
 445                         dma-names = "tx", "rx", "tx", "rx";
 446                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 447                         resets = <&cpg 720>;
 448                         status = "disabled";
 449                 };
 450
 451                 scif2: serial@e6e58000 {
 452                         compatible = "renesas,scif-r8a7792",
 453                                      "renesas,rcar-gen2-scif", "renesas,scif";
 454                         reg = <0 0xe6e58000 0 64>;
 455                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 456                         clocks = <&cpg CPG_MOD 719>,
 457                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 458                         clock-names = "fck", "brg_int", "scif_clk";
 459                         dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
 460                                <&dmac1 0x2b>, <&dmac1 0x2c>;
 461                         dma-names = "tx", "rx", "tx", "rx";
 462                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 463                         resets = <&cpg 719>;
 464                         status = "disabled";
 465                 };
 466
 467                 scif3: serial@e6ea8000 {
 468                         compatible = "renesas,scif-r8a7792",
 469                                      "renesas,rcar-gen2-scif", "renesas,scif";
 470                         reg = <0 0xe6ea8000 0 64>;
 471                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&cpg CPG_MOD 718>,
 473                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 474                         clock-names = "fck", "brg_int", "scif_clk";
 475                         dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
 476                                <&dmac1 0x2f>, <&dmac1 0x30>;
 477                         dma-names = "tx", "rx", "tx", "rx";
 478                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 479                         resets = <&cpg 718>;
 480                         status = "disabled";
 481                 };
 482
 483                 hscif0: serial@e62c0000 {
 484                         compatible = "renesas,hscif-r8a7792",
 485                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 486                         reg = <0 0xe62c0000 0 96>;
 487                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 488                         clocks = <&cpg CPG_MOD 717>,
 489                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 490                         clock-names = "fck", "brg_int", "scif_clk";
 491                         dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
 492                                <&dmac1 0x39>, <&dmac1 0x3a>;
 493                         dma-names = "tx", "rx", "tx", "rx";
 494                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 495                         resets = <&cpg 717>;
 496                         status = "disabled";
 497                 };
 498
 499                 hscif1: serial@e62c8000 {
 500                         compatible = "renesas,hscif-r8a7792",
 501                                      "renesas,rcar-gen2-hscif", "renesas,hscif";
 502                         reg = <0 0xe62c8000 0 96>;
 503                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 504                         clocks = <&cpg CPG_MOD 716>,
 505                                  <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
 506                         clock-names = "fck", "brg_int", "scif_clk";
 507                         dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
 508                                <&dmac1 0x4d>, <&dmac1 0x4e>;
 509                         dma-names = "tx", "rx", "tx", "rx";
 510                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 511                         resets = <&cpg 716>;
 512                         status = "disabled";
 513                 };
 514
 515                 icram0: sram@e63a0000 {
 516                         compatible = "mmio-sram";
 517                         reg = <0 0xe63a0000 0 0x12000>;
 518                 };
 519
 520                 icram1: sram@e63c0000 {
 521                         compatible = "mmio-sram";
 522                         reg = <0 0xe63c0000 0 0x1000>;
 523                         #address-cells = <1>;
 524                         #size-cells = <1>;
 525                         ranges = <0 0 0xe63c0000 0x1000>;
 526
 527                         smp-sram@0 {
 528                                 compatible = "renesas,smp-sram";
 529                                 reg = <0 0x10>;
 530                         };
 531                 };
 532
 533                 sdhi0: sd@ee100000 {
 534                         compatible = "renesas,sdhi-r8a7792",
 535                                      "renesas,rcar-gen2-sdhi";
 536                         reg = <0 0xee100000 0 0x328>;
 537                         interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
 538                         dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
 539                                <&dmac1 0xcd>, <&dmac1 0xce>;
 540                         dma-names = "tx", "rx", "tx", "rx";
 541                         clocks = <&cpg CPG_MOD 314>;
 542                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 543                         resets = <&cpg 314>;
 544                         status = "disabled";
 545                 };
 546
 547                 jpu: jpeg-codec@fe980000 {
 548                         compatible = "renesas,jpu-r8a7792",
 549                                      "renesas,rcar-gen2-jpu";
 550                         reg = <0 0xfe980000 0 0x10300>;
 551                         interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
 552                         clocks = <&cpg CPG_MOD 106>;
 553                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 554                         resets = <&cpg 106>;
 555                 };
 556
 557                 avb: ethernet@e6800000 {
 558                         compatible = "renesas,etheravb-r8a7792",
 559                                      "renesas,etheravb-rcar-gen2";
 560                         reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
 561                         interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
 562                         clocks = <&cpg CPG_MOD 812>;
 563                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 564                         resets = <&cpg 812>;
 565                         #address-cells = <1>;
 566                         #size-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 /* I2C doesn't need pinmux */
 571                 i2c0: i2c@e6508000 {
 572                         compatible = "renesas,i2c-r8a7792",
 573                                      "renesas,rcar-gen2-i2c";
 574                         reg = <0 0xe6508000 0 0x40>;
 575                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&cpg CPG_MOD 931>;
 577                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 578                         resets = <&cpg 931>;
 579                         i2c-scl-internal-delay-ns = <6>;
 580                         #address-cells = <1>;
 581                         #size-cells = <0>;
 582                         status = "disabled";
 583                 };
 584
 585                 i2c1: i2c@e6518000 {
 586                         compatible = "renesas,i2c-r8a7792",
 587                                      "renesas,rcar-gen2-i2c";
 588                         reg = <0 0xe6518000 0 0x40>;
 589                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 590                         clocks = <&cpg CPG_MOD 930>;
 591                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 592                         resets = <&cpg 930>;
 593                         i2c-scl-internal-delay-ns = <6>;
 594                         #address-cells = <1>;
 595                         #size-cells = <0>;
 596                         status = "disabled";
 597                 };
 598
 599                 i2c2: i2c@e6530000 {
 600                         compatible = "renesas,i2c-r8a7792",
 601                                      "renesas,rcar-gen2-i2c";
 602                         reg = <0 0xe6530000 0 0x40>;
 603                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 604                         clocks = <&cpg CPG_MOD 929>;
 605                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 606                         resets = <&cpg 929>;
 607                         i2c-scl-internal-delay-ns = <6>;
 608                         #address-cells = <1>;
 609                         #size-cells = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 i2c3: i2c@e6540000 {
 614                         compatible = "renesas,i2c-r8a7792",
 615                                      "renesas,rcar-gen2-i2c";
 616                         reg = <0 0xe6540000 0 0x40>;
 617                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 618                         clocks = <&cpg CPG_MOD 928>;
 619                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 620                         resets = <&cpg 928>;
 621                         i2c-scl-internal-delay-ns = <6>;
 622                         #address-cells = <1>;
 623                         #size-cells = <0>;
 624                         status = "disabled";
 625                 };
 626
 627                 i2c4: i2c@e6520000 {
 628                         compatible = "renesas,i2c-r8a7792",
 629                                      "renesas,rcar-gen2-i2c";
 630                         reg = <0 0xe6520000 0 0x40>;
 631                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 632                         clocks = <&cpg CPG_MOD 927>;
 633                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 634                         resets = <&cpg 927>;
 635                         i2c-scl-internal-delay-ns = <6>;
 636                         #address-cells = <1>;
 637                         #size-cells = <0>;
 638                         status = "disabled";
 639                 };
 640
 641                 i2c5: i2c@e6528000 {
 642                         compatible = "renesas,i2c-r8a7792",
 643                                      "renesas,rcar-gen2-i2c";
 644                         reg = <0 0xe6528000 0 0x40>;
 645                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 646                         clocks = <&cpg CPG_MOD 925>;
 647                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 648                         resets = <&cpg 925>;
 649                         i2c-scl-internal-delay-ns = <110>;
 650                         #address-cells = <1>;
 651                         #size-cells = <0>;
 652                         status = "disabled";
 653                 };
 654
 655                 qspi: spi@e6b10000 {
 656                         compatible = "renesas,qspi-r8a7792", "renesas,qspi";
 657                         reg = <0 0xe6b10000 0 0x2c>;
 658                         interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
 659                         clocks = <&cpg CPG_MOD 917>;
 660                         dmas = <&dmac0 0x17>, <&dmac0 0x18>,
 661                                <&dmac1 0x17>, <&dmac1 0x18>;
 662                         dma-names = "tx", "rx", "tx", "rx";
 663                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 664                         resets = <&cpg 917>;
 665                         num-cs = <1>;
 666                         #address-cells = <1>;
 667                         #size-cells = <0>;
 668                         status = "disabled";
 669                 };
 670
 671                 msiof0: spi@e6e20000 {
 672                         compatible = "renesas,msiof-r8a7792",
 673                                      "renesas,rcar-gen2-msiof";
 674                         reg = <0 0xe6e20000 0 0x0064>;
 675                         interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&cpg CPG_MOD 000>;
 677                         dmas = <&dmac0 0x51>, <&dmac0 0x52>,
 678                                <&dmac1 0x51>, <&dmac1 0x52>;
 679                         dma-names = "tx", "rx", "tx", "rx";
 680                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 681                         resets = <&cpg 000>;
 682                         #address-cells = <1>;
 683                         #size-cells = <0>;
 684                         status = "disabled";
 685                 };
 686
 687                 msiof1: spi@e6e10000 {
 688                         compatible = "renesas,msiof-r8a7792",
 689                                      "renesas,rcar-gen2-msiof";
 690                         reg = <0 0xe6e10000 0 0x0064>;
 691                         interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
 692                         clocks = <&cpg CPG_MOD 208>;
 693                         dmas = <&dmac0 0x55>, <&dmac0 0x56>,
 694                                <&dmac1 0x55>, <&dmac1 0x56>;
 695                         dma-names = "tx", "rx", "tx", "rx";
 696                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 697                         resets = <&cpg 208>;
 698                         #address-cells = <1>;
 699                         #size-cells = <0>;
 700                         status = "disabled";
 701                 };
 702
 703                 du: display@feb00000 {
 704                         compatible = "renesas,du-r8a7792";
 705                         reg = <0 0xfeb00000 0 0x40000>;
 706                         reg-names = "du";
 707                         interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
 708                                      <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
 709                         clocks = <&cpg CPG_MOD 724>,
 710                                  <&cpg CPG_MOD 723>;
 711                         clock-names = "du.0", "du.1";
 712                         status = "disabled";
 713
 714                         ports {
 715                                 #address-cells = <1>;
 716                                 #size-cells = <0>;
 717
 718                                 port@0 {
 719                                         reg = <0>;
 720                                         du_out_rgb0: endpoint {
 721                                         };
 722                                 };
 723                                 port@1 {
 724                                         reg = <1>;
 725                                         du_out_rgb1: endpoint {
 726                                         };
 727                                 };
 728                         };
 729                 };
 730
 731                 can0: can@e6e80000 {
 732                         compatible = "renesas,can-r8a7792",
 733                                      "renesas,rcar-gen2-can";
 734                         reg = <0 0xe6e80000 0 0x1000>;
 735                         interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
 736                         clocks = <&cpg CPG_MOD 916>,
 737                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 738                         clock-names = "clkp1", "clkp2", "can_clk";
 739                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 740                         resets = <&cpg 916>;
 741                         status = "disabled";
 742                 };
 743
 744                 can1: can@e6e88000 {
 745                         compatible = "renesas,can-r8a7792",
 746                                      "renesas,rcar-gen2-can";
 747                         reg = <0 0xe6e88000 0 0x1000>;
 748                         interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
 749                         clocks = <&cpg CPG_MOD 915>,
 750                                  <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
 751                         clock-names = "clkp1", "clkp2", "can_clk";
 752                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 753                         resets = <&cpg 915>;
 754                         status = "disabled";
 755                 };
 756
 757                 vin0: video@e6ef0000 {
 758                         compatible = "renesas,vin-r8a7792",
 759                                      "renesas,rcar-gen2-vin";
 760                         reg = <0 0xe6ef0000 0 0x1000>;
 761                         interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
 762                         clocks = <&cpg CPG_MOD 811>;
 763                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 764                         resets = <&cpg 811>;
 765                         status = "disabled";
 766                 };
 767
 768                 vin1: video@e6ef1000 {
 769                         compatible = "renesas,vin-r8a7792",
 770                                      "renesas,rcar-gen2-vin";
 771                         reg = <0 0xe6ef1000 0 0x1000>;
 772                         interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
 773                         clocks = <&cpg CPG_MOD 810>;
 774                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 775                         resets = <&cpg 810>;
 776                         status = "disabled";
 777                 };
 778
 779                 vin2: video@e6ef2000 {
 780                         compatible = "renesas,vin-r8a7792",
 781                                      "renesas,rcar-gen2-vin";
 782                         reg = <0 0xe6ef2000 0 0x1000>;
 783                         interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
 784                         clocks = <&cpg CPG_MOD 809>;
 785                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 786                         resets = <&cpg 809>;
 787                         status = "disabled";
 788                 };
 789
 790                 vin3: video@e6ef3000 {
 791                         compatible = "renesas,vin-r8a7792",
 792                                      "renesas,rcar-gen2-vin";
 793                         reg = <0 0xe6ef3000 0 0x1000>;
 794                         interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
 795                         clocks = <&cpg CPG_MOD 808>;
 796                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 797                         resets = <&cpg 808>;
 798                         status = "disabled";
 799                 };
 800
 801                 vin4: video@e6ef4000 {
 802                         compatible = "renesas,vin-r8a7792",
 803                                      "renesas,rcar-gen2-vin";
 804                         reg = <0 0xe6ef4000 0 0x1000>;
 805                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 806                         clocks = <&cpg CPG_MOD 805>;
 807                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 808                         resets = <&cpg 805>;
 809                         status = "disabled";
 810                 };
 811
 812                 vin5: video@e6ef5000 {
 813                         compatible = "renesas,vin-r8a7792",
 814                                      "renesas,rcar-gen2-vin";
 815                         reg = <0 0xe6ef5000 0 0x1000>;
 816                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 817                         clocks = <&cpg CPG_MOD 804>;
 818                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 819                         resets = <&cpg 804>;
 820                         status = "disabled";
 821                 };
 822
 823                 vsp@fe928000 {
 824                         compatible = "renesas,vsp1";
 825                         reg = <0 0xfe928000 0 0x8000>;
 826                         interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
 827                         clocks = <&cpg CPG_MOD 131>;
 828                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 829                         resets = <&cpg 131>;
 830                 };
 831
 832                 vsp@fe930000 {
 833                         compatible = "renesas,vsp1";
 834                         reg = <0 0xfe930000 0 0x8000>;
 835                         interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
 836                         clocks = <&cpg CPG_MOD 128>;
 837                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 838                         resets = <&cpg 128>;
 839                 };
 840
 841                 vsp@fe938000 {
 842                         compatible = "renesas,vsp1";
 843                         reg = <0 0xfe938000 0 0x8000>;
 844                         interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 845                         clocks = <&cpg CPG_MOD 127>;
 846                         power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
 847                         resets = <&cpg 127>;
 848                 };
 849
 850                 cpg: clock-controller@e6150000 {
 851                         compatible = "renesas,r8a7792-cpg-mssr";
 852                         reg = <0 0xe6150000 0 0x1000>;
 853                         clocks = <&extal_clk>;
 854                         clock-names = "extal";
 855                         #clock-cells = <2>;
 856                         #power-domain-cells = <0>;
 857                 };
 858         };
 859 };