arch/arm/boot/dts/r8a7793.dtsi

   1 /*
   2  * Device Tree Source for the r8a7793 SoC
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/clock/r8a7793-clock.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/interrupt-controller/irq.h>
  14
  15 / {
  16         compatible = "renesas,r8a7793";
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 spi0 = &qspi;
  23         };
  24
  25         cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28
  29                 cpu0: cpu@0 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a15";
  32                         reg = <0>;
  33                         clock-frequency = <1500000000>;
  34                         voltage-tolerance = <1>; /* 1% */
  35                         clocks = <&cpg_clocks R8A7793_CLK_Z>;
  36                         clock-latency = <300000>; /* 300 us */
  37
  38                         /* kHz - uV - OPPs unknown yet */
  39                         operating-points = <1500000 1000000>,
  40                                            <1312500 1000000>,
  41                                            <1125000 1000000>,
  42                                            < 937500 1000000>,
  43                                            < 750000 1000000>,
  44                                            < 375000 1000000>;
  45                 };
  46         };
  47
  48         gic: interrupt-controller@f1001000 {
  49                 compatible = "arm,gic-400";
  50                 #interrupt-cells = <3>;
  51                 #address-cells = <0>;
  52                 interrupt-controller;
  53                 reg = <0 0xf1001000 0 0x1000>,
  54                         <0 0xf1002000 0 0x1000>,
  55                         <0 0xf1004000 0 0x2000>,
  56                         <0 0xf1006000 0 0x2000>;
  57                 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  58         };
  59
  60         gpio0: gpio@e6050000 {
  61                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  62                 reg = <0 0xe6050000 0 0x50>;
  63                 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
  64                 #gpio-cells = <2>;
  65                 gpio-controller;
  66                 gpio-ranges = <&pfc 0 0 32>;
  67                 #interrupt-cells = <2>;
  68                 interrupt-controller;
  69                 clocks = <&mstp9_clks R8A7793_CLK_GPIO0>;
  70                 power-domains = <&cpg_clocks>;
  71         };
  72
  73         gpio1: gpio@e6051000 {
  74                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  75                 reg = <0 0xe6051000 0 0x50>;
  76                 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
  77                 #gpio-cells = <2>;
  78                 gpio-controller;
  79                 gpio-ranges = <&pfc 0 32 26>;
  80                 #interrupt-cells = <2>;
  81                 interrupt-controller;
  82                 clocks = <&mstp9_clks R8A7793_CLK_GPIO1>;
  83                 power-domains = <&cpg_clocks>;
  84         };
  85
  86         gpio2: gpio@e6052000 {
  87                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
  88                 reg = <0 0xe6052000 0 0x50>;
  89                 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
  90                 #gpio-cells = <2>;
  91                 gpio-controller;
  92                 gpio-ranges = <&pfc 0 64 32>;
  93                 #interrupt-cells = <2>;
  94                 interrupt-controller;
  95                 clocks = <&mstp9_clks R8A7793_CLK_GPIO2>;
  96                 power-domains = <&cpg_clocks>;
  97         };
  98
  99         gpio3: gpio@e6053000 {
 100                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 101                 reg = <0 0xe6053000 0 0x50>;
 102                 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
 103                 #gpio-cells = <2>;
 104                 gpio-controller;
 105                 gpio-ranges = <&pfc 0 96 32>;
 106                 #interrupt-cells = <2>;
 107                 interrupt-controller;
 108                 clocks = <&mstp9_clks R8A7793_CLK_GPIO3>;
 109                 power-domains = <&cpg_clocks>;
 110         };
 111
 112         gpio4: gpio@e6054000 {
 113                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 114                 reg = <0 0xe6054000 0 0x50>;
 115                 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
 116                 #gpio-cells = <2>;
 117                 gpio-controller;
 118                 gpio-ranges = <&pfc 0 128 32>;
 119                 #interrupt-cells = <2>;
 120                 interrupt-controller;
 121                 clocks = <&mstp9_clks R8A7793_CLK_GPIO4>;
 122                 power-domains = <&cpg_clocks>;
 123         };
 124
 125         gpio5: gpio@e6055000 {
 126                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 127                 reg = <0 0xe6055000 0 0x50>;
 128                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
 129                 #gpio-cells = <2>;
 130                 gpio-controller;
 131                 gpio-ranges = <&pfc 0 160 32>;
 132                 #interrupt-cells = <2>;
 133                 interrupt-controller;
 134                 clocks = <&mstp9_clks R8A7793_CLK_GPIO5>;
 135                 power-domains = <&cpg_clocks>;
 136         };
 137
 138         gpio6: gpio@e6055400 {
 139                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 140                 reg = <0 0xe6055400 0 0x50>;
 141                 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
 142                 #gpio-cells = <2>;
 143                 gpio-controller;
 144                 gpio-ranges = <&pfc 0 192 32>;
 145                 #interrupt-cells = <2>;
 146                 interrupt-controller;
 147                 clocks = <&mstp9_clks R8A7793_CLK_GPIO6>;
 148                 power-domains = <&cpg_clocks>;
 149         };
 150
 151         gpio7: gpio@e6055800 {
 152                 compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar";
 153                 reg = <0 0xe6055800 0 0x50>;
 154                 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
 155                 #gpio-cells = <2>;
 156                 gpio-controller;
 157                 gpio-ranges = <&pfc 0 224 26>;
 158                 #interrupt-cells = <2>;
 159                 interrupt-controller;
 160                 clocks = <&mstp9_clks R8A7793_CLK_GPIO7>;
 161                 power-domains = <&cpg_clocks>;
 162         };
 163
 164         thermal@e61f0000 {
 165                 compatible = "renesas,thermal-r8a7793", "renesas,rcar-thermal";
 166                 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
 167                 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
 168                 clocks = <&mstp5_clks R8A7793_CLK_THERMAL>;
 169                 power-domains = <&cpg_clocks>;
 170         };
 171
 172         timer {
 173                 compatible = "arm,armv7-timer";
 174                 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 175                              <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 176                              <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
 177                              <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
 178         };
 179
 180         cmt0: timer@ffca0000 {
 181                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 182                 reg = <0 0xffca0000 0 0x1004>;
 183                 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
 184                              <0 143 IRQ_TYPE_LEVEL_HIGH>;
 185                 clocks = <&mstp1_clks R8A7793_CLK_CMT0>;
 186                 clock-names = "fck";
 187                 power-domains = <&cpg_clocks>;
 188
 189                 renesas,channels-mask = <0x60>;
 190
 191                 status = "disabled";
 192         };
 193
 194         cmt1: timer@e6130000 {
 195                 compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2";
 196                 reg = <0 0xe6130000 0 0x1004>;
 197                 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
 198                              <0 121 IRQ_TYPE_LEVEL_HIGH>,
 199                              <0 122 IRQ_TYPE_LEVEL_HIGH>,
 200                              <0 123 IRQ_TYPE_LEVEL_HIGH>,
 201                              <0 124 IRQ_TYPE_LEVEL_HIGH>,
 202                              <0 125 IRQ_TYPE_LEVEL_HIGH>,
 203                              <0 126 IRQ_TYPE_LEVEL_HIGH>,
 204                              <0 127 IRQ_TYPE_LEVEL_HIGH>;
 205                 clocks = <&mstp3_clks R8A7793_CLK_CMT1>;
 206                 clock-names = "fck";
 207                 power-domains = <&cpg_clocks>;
 208
 209                 renesas,channels-mask = <0xff>;
 210
 211                 status = "disabled";
 212         };
 213
 214         irqc0: interrupt-controller@e61c0000 {
 215                 compatible = "renesas,irqc-r8a7793", "renesas,irqc";
 216                 #interrupt-cells = <2>;
 217                 interrupt-controller;
 218                 reg = <0 0xe61c0000 0 0x200>;
 219                 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
 220                              <0 1 IRQ_TYPE_LEVEL_HIGH>,
 221                              <0 2 IRQ_TYPE_LEVEL_HIGH>,
 222                              <0 3 IRQ_TYPE_LEVEL_HIGH>,
 223                              <0 12 IRQ_TYPE_LEVEL_HIGH>,
 224                              <0 13 IRQ_TYPE_LEVEL_HIGH>,
 225                              <0 14 IRQ_TYPE_LEVEL_HIGH>,
 226                              <0 15 IRQ_TYPE_LEVEL_HIGH>,
 227                              <0 16 IRQ_TYPE_LEVEL_HIGH>,
 228                              <0 17 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&mstp4_clks R8A7793_CLK_IRQC>;
 230                 power-domains = <&cpg_clocks>;
 231         };
 232
 233         pfc: pfc@e6060000 {
 234                 compatible = "renesas,pfc-r8a7793";
 235                 reg = <0 0xe6060000 0 0x250>;
 236         };
 237
 238         dmac0: dma-controller@e6700000 {
 239                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 240                 reg = <0 0xe6700000 0 0x20000>;
 241                 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
 242                               0 200 IRQ_TYPE_LEVEL_HIGH
 243                               0 201 IRQ_TYPE_LEVEL_HIGH
 244                               0 202 IRQ_TYPE_LEVEL_HIGH
 245                               0 203 IRQ_TYPE_LEVEL_HIGH
 246                               0 204 IRQ_TYPE_LEVEL_HIGH
 247                               0 205 IRQ_TYPE_LEVEL_HIGH
 248                               0 206 IRQ_TYPE_LEVEL_HIGH
 249                               0 207 IRQ_TYPE_LEVEL_HIGH
 250                               0 208 IRQ_TYPE_LEVEL_HIGH
 251                               0 209 IRQ_TYPE_LEVEL_HIGH
 252                               0 210 IRQ_TYPE_LEVEL_HIGH
 253                               0 211 IRQ_TYPE_LEVEL_HIGH
 254                               0 212 IRQ_TYPE_LEVEL_HIGH
 255                               0 213 IRQ_TYPE_LEVEL_HIGH
 256                               0 214 IRQ_TYPE_LEVEL_HIGH>;
 257                 interrupt-names = "error",
 258                                 "ch0", "ch1", "ch2", "ch3",
 259                                 "ch4", "ch5", "ch6", "ch7",
 260                                 "ch8", "ch9", "ch10", "ch11",
 261                                 "ch12", "ch13", "ch14";
 262                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>;
 263                 clock-names = "fck";
 264                 power-domains = <&cpg_clocks>;
 265                 #dma-cells = <1>;
 266                 dma-channels = <15>;
 267         };
 268
 269         dmac1: dma-controller@e6720000 {
 270                 compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac";
 271                 reg = <0 0xe6720000 0 0x20000>;
 272                 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
 273                               0 216 IRQ_TYPE_LEVEL_HIGH
 274                               0 217 IRQ_TYPE_LEVEL_HIGH
 275                               0 218 IRQ_TYPE_LEVEL_HIGH
 276                               0 219 IRQ_TYPE_LEVEL_HIGH
 277                               0 308 IRQ_TYPE_LEVEL_HIGH
 278                               0 309 IRQ_TYPE_LEVEL_HIGH
 279                               0 310 IRQ_TYPE_LEVEL_HIGH
 280                               0 311 IRQ_TYPE_LEVEL_HIGH
 281                               0 312 IRQ_TYPE_LEVEL_HIGH
 282                               0 313 IRQ_TYPE_LEVEL_HIGH
 283                               0 314 IRQ_TYPE_LEVEL_HIGH
 284                               0 315 IRQ_TYPE_LEVEL_HIGH
 285                               0 316 IRQ_TYPE_LEVEL_HIGH
 286                               0 317 IRQ_TYPE_LEVEL_HIGH
 287                               0 318 IRQ_TYPE_LEVEL_HIGH>;
 288                 interrupt-names = "error",
 289                                 "ch0", "ch1", "ch2", "ch3",
 290                                 "ch4", "ch5", "ch6", "ch7",
 291                                 "ch8", "ch9", "ch10", "ch11",
 292                                 "ch12", "ch13", "ch14";
 293                 clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>;
 294                 clock-names = "fck";
 295                 power-domains = <&cpg_clocks>;
 296                 #dma-cells = <1>;
 297                 dma-channels = <15>;
 298         };
 299
 300         scif0: serial@e6e60000 {
 301                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 302                 reg = <0 0xe6e60000 0 64>;
 303                 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
 304                 clocks = <&mstp7_clks R8A7793_CLK_SCIF0>;
 305                 clock-names = "sci_ick";
 306                 power-domains = <&cpg_clocks>;
 307                 status = "disabled";
 308         };
 309
 310         scif1: serial@e6e68000 {
 311                 compatible = "renesas,scif-r8a7793", "renesas,scif";
 312                 reg = <0 0xe6e68000 0 64>;
 313                 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
 314                 clocks = <&mstp7_clks R8A7793_CLK_SCIF1>;
 315                 clock-names = "sci_ick";
 316                 power-domains = <&cpg_clocks>;
 317                 status = "disabled";
 318         };
 319
 320         ether: ethernet@ee700000 {
 321                 compatible = "renesas,ether-r8a7793";
 322                 reg = <0 0xee700000 0 0x400>;
 323                 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
 324                 clocks = <&mstp8_clks R8A7793_CLK_ETHER>;
 325                 power-domains = <&cpg_clocks>;
 326                 phy-mode = "rmii";
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 status = "disabled";
 330         };
 331
 332         qspi: spi@e6b10000 {
 333                 compatible = "renesas,qspi-r8a7793", "renesas,qspi";
 334                 reg = <0 0xe6b10000 0 0x2c>;
 335                 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
 336                 clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>;
 337                 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
 338                 dma-names = "tx", "rx";
 339                 power-domains = <&cpg_clocks>;
 340                 num-cs = <1>;
 341                 #address-cells = <1>;
 342                 #size-cells = <0>;
 343                 status = "disabled";
 344         };
 345
 346         du: display@feb00000 {
 347                 compatible = "renesas,du-r8a7793";
 348                 reg = <0 0xfeb00000 0 0x40000>,
 349                       <0 0xfeb90000 0 0x1c>;
 350                 reg-names = "du", "lvds.0";
 351                 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
 352                              <0 268 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&mstp7_clks R8A7793_CLK_DU0>,
 354                          <&mstp7_clks R8A7793_CLK_DU1>,
 355                          <&mstp7_clks R8A7793_CLK_LVDS0>;
 356                 clock-names = "du.0", "du.1", "lvds.0";
 357                 status = "disabled";
 358
 359                 ports {
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362
 363                         port@0 {
 364                                 reg = <0>;
 365                                 du_out_rgb: endpoint {
 366                                 };
 367                         };
 368                         port@1 {
 369                                 reg = <1>;
 370                                 du_out_lvds0: endpoint {
 371                                 };
 372                         };
 373                 };
 374         };
 375
 376         clocks {
 377                 #address-cells = <2>;
 378                 #size-cells = <2>;
 379                 ranges;
 380
 381                 /* External root clock */
 382                 extal_clk: extal_clk {
 383                         compatible = "fixed-clock";
 384                         #clock-cells = <0>;
 385                         /* This value must be overridden by the board. */
 386                         clock-frequency = <0>;
 387                         clock-output-names = "extal";
 388                 };
 389
 390                 /* Special CPG clocks */
 391                 cpg_clocks: cpg_clocks@e6150000 {
 392                         compatible = "renesas,r8a7793-cpg-clocks",
 393                                      "renesas,rcar-gen2-cpg-clocks";
 394                         reg = <0 0xe6150000 0 0x1000>;
 395                         clocks = <&extal_clk>;
 396                         #clock-cells = <1>;
 397                         clock-output-names = "main", "pll0", "pll1", "pll3",
 398                                              "lb", "qspi", "sdh", "sd0", "z",
 399                                              "rcan", "adsp";
 400                         #power-domain-cells = <0>;
 401                 };
 402
 403                 /* Variable factor clocks */
 404                 sd2_clk: sd2_clk@e6150078 {
 405                         compatible = "renesas,r8a7793-div6-clock",
 406                                      "renesas,cpg-div6-clock";
 407                         reg = <0 0xe6150078 0 4>;
 408                         clocks = <&pll1_div2_clk>;
 409                         #clock-cells = <0>;
 410                         clock-output-names = "sd2";
 411                 };
 412                 sd3_clk: sd3_clk@e615026c {
 413                         compatible = "renesas,r8a7793-div6-clock",
 414                                      "renesas,cpg-div6-clock";
 415                         reg = <0 0xe615026c 0 4>;
 416                         clocks = <&pll1_div2_clk>;
 417                         #clock-cells = <0>;
 418                         clock-output-names = "sd3";
 419                 };
 420                 mmc0_clk: mmc0_clk@e6150240 {
 421                         compatible = "renesas,r8a7793-div6-clock",
 422                                      "renesas,cpg-div6-clock";
 423                         reg = <0 0xe6150240 0 4>;
 424                         clocks = <&pll1_div2_clk>;
 425                         #clock-cells = <0>;
 426                         clock-output-names = "mmc0";
 427                 };
 428
 429                 /* Fixed factor clocks */
 430                 pll1_div2_clk: pll1_div2_clk {
 431                         compatible = "fixed-factor-clock";
 432                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 433                         #clock-cells = <0>;
 434                         clock-div = <2>;
 435                         clock-mult = <1>;
 436                         clock-output-names = "pll1_div2";
 437                 };
 438                 zg_clk: zg_clk {
 439                         compatible = "fixed-factor-clock";
 440                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 441                         #clock-cells = <0>;
 442                         clock-div = <5>;
 443                         clock-mult = <1>;
 444                         clock-output-names = "zg";
 445                 };
 446                 zx_clk: zx_clk {
 447                         compatible = "fixed-factor-clock";
 448                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 449                         #clock-cells = <0>;
 450                         clock-div = <3>;
 451                         clock-mult = <1>;
 452                         clock-output-names = "zx";
 453                 };
 454                 zs_clk: zs_clk {
 455                         compatible = "fixed-factor-clock";
 456                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 457                         #clock-cells = <0>;
 458                         clock-div = <6>;
 459                         clock-mult = <1>;
 460                         clock-output-names = "zs";
 461                 };
 462                 hp_clk: hp_clk {
 463                         compatible = "fixed-factor-clock";
 464                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 465                         #clock-cells = <0>;
 466                         clock-div = <12>;
 467                         clock-mult = <1>;
 468                         clock-output-names = "hp";
 469                 };
 470                 p_clk: p_clk {
 471                         compatible = "fixed-factor-clock";
 472                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 473                         #clock-cells = <0>;
 474                         clock-div = <24>;
 475                         clock-mult = <1>;
 476                         clock-output-names = "p";
 477                 };
 478                 rclk_clk: rclk_clk {
 479                         compatible = "fixed-factor-clock";
 480                         clocks = <&cpg_clocks R8A7793_CLK_PLL1>;
 481                         #clock-cells = <0>;
 482                         clock-div = <(48 * 1024)>;
 483                         clock-mult = <1>;
 484                         clock-output-names = "rclk";
 485                 };
 486                 mp_clk: mp_clk {
 487                         compatible = "fixed-factor-clock";
 488                         clocks = <&pll1_div2_clk>;
 489                         #clock-cells = <0>;
 490                         clock-div = <15>;
 491                         clock-mult = <1>;
 492                         clock-output-names = "mp";
 493                 };
 494                 cp_clk: cp_clk {
 495                         compatible = "fixed-factor-clock";
 496                         clocks = <&extal_clk>;
 497                         #clock-cells = <0>;
 498                         clock-div = <2>;
 499                         clock-mult = <1>;
 500                         clock-output-names = "cp";
 501                 };
 502
 503                 /* Gate clocks */
 504                 mstp1_clks: mstp1_clks@e6150134 {
 505                         compatible = "renesas,r8a7793-mstp-clocks",
 506                                      "renesas,cpg-mstp-clocks";
 507                         reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
 508                         clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 509                                  <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
 510                                  <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
 511                                  <&zs_clk>, <&zs_clk>, <&zs_clk>;
 512                         #clock-cells = <1>;
 513                         clock-indices = <
 514                                 R8A7793_CLK_VCP0 R8A7793_CLK_VPC0
 515                                 R8A7793_CLK_SSP1 R8A7793_CLK_TMU1
 516                                 R8A7793_CLK_3DG R8A7793_CLK_2DDMAC
 517                                 R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0
 518                                 R8A7793_CLK_TMU3 R8A7793_CLK_TMU2
 519                                 R8A7793_CLK_CMT0 R8A7793_CLK_TMU0
 520                                 R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0
 521                                 R8A7793_CLK_VSP1_S
 522                         >;
 523                         clock-output-names =
 524                                 "vcp0", "vpc0", "ssp_dev", "tmu1",
 525                                 "pvrsrvkm", "tddmac", "fdp1", "fdp0",
 526                                 "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
 527                                 "vsp1-du0", "vsps";
 528                 };
 529                 mstp2_clks: mstp2_clks@e6150138 {
 530                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 531                         reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
 532                         clocks = <&zs_clk>, <&zs_clk>;
 533                         #clock-cells = <1>;
 534                         clock-indices = <
 535                                 R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0
 536                         >;
 537                         clock-output-names = "sys-dmac1", "sys-dmac0";
 538                 };
 539                 mstp3_clks: mstp3_clks@e615013c {
 540                         compatible = "renesas,r8a7793-mstp-clocks",
 541                                      "renesas,cpg-mstp-clocks";
 542                         reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
 543                         clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>,
 544                                  <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>,
 545                                  <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>,
 546                                  <&rclk_clk>, <&hp_clk>, <&hp_clk>;
 547                         #clock-cells = <1>;
 548                         clock-indices = <
 549                                 R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2
 550                                 R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0
 551                                 R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0
 552                                 R8A7793_CLK_PCIEC R8A7793_CLK_IIC1
 553                                 R8A7793_CLK_SSUSB R8A7793_CLK_CMT1
 554                                 R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1
 555                         >;
 556                         clock-output-names =
 557                                 "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
 558                                 "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
 559                                 "usbdmac0", "usbdmac1";
 560                 };
 561                 mstp4_clks: mstp4_clks@e6150140 {
 562                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 563                         reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
 564                         clocks = <&cp_clk>;
 565                         #clock-cells = <1>;
 566                         clock-indices = <R8A7793_CLK_IRQC>;
 567                         clock-output-names = "irqc";
 568                 };
 569                 mstp5_clks: mstp5_clks@e6150144 {
 570                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 571                         reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
 572                         clocks = <&extal_clk>;
 573                         #clock-cells = <1>;
 574                         clock-indices = <R8A7793_CLK_THERMAL>;
 575                         clock-output-names = "thermal";
 576                 };
 577                 mstp7_clks: mstp7_clks@e615014c {
 578                         compatible = "renesas,r8a7793-mstp-clocks",
 579                                      "renesas,cpg-mstp-clocks";
 580                         reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
 581                         clocks = <&mp_clk>,  <&hp_clk>, <&zs_clk>, <&p_clk>,
 582                                  <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
 583                                  <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>,
 584                                  <&zx_clk>, <&zx_clk>;
 585                         #clock-cells = <1>;
 586                         clock-indices = <
 587                                 R8A7793_CLK_EHCI R8A7793_CLK_HSUSB
 588                                 R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5
 589                                 R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1
 590                                 R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3
 591                                 R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1
 592                                 R8A7793_CLK_SCIF0 R8A7793_CLK_DU1
 593                                 R8A7793_CLK_DU0 R8A7793_CLK_LVDS0
 594                         >;
 595                         clock-output-names =
 596                                 "ehci", "hsusb", "hscif2", "scif5", "scif4",
 597                                 "hscif1", "hscif0", "scif3", "scif2",
 598                                 "scif1", "scif0", "du1", "du0", "lvds0";
 599                 };
 600                 mstp8_clks: mstp8_clks@e6150990 {
 601                         compatible = "renesas,r8a7793-mstp-clocks",
 602                                      "renesas,cpg-mstp-clocks";
 603                         reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
 604                         clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
 605                                  <&p_clk>, <&zs_clk>, <&zs_clk>;
 606                         #clock-cells = <1>;
 607                         clock-indices = <
 608                                 R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2
 609                                 R8A7793_CLK_VIN1 R8A7793_CLK_VIN0
 610                                 R8A7793_CLK_ETHER R8A7793_CLK_SATA1
 611                                 R8A7793_CLK_SATA0
 612                         >;
 613                         clock-output-names =
 614                                 "ipmmu_sgx", "vin2", "vin1", "vin0", "ether",
 615                                 "sata1", "sata0";
 616                 };
 617                 mstp9_clks: mstp9_clks@e6150994 {
 618                         compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
 619                         reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
 620                         clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 621                                  <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
 622                                  <&cpg_clocks R8A7793_CLK_QSPI>;
 623                         #clock-cells = <1>;
 624                         clock-indices = <
 625                                 R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
 626                                 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
 627                                 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
 628                                 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
 629                                 R8A7793_CLK_QSPI_MOD
 630                         >;
 631                         clock-output-names =
 632                                 "gpio7", "gpio6", "gpio5", "gpio4",
 633                                 "gpio3", "gpio2", "gpio1", "gpio0",
 634                                 "qspi_mod";
 635                 };
 636         };
 637
 638         ipmmu_sy0: mmu@e6280000 {
 639                 compatible = "renesas,ipmmu-vmsa";
 640                 reg = <0 0xe6280000 0 0x1000>;
 641                 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
 642                              <0 224 IRQ_TYPE_LEVEL_HIGH>;
 643                 #iommu-cells = <1>;
 644                 status = "disabled";
 645         };
 646
 647         ipmmu_sy1: mmu@e6290000 {
 648                 compatible = "renesas,ipmmu-vmsa";
 649                 reg = <0 0xe6290000 0 0x1000>;
 650                 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
 651                 #iommu-cells = <1>;
 652                 status = "disabled";
 653         };
 654
 655         ipmmu_ds: mmu@e6740000 {
 656                 compatible = "renesas,ipmmu-vmsa";
 657                 reg = <0 0xe6740000 0 0x1000>;
 658                 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
 659                              <0 199 IRQ_TYPE_LEVEL_HIGH>;
 660                 #iommu-cells = <1>;
 661                 status = "disabled";
 662         };
 663
 664         ipmmu_mp: mmu@ec680000 {
 665                 compatible = "renesas,ipmmu-vmsa";
 666                 reg = <0 0xec680000 0 0x1000>;
 667                 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
 668                 #iommu-cells = <1>;
 669                 status = "disabled";
 670         };
 671
 672         ipmmu_mx: mmu@fe951000 {
 673                 compatible = "renesas,ipmmu-vmsa";
 674                 reg = <0 0xfe951000 0 0x1000>;
 675                 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
 676                              <0 221 IRQ_TYPE_LEVEL_HIGH>;
 677                 #iommu-cells = <1>;
 678                 status = "disabled";
 679         };
 680
 681         ipmmu_rt: mmu@ffc80000 {
 682                 compatible = "renesas,ipmmu-vmsa";
 683                 reg = <0 0xffc80000 0 0x1000>;
 684                 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
 685                 #iommu-cells = <1>;
 686                 status = "disabled";
 687         };
 688
 689         ipmmu_gp: mmu@e62a0000 {
 690                 compatible = "renesas,ipmmu-vmsa";
 691                 reg = <0 0xe62a0000 0 0x1000>;
 692                 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
 693                              <0 261 IRQ_TYPE_LEVEL_HIGH>;
 694                 #iommu-cells = <1>;
 695                 status = "disabled";
 696         };
 697 };