arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This library is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This library is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  *     You should have received a copy of the GNU General Public
  22  *     License along with this library; if not, write to the Free
  23  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  24  *     MA 02110-1301 USA
  25  *
  26  * Or, alternatively,
  27  *
  28  *  b) Permission is hereby granted, free of charge, to any person
  29  *     obtaining a copy of this software and associated documentation
  30  *     files (the "Software"), to deal in the Software without
  31  *     restriction, including without limitation the rights to use,
  32  *     copy, modify, merge, publish, distribute, sublicense, and/or
  33  *     sell copies of the Software, and to permit persons to whom the
  34  *     Software is furnished to do so, subject to the following
  35  *     conditions:
  36  *
  37  *     The above copyright notice and this permission notice shall be
  38  *     included in all copies or substantial portions of the Software.
  39  *
  40  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  41  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  42  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  43  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  44  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  45  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  46  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  47  *     OTHER DEALINGS IN THE SOFTWARE.
  48  */
  49
  50 #include "skeleton.dtsi"
  51
  52 #include <dt-bindings/dma/sun4i-a10.h>
  53 #include <dt-bindings/pinctrl/sun4i-a10.h>
  54
  55 / {
  56         interrupt-parent = <&intc>;
  57
  58         aliases {
  59                 ethernet0 = &emac;
  60         };
  61
  62         chosen {
  63                 #address-cells = <1>;
  64                 #size-cells = <1>;
  65                 ranges;
  66
  67                 framebuffer@0 {
  68                         compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
  71                                  <&ahb_gates 44>;
  72                         status = "disabled";
  73                 };
  74
  75                 framebuffer@1 {
  76                         compatible = "allwinner,simple-framebuffer",
  77                                      "simple-framebuffer";
  78                         allwinner,pipeline = "de_be0-lcd0";
  79                         clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
  80                         status = "disabled";
  81                 };
  82         };
  83
  84         cpus {
  85                 cpu@0 {
  86                         compatible = "arm,cortex-a8";
  87                 };
  88         };
  89
  90         memory {
  91                 reg = <0x40000000 0x20000000>;
  92         };
  93
  94         clocks {
  95                 #address-cells = <1>;
  96                 #size-cells = <1>;
  97                 ranges;
  98
  99                 /*
 100                  * This is a dummy clock, to be used as placeholder on
 101                  * other mux clocks when a specific parent clock is not
 102                  * yet implemented. It should be dropped when the driver
 103                  * is complete.
 104                  */
 105                 dummy: dummy {
 106                         #clock-cells = <0>;
 107                         compatible = "fixed-clock";
 108                         clock-frequency = <0>;
 109                 };
 110
 111                 osc24M: clk@01c20050 {
 112                         #clock-cells = <0>;
 113                         compatible = "allwinner,sun4i-a10-osc-clk";
 114                         reg = <0x01c20050 0x4>;
 115                         clock-frequency = <24000000>;
 116                         clock-output-names = "osc24M";
 117                 };
 118
 119                 osc32k: clk@0 {
 120                         #clock-cells = <0>;
 121                         compatible = "fixed-clock";
 122                         clock-frequency = <32768>;
 123                         clock-output-names = "osc32k";
 124                 };
 125
 126                 pll1: clk@01c20000 {
 127                         #clock-cells = <0>;
 128                         compatible = "allwinner,sun4i-a10-pll1-clk";
 129                         reg = <0x01c20000 0x4>;
 130                         clocks = <&osc24M>;
 131                         clock-output-names = "pll1";
 132                 };
 133
 134                 pll4: clk@01c20018 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-a10-pll1-clk";
 137                         reg = <0x01c20018 0x4>;
 138                         clocks = <&osc24M>;
 139                         clock-output-names = "pll4";
 140                 };
 141
 142                 pll5: clk@01c20020 {
 143                         #clock-cells = <1>;
 144                         compatible = "allwinner,sun4i-a10-pll5-clk";
 145                         reg = <0x01c20020 0x4>;
 146                         clocks = <&osc24M>;
 147                         clock-output-names = "pll5_ddr", "pll5_other";
 148                 };
 149
 150                 pll6: clk@01c20028 {
 151                         #clock-cells = <1>;
 152                         compatible = "allwinner,sun4i-a10-pll6-clk";
 153                         reg = <0x01c20028 0x4>;
 154                         clocks = <&osc24M>;
 155                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 156                 };
 157
 158                 /* dummy is 200M */
 159                 cpu: cpu@01c20054 {
 160                         #clock-cells = <0>;
 161                         compatible = "allwinner,sun4i-a10-cpu-clk";
 162                         reg = <0x01c20054 0x4>;
 163                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 164                         clock-output-names = "cpu";
 165                 };
 166
 167                 axi: axi@01c20054 {
 168                         #clock-cells = <0>;
 169                         compatible = "allwinner,sun4i-a10-axi-clk";
 170                         reg = <0x01c20054 0x4>;
 171                         clocks = <&cpu>;
 172                         clock-output-names = "axi";
 173                 };
 174
 175                 axi_gates: clk@01c2005c {
 176                         #clock-cells = <1>;
 177                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 178                         reg = <0x01c2005c 0x4>;
 179                         clocks = <&axi>;
 180                         clock-output-names = "axi_dram";
 181                 };
 182
 183                 ahb: ahb@01c20054 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-ahb-clk";
 186                         reg = <0x01c20054 0x4>;
 187                         clocks = <&axi>;
 188                         clock-output-names = "ahb";
 189                 };
 190
 191                 ahb_gates: clk@01c20060 {
 192                         #clock-cells = <1>;
 193                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 194                         reg = <0x01c20060 0x8>;
 195                         clocks = <&ahb>;
 196                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 197                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 198                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 199                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 200                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 201                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 202                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 203                 };
 204
 205                 apb0: apb0@01c20054 {
 206                         #clock-cells = <0>;
 207                         compatible = "allwinner,sun4i-a10-apb0-clk";
 208                         reg = <0x01c20054 0x4>;
 209                         clocks = <&ahb>;
 210                         clock-output-names = "apb0";
 211                 };
 212
 213                 apb0_gates: clk@01c20068 {
 214                         #clock-cells = <1>;
 215                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 216                         reg = <0x01c20068 0x4>;
 217                         clocks = <&apb0>;
 218                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 219                                 "apb0_ir", "apb0_keypad";
 220                 };
 221
 222                 apb1: clk@01c20058 {
 223                         #clock-cells = <0>;
 224                         compatible = "allwinner,sun4i-a10-apb1-clk";
 225                         reg = <0x01c20058 0x4>;
 226                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 227                         clock-output-names = "apb1";
 228                 };
 229
 230                 apb1_gates: clk@01c2006c {
 231                         #clock-cells = <1>;
 232                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 233                         reg = <0x01c2006c 0x4>;
 234                         clocks = <&apb1>;
 235                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 236                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 237                                 "apb1_uart2", "apb1_uart3";
 238                 };
 239
 240                 nand_clk: clk@01c20080 {
 241                         #clock-cells = <0>;
 242                         compatible = "allwinner,sun4i-a10-mod0-clk";
 243                         reg = <0x01c20080 0x4>;
 244                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 245                         clock-output-names = "nand";
 246                 };
 247
 248                 ms_clk: clk@01c20084 {
 249                         #clock-cells = <0>;
 250                         compatible = "allwinner,sun4i-a10-mod0-clk";
 251                         reg = <0x01c20084 0x4>;
 252                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 253                         clock-output-names = "ms";
 254                 };
 255
 256                 mmc0_clk: clk@01c20088 {
 257                         #clock-cells = <1>;
 258                         compatible = "allwinner,sun4i-a10-mmc-clk";
 259                         reg = <0x01c20088 0x4>;
 260                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 261                         clock-output-names = "mmc0",
 262                                              "mmc0_output",
 263                                              "mmc0_sample";
 264                 };
 265
 266                 mmc1_clk: clk@01c2008c {
 267                         #clock-cells = <1>;
 268                         compatible = "allwinner,sun4i-a10-mmc-clk";
 269                         reg = <0x01c2008c 0x4>;
 270                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 271                         clock-output-names = "mmc1",
 272                                              "mmc1_output",
 273                                              "mmc1_sample";
 274                 };
 275
 276                 mmc2_clk: clk@01c20090 {
 277                         #clock-cells = <1>;
 278                         compatible = "allwinner,sun4i-a10-mmc-clk";
 279                         reg = <0x01c20090 0x4>;
 280                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 281                         clock-output-names = "mmc2",
 282                                              "mmc2_output",
 283                                              "mmc2_sample";
 284                 };
 285
 286                 ts_clk: clk@01c20098 {
 287                         #clock-cells = <0>;
 288                         compatible = "allwinner,sun4i-a10-mod0-clk";
 289                         reg = <0x01c20098 0x4>;
 290                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 291                         clock-output-names = "ts";
 292                 };
 293
 294                 ss_clk: clk@01c2009c {
 295                         #clock-cells = <0>;
 296                         compatible = "allwinner,sun4i-a10-mod0-clk";
 297                         reg = <0x01c2009c 0x4>;
 298                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 299                         clock-output-names = "ss";
 300                 };
 301
 302                 spi0_clk: clk@01c200a0 {
 303                         #clock-cells = <0>;
 304                         compatible = "allwinner,sun4i-a10-mod0-clk";
 305                         reg = <0x01c200a0 0x4>;
 306                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 307                         clock-output-names = "spi0";
 308                 };
 309
 310                 spi1_clk: clk@01c200a4 {
 311                         #clock-cells = <0>;
 312                         compatible = "allwinner,sun4i-a10-mod0-clk";
 313                         reg = <0x01c200a4 0x4>;
 314                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 315                         clock-output-names = "spi1";
 316                 };
 317
 318                 spi2_clk: clk@01c200a8 {
 319                         #clock-cells = <0>;
 320                         compatible = "allwinner,sun4i-a10-mod0-clk";
 321                         reg = <0x01c200a8 0x4>;
 322                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 323                         clock-output-names = "spi2";
 324                 };
 325
 326                 ir0_clk: clk@01c200b0 {
 327                         #clock-cells = <0>;
 328                         compatible = "allwinner,sun4i-a10-mod0-clk";
 329                         reg = <0x01c200b0 0x4>;
 330                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 331                         clock-output-names = "ir0";
 332                 };
 333
 334                 usb_clk: clk@01c200cc {
 335                         #clock-cells = <1>;
 336                         #reset-cells = <1>;
 337                         compatible = "allwinner,sun5i-a13-usb-clk";
 338                         reg = <0x01c200cc 0x4>;
 339                         clocks = <&pll6 1>;
 340                         clock-output-names = "usb_ohci0", "usb_phy";
 341                 };
 342
 343                 mbus_clk: clk@01c2015c {
 344                         #clock-cells = <0>;
 345                         compatible = "allwinner,sun5i-a13-mbus-clk";
 346                         reg = <0x01c2015c 0x4>;
 347                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 348                         clock-output-names = "mbus";
 349                 };
 350         };
 351
 352         soc@01c00000 {
 353                 compatible = "simple-bus";
 354                 #address-cells = <1>;
 355                 #size-cells = <1>;
 356                 ranges;
 357
 358                 dma: dma-controller@01c02000 {
 359                         compatible = "allwinner,sun4i-a10-dma";
 360                         reg = <0x01c02000 0x1000>;
 361                         interrupts = <27>;
 362                         clocks = <&ahb_gates 6>;
 363                         #dma-cells = <2>;
 364                 };
 365
 366                 spi0: spi@01c05000 {
 367                         compatible = "allwinner,sun4i-a10-spi";
 368                         reg = <0x01c05000 0x1000>;
 369                         interrupts = <10>;
 370                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 371                         clock-names = "ahb", "mod";
 372                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 373                                <&dma SUN4I_DMA_DEDICATED 26>;
 374                         dma-names = "rx", "tx";
 375                         status = "disabled";
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                 };
 379
 380                 spi1: spi@01c06000 {
 381                         compatible = "allwinner,sun4i-a10-spi";
 382                         reg = <0x01c06000 0x1000>;
 383                         interrupts = <11>;
 384                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 385                         clock-names = "ahb", "mod";
 386                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 387                                <&dma SUN4I_DMA_DEDICATED 8>;
 388                         dma-names = "rx", "tx";
 389                         status = "disabled";
 390                         #address-cells = <1>;
 391                         #size-cells = <0>;
 392                 };
 393
 394                 emac: ethernet@01c0b000 {
 395                         compatible = "allwinner,sun4i-a10-emac";
 396                         reg = <0x01c0b000 0x1000>;
 397                         interrupts = <55>;
 398                         clocks = <&ahb_gates 17>;
 399                         status = "disabled";
 400                 };
 401
 402                 mdio: mdio@01c0b080 {
 403                         compatible = "allwinner,sun4i-a10-mdio";
 404                         reg = <0x01c0b080 0x14>;
 405                         status = "disabled";
 406                         #address-cells = <1>;
 407                         #size-cells = <0>;
 408                 };
 409
 410                 mmc0: mmc@01c0f000 {
 411                         compatible = "allwinner,sun5i-a13-mmc";
 412                         reg = <0x01c0f000 0x1000>;
 413                         clocks = <&ahb_gates 8>,
 414                                  <&mmc0_clk 0>,
 415                                  <&mmc0_clk 1>,
 416                                  <&mmc0_clk 2>;
 417                         clock-names = "ahb",
 418                                       "mmc",
 419                                       "output",
 420                                       "sample";
 421                         interrupts = <32>;
 422                         status = "disabled";
 423                 };
 424
 425                 mmc1: mmc@01c10000 {
 426                         compatible = "allwinner,sun5i-a13-mmc";
 427                         reg = <0x01c10000 0x1000>;
 428                         clocks = <&ahb_gates 9>,
 429                                  <&mmc1_clk 0>,
 430                                  <&mmc1_clk 1>,
 431                                  <&mmc1_clk 2>;
 432                         clock-names = "ahb",
 433                                       "mmc",
 434                                       "output",
 435                                       "sample";
 436                         interrupts = <33>;
 437                         status = "disabled";
 438                 };
 439
 440                 mmc2: mmc@01c11000 {
 441                         compatible = "allwinner,sun5i-a13-mmc";
 442                         reg = <0x01c11000 0x1000>;
 443                         clocks = <&ahb_gates 10>,
 444                                  <&mmc2_clk 0>,
 445                                  <&mmc2_clk 1>,
 446                                  <&mmc2_clk 2>;
 447                         clock-names = "ahb",
 448                                       "mmc",
 449                                       "output",
 450                                       "sample";
 451                         interrupts = <34>;
 452                         status = "disabled";
 453                 };
 454
 455                 usbphy: phy@01c13400 {
 456                         #phy-cells = <1>;
 457                         compatible = "allwinner,sun5i-a13-usb-phy";
 458                         reg = <0x01c13400 0x10 0x01c14800 0x4>;
 459                         reg-names = "phy_ctrl", "pmu1";
 460                         clocks = <&usb_clk 8>;
 461                         clock-names = "usb_phy";
 462                         resets = <&usb_clk 0>, <&usb_clk 1>;
 463                         reset-names = "usb0_reset", "usb1_reset";
 464                         status = "disabled";
 465                 };
 466
 467                 ehci0: usb@01c14000 {
 468                         compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
 469                         reg = <0x01c14000 0x100>;
 470                         interrupts = <39>;
 471                         clocks = <&ahb_gates 1>;
 472                         phys = <&usbphy 1>;
 473                         phy-names = "usb";
 474                         status = "disabled";
 475                 };
 476
 477                 ohci0: usb@01c14400 {
 478                         compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
 479                         reg = <0x01c14400 0x100>;
 480                         interrupts = <40>;
 481                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 482                         phys = <&usbphy 1>;
 483                         phy-names = "usb";
 484                         status = "disabled";
 485                 };
 486
 487                 spi2: spi@01c17000 {
 488                         compatible = "allwinner,sun4i-a10-spi";
 489                         reg = <0x01c17000 0x1000>;
 490                         interrupts = <12>;
 491                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 492                         clock-names = "ahb", "mod";
 493                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 494                                <&dma SUN4I_DMA_DEDICATED 28>;
 495                         dma-names = "rx", "tx";
 496                         status = "disabled";
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                 };
 500
 501                 intc: interrupt-controller@01c20400 {
 502                         compatible = "allwinner,sun4i-a10-ic";
 503                         reg = <0x01c20400 0x400>;
 504                         interrupt-controller;
 505                         #interrupt-cells = <1>;
 506                 };
 507
 508                 pio: pinctrl@01c20800 {
 509                         compatible = "allwinner,sun5i-a10s-pinctrl";
 510                         reg = <0x01c20800 0x400>;
 511                         interrupts = <28>;
 512                         clocks = <&apb0_gates 5>;
 513                         gpio-controller;
 514                         interrupt-controller;
 515                         #interrupt-cells = <2>;
 516                         #size-cells = <0>;
 517                         #gpio-cells = <3>;
 518
 519                         uart0_pins_a: uart0@0 {
 520                                 allwinner,pins = "PB19", "PB20";
 521                                 allwinner,function = "uart0";
 522                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 523                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 524                         };
 525
 526                         uart2_pins_a: uart2@0 {
 527                                 allwinner,pins = "PC18", "PC19";
 528                                 allwinner,function = "uart2";
 529                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 530                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 531                         };
 532
 533                         uart3_pins_a: uart3@0 {
 534                                 allwinner,pins = "PG9", "PG10";
 535                                 allwinner,function = "uart3";
 536                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 537                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 538                         };
 539
 540                         emac_pins_a: emac0@0 {
 541                                 allwinner,pins = "PA0", "PA1", "PA2",
 542                                                 "PA3", "PA4", "PA5", "PA6",
 543                                                 "PA7", "PA8", "PA9", "PA10",
 544                                                 "PA11", "PA12", "PA13", "PA14",
 545                                                 "PA15", "PA16";
 546                                 allwinner,function = "emac";
 547                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 548                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 549                         };
 550
 551                         i2c0_pins_a: i2c0@0 {
 552                                 allwinner,pins = "PB0", "PB1";
 553                                 allwinner,function = "i2c0";
 554                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 555                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 556                         };
 557
 558                         i2c1_pins_a: i2c1@0 {
 559                                 allwinner,pins = "PB15", "PB16";
 560                                 allwinner,function = "i2c1";
 561                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 562                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 563                         };
 564
 565                         i2c2_pins_a: i2c2@0 {
 566                                 allwinner,pins = "PB17", "PB18";
 567                                 allwinner,function = "i2c2";
 568                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 569                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 570                         };
 571
 572                         mmc0_pins_a: mmc0@0 {
 573                                 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
 574                                 allwinner,function = "mmc0";
 575                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 576                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 577                         };
 578
 579                         mmc1_pins_a: mmc1@0 {
 580                                 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
 581                                 allwinner,function = "mmc1";
 582                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 583                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 584                         };
 585                 };
 586
 587                 timer@01c20c00 {
 588                         compatible = "allwinner,sun4i-a10-timer";
 589                         reg = <0x01c20c00 0x90>;
 590                         interrupts = <22>;
 591                         clocks = <&osc24M>;
 592                 };
 593
 594                 wdt: watchdog@01c20c90 {
 595                         compatible = "allwinner,sun4i-a10-wdt";
 596                         reg = <0x01c20c90 0x10>;
 597                 };
 598
 599                 lradc: lradc@01c22800 {
 600                         compatible = "allwinner,sun4i-a10-lradc-keys";
 601                         reg = <0x01c22800 0x100>;
 602                         interrupts = <31>;
 603                         status = "disabled";
 604                 };
 605
 606                 sid: eeprom@01c23800 {
 607                         compatible = "allwinner,sun4i-a10-sid";
 608                         reg = <0x01c23800 0x10>;
 609                 };
 610
 611                 rtp: rtp@01c25000 {
 612                         compatible = "allwinner,sun4i-a10-ts";
 613                         reg = <0x01c25000 0x100>;
 614                         interrupts = <29>;
 615                         #thermal-sensor-cells = <0>;
 616                 };
 617
 618                 uart0: serial@01c28000 {
 619                         compatible = "snps,dw-apb-uart";
 620                         reg = <0x01c28000 0x400>;
 621                         interrupts = <1>;
 622                         reg-shift = <2>;
 623                         reg-io-width = <4>;
 624                         clocks = <&apb1_gates 16>;
 625                         status = "disabled";
 626                 };
 627
 628                 uart1: serial@01c28400 {
 629                         compatible = "snps,dw-apb-uart";
 630                         reg = <0x01c28400 0x400>;
 631                         interrupts = <2>;
 632                         reg-shift = <2>;
 633                         reg-io-width = <4>;
 634                         clocks = <&apb1_gates 17>;
 635                         status = "disabled";
 636                 };
 637
 638                 uart2: serial@01c28800 {
 639                         compatible = "snps,dw-apb-uart";
 640                         reg = <0x01c28800 0x400>;
 641                         interrupts = <3>;
 642                         reg-shift = <2>;
 643                         reg-io-width = <4>;
 644                         clocks = <&apb1_gates 18>;
 645                         status = "disabled";
 646                 };
 647
 648                 uart3: serial@01c28c00 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x01c28c00 0x400>;
 651                         interrupts = <4>;
 652                         reg-shift = <2>;
 653                         reg-io-width = <4>;
 654                         clocks = <&apb1_gates 19>;
 655                         status = "disabled";
 656                 };
 657
 658                 i2c0: i2c@01c2ac00 {
 659                         #address-cells = <1>;
 660                         #size-cells = <0>;
 661                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 662                         reg = <0x01c2ac00 0x400>;
 663                         interrupts = <7>;
 664                         clocks = <&apb1_gates 0>;
 665                         status = "disabled";
 666                 };
 667
 668                 i2c1: i2c@01c2b000 {
 669                         #address-cells = <1>;
 670                         #size-cells = <0>;
 671                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 672                         reg = <0x01c2b000 0x400>;
 673                         interrupts = <8>;
 674                         clocks = <&apb1_gates 1>;
 675                         status = "disabled";
 676                 };
 677
 678                 i2c2: i2c@01c2b400 {
 679                         #address-cells = <1>;
 680                         #size-cells = <0>;
 681                         compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
 682                         reg = <0x01c2b400 0x400>;
 683                         interrupts = <9>;
 684                         clocks = <&apb1_gates 2>;
 685                         status = "disabled";
 686                 };
 687
 688                 timer@01c60000 {
 689                         compatible = "allwinner,sun5i-a13-hstimer";
 690                         reg = <0x01c60000 0x1000>;
 691                         interrupts = <82>, <83>;
 692                         clocks = <&ahb_gates 28>;
 693                 };
 694         };
 695 };