arch/arm/boot/dts/sun8i-h3.dtsi

   1 /*
   2  * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include "sunxi-h3-h5.dtsi"
  44
  45 / {
  46         cpu0_opp_table: opp_table0 {
  47                 compatible = "operating-points-v2";
  48                 opp-shared;
  49
  50                 opp-648000000 {
  51                         opp-hz = /bits/ 64 <648000000>;
  52                         opp-microvolt = <1040000 1040000 1300000>;
  53                         clock-latency-ns = <244144>; /* 8 32k periods */
  54                 };
  55
  56                 opp-816000000 {
  57                         opp-hz = /bits/ 64 <816000000>;
  58                         opp-microvolt = <1100000 1100000 1300000>;
  59                         clock-latency-ns = <244144>; /* 8 32k periods */
  60                 };
  61
  62                 opp-1008000000 {
  63                         opp-hz = /bits/ 64 <1008000000>;
  64                         opp-microvolt = <1200000 1200000 1300000>;
  65                         clock-latency-ns = <244144>; /* 8 32k periods */
  66                 };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         compatible = "arm,cortex-a7";
  75                         device_type = "cpu";
  76                         reg = <0>;
  77                         clocks = <&ccu CLK_CPUX>;
  78                         clock-names = "cpu";
  79                         operating-points-v2 = <&cpu0_opp_table>;
  80                         #cooling-cells = <2>;
  81                 };
  82
  83                 cpu1: cpu@1 {
  84                         compatible = "arm,cortex-a7";
  85                         device_type = "cpu";
  86                         reg = <1>;
  87                         clocks = <&ccu CLK_CPUX>;
  88                         clock-names = "cpu";
  89                         operating-points-v2 = <&cpu0_opp_table>;
  90                         #cooling-cells = <2>;
  91                 };
  92
  93                 cpu2: cpu@2 {
  94                         compatible = "arm,cortex-a7";
  95                         device_type = "cpu";
  96                         reg = <2>;
  97                         clocks = <&ccu CLK_CPUX>;
  98                         clock-names = "cpu";
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>;
 101                 };
 102
 103                 cpu3: cpu@3 {
 104                         compatible = "arm,cortex-a7";
 105                         device_type = "cpu";
 106                         reg = <3>;
 107                         clocks = <&ccu CLK_CPUX>;
 108                         clock-names = "cpu";
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                         #cooling-cells = <2>;
 111                 };
 112         };
 113
 114         pmu {
 115                 compatible = "arm,cortex-a7-pmu";
 116                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 117                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 120                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 121         };
 122
 123         timer {
 124                 compatible = "arm,armv7-timer";
 125                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 126                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 127                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 128                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 129         };
 130
 131         soc {
 132                 deinterlace: deinterlace@1400000 {
 133                         compatible = "allwinner,sun8i-h3-deinterlace";
 134                         reg = <0x01400000 0x20000>;
 135                         clocks = <&ccu CLK_BUS_DEINTERLACE>,
 136                                  <&ccu CLK_DEINTERLACE>,
 137                                  <&ccu CLK_DRAM_DEINTERLACE>;
 138                         clock-names = "bus", "mod", "ram";
 139                         resets = <&ccu RST_BUS_DEINTERLACE>;
 140                         interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 141                         interconnects = <&mbus 9>;
 142                         interconnect-names = "dma-mem";
 143                 };
 144
 145                 syscon: system-control@1c00000 {
 146                         compatible = "allwinner,sun8i-h3-system-control";
 147                         reg = <0x01c00000 0x1000>;
 148                         #address-cells = <1>;
 149                         #size-cells = <1>;
 150                         ranges;
 151
 152                         sram_c: sram@1d00000 {
 153                                 compatible = "mmio-sram";
 154                                 reg = <0x01d00000 0x80000>;
 155                                 #address-cells = <1>;
 156                                 #size-cells = <1>;
 157                                 ranges = <0 0x01d00000 0x80000>;
 158
 159                                 ve_sram: sram-section@0 {
 160                                         compatible = "allwinner,sun8i-h3-sram-c1",
 161                                                      "allwinner,sun4i-a10-sram-c1";
 162                                         reg = <0x000000 0x80000>;
 163                                 };
 164                         };
 165                 };
 166
 167                 video-codec@1c0e000 {
 168                         compatible = "allwinner,sun8i-h3-video-engine";
 169                         reg = <0x01c0e000 0x1000>;
 170                         clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
 171                                  <&ccu CLK_DRAM_VE>;
 172                         clock-names = "ahb", "mod", "ram";
 173                         resets = <&ccu RST_BUS_VE>;
 174                         interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 175                         allwinner,sram = <&ve_sram 1>;
 176                 };
 177
 178                 crypto: crypto@1c15000 {
 179                         compatible = "allwinner,sun8i-h3-crypto";
 180                         reg = <0x01c15000 0x1000>;
 181                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 182                         clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
 183                         clock-names = "bus", "mod";
 184                         resets = <&ccu RST_BUS_CE>;
 185                 };
 186
 187                 mali: gpu@1c40000 {
 188                         compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
 189                         reg = <0x01c40000 0x10000>;
 190                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 191                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 192                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
 194                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
 195                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 196                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 197                         interrupt-names = "gp",
 198                                           "gpmmu",
 199                                           "pp0",
 200                                           "ppmmu0",
 201                                           "pp1",
 202                                           "ppmmu1",
 203                                           "pmu";
 204                         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 205                         clock-names = "bus", "core";
 206                         resets = <&ccu RST_BUS_GPU>;
 207
 208                         assigned-clocks = <&ccu CLK_GPU>;
 209                         assigned-clock-rates = <384000000>;
 210                 };
 211
 212                 ths: thermal-sensor@1c25000 {
 213                         compatible = "allwinner,sun8i-h3-ths";
 214                         reg = <0x01c25000 0x400>;
 215                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 216                         resets = <&ccu RST_BUS_THS>;
 217                         clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
 218                         clock-names = "bus", "mod";
 219                         nvmem-cells = <&ths_calibration>;
 220                         nvmem-cell-names = "calibration";
 221                         #thermal-sensor-cells = <0>;
 222                 };
 223         };
 224
 225         thermal-zones {
 226                 cpu_thermal: cpu-thermal {
 227                         polling-delay-passive = <0>;
 228                         polling-delay = <0>;
 229                         thermal-sensors = <&ths 0>;
 230                 };
 231         };
 232 };
 233
 234 &ccu {
 235         compatible = "allwinner,sun8i-h3-ccu";
 236 };
 237
 238 &display_clocks {
 239         compatible = "allwinner,sun8i-h3-de2-clk";
 240 };
 241
 242 &mmc0 {
 243         compatible = "allwinner,sun7i-a20-mmc";
 244         clocks = <&ccu CLK_BUS_MMC0>,
 245                  <&ccu CLK_MMC0>,
 246                  <&ccu CLK_MMC0_OUTPUT>,
 247                  <&ccu CLK_MMC0_SAMPLE>;
 248         clock-names = "ahb",
 249                       "mmc",
 250                       "output",
 251                       "sample";
 252 };
 253
 254 &mmc1 {
 255         compatible = "allwinner,sun7i-a20-mmc";
 256         clocks = <&ccu CLK_BUS_MMC1>,
 257                  <&ccu CLK_MMC1>,
 258                  <&ccu CLK_MMC1_OUTPUT>,
 259                  <&ccu CLK_MMC1_SAMPLE>;
 260         clock-names = "ahb",
 261                       "mmc",
 262                       "output",
 263                       "sample";
 264 };
 265
 266 &mmc2 {
 267         compatible = "allwinner,sun7i-a20-mmc";
 268         clocks = <&ccu CLK_BUS_MMC2>,
 269                  <&ccu CLK_MMC2>,
 270                  <&ccu CLK_MMC2_OUTPUT>,
 271                  <&ccu CLK_MMC2_SAMPLE>;
 272         clock-names = "ahb",
 273                       "mmc",
 274                       "output",
 275                       "sample";
 276 };
 277
 278 &pio {
 279         compatible = "allwinner,sun8i-h3-pinctrl";
 280 };
 281
 282 &rtc {
 283         compatible = "allwinner,sun8i-h3-rtc";
 284 };
 285
 286 &sid {
 287         compatible = "allwinner,sun8i-h3-sid";
 288 };