1 // SPDX-License-Identifier: GPL-2.0
2 #include "tegra20.dtsi"
5 * Toradex Colibri T20 Module Device Tree
6 * Compatible for Revisions Colibri T20 256MB V1.1B, V1.2A;
7 * Colibri T20 256MB IT V1.2A; Colibri T20 512MB V1.1C, V1.2A;
8 * Colibri T20 512MB IT V1.2A
13 * Set memory to 256 MB to be safe as this could be used on
14 * 256 or 512 MB module. It is expected from bootloader
15 * to fix this up for 512 MB version.
17 reg = <0x00000000 0x10000000>;
22 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
24 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
25 pll-supply = <®_1v8_avdd_hdmi_pll>;
26 vdd-supply = <®_3v3_avdd_hdmi>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&state_default>;
34 state_default: pinmux {
35 /* Analogue Audio AC97 to WM9712 (On-module) */
37 nvidia,pins = "cdev1";
38 nvidia,function = "plla_out";
39 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
40 nvidia,tristate = <TEGRA_PIN_DISABLE>;
44 nvidia,function = "dap3";
45 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
46 nvidia,tristate = <TEGRA_PIN_DISABLE>;
50 * AC97_RESET, ULPI_RESET, AC97_INT aka WM9712 GENIRQ
51 * (All on-module), SODIMM Pin 45 Wakeup
55 nvidia,function = "rsvd2";
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
61 * Buffer Enables for nPWE and RDnWR (On-module,
62 * see GPIO hogging further down below)
66 nvidia,function = "rsvd4";
67 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
68 nvidia,tristate = <TEGRA_PIN_DISABLE>;
72 * CLK_32K_OUT, CORE_PWR_REQ, CPU_PWR_REQ, PWR_INT_N,
73 * SYS_CLK_REQ (All on-module)
77 nvidia,function = "pwr_on";
78 nvidia,tristate = <TEGRA_PIN_DISABLE>;
82 * Colibri Address/Data Bus (GMI)
83 * Note: spid and spie optionally used for SPI1
86 nvidia,pins = "atc", "atd", "ate", "dap1",
87 "dap2", "dap4", "gmd", "gpu",
88 "irrx", "irtx", "spia", "spib",
89 "spic", "spid", "spie", "uca",
91 nvidia,function = "gmi";
92 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
93 nvidia,tristate = <TEGRA_PIN_ENABLE>;
95 /* Further pins may be used as GPIOs */
97 nvidia,pins = "lpw0", "lsc1", "lsck", "lsda";
98 nvidia,function = "hdmi";
99 nvidia,tristate = <TEGRA_PIN_ENABLE>;
102 nvidia,pins = "lcsn", "ldc", "lm0", "lsdi";
103 nvidia,function = "rsvd4";
104 nvidia,tristate = <TEGRA_PIN_ENABLE>;
110 nvidia,function = "rsvd1";
111 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
112 nvidia,tristate = <TEGRA_PIN_ENABLE>;
115 /* Colibri Backlight PWM<A>, PWM<B> */
118 nvidia,function = "pwm";
119 nvidia,tristate = <TEGRA_PIN_ENABLE>;
125 nvidia,function = "i2c2";
126 nvidia,pull = <TEGRA_PIN_PULL_UP>;
127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
132 * Note: dtf optionally used for I2C3
135 nvidia,pins = "dtf", "spdi";
136 nvidia,function = "rsvd2";
137 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
138 nvidia,tristate = <TEGRA_PIN_ENABLE>;
142 * Colibri Ethernet (On-module)
143 * ULPI EHCI instance 1 USB2_DP/N -> AX88772B
146 nvidia,pins = "uaa", "uab", "uda";
147 nvidia,function = "ulpi";
148 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
149 nvidia,tristate = <TEGRA_PIN_DISABLE>;
152 nvidia,pins = "cdev2";
153 nvidia,function = "pllp_out4";
154 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
155 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 /* Colibri HOTPLUG_DETECT (HDMI) */
160 nvidia,pins = "hdint";
161 nvidia,function = "hdmi";
162 nvidia,tristate = <TEGRA_PIN_ENABLE>;
168 nvidia,function = "i2c1";
169 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
170 nvidia,tristate = <TEGRA_PIN_ENABLE>;
174 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
175 * today's display need DE, disable LCD_M1
179 nvidia,function = "rsvd3";
180 nvidia,tristate = <TEGRA_PIN_ENABLE>;
183 /* Colibri LCD (L_* resp. LDD<*>) */
185 nvidia,pins = "ld0", "ld1", "ld2", "ld3",
186 "ld4", "ld5", "ld6", "ld7",
187 "ld8", "ld9", "ld10", "ld11",
188 "ld12", "ld13", "ld14", "ld15",
189 "ld16", "ld17", "lhs", "lsc0",
191 nvidia,function = "displaya";
192 nvidia,tristate = <TEGRA_PIN_ENABLE>;
194 /* Colibri LCD (Optional 24 BPP Support) */
196 nvidia,pins = "ldi", "lhp0", "lhp1", "lhp2",
198 nvidia,function = "displaya";
199 nvidia,tristate = <TEGRA_PIN_ENABLE>;
204 nvidia,pins = "atb", "gma";
205 nvidia,function = "sdio4";
206 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
207 nvidia,tristate = <TEGRA_PIN_ENABLE>;
213 nvidia,function = "gmi_int";
214 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
215 nvidia,tristate = <TEGRA_PIN_ENABLE>;
218 /* Colibri MMC (Optional 8-bit) */
221 nvidia,function = "sdio4";
222 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
227 * Colibri Parallel Camera (Optional)
228 * pins multiplexed with others and therefore disabled
229 * Note: dta used for BL_ON by default
232 nvidia,pins = "csus";
233 nvidia,function = "vi_sensor_clk";
234 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
235 nvidia,tristate = <TEGRA_PIN_ENABLE>;
238 nvidia,pins = "dtb", "dtc", "dtd";
239 nvidia,function = "vi";
240 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
241 nvidia,tristate = <TEGRA_PIN_ENABLE>;
244 /* Colibri PWM<C>, PWM<D> */
246 nvidia,pins = "sdb", "sdd";
247 nvidia,function = "pwm";
248 nvidia,tristate = <TEGRA_PIN_ENABLE>;
253 nvidia,pins = "slxa", "slxc", "slxd", "slxk";
254 nvidia,function = "spi4";
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_ENABLE>;
261 nvidia,pins = "sdio1";
262 nvidia,function = "uarta";
263 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
264 nvidia,tristate = <TEGRA_PIN_ENABLE>;
267 nvidia,pins = "lpw1";
268 nvidia,function = "rsvd3";
269 nvidia,tristate = <TEGRA_PIN_ENABLE>;
272 nvidia,pins = "lpw2";
273 nvidia,function = "hdmi";
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
280 nvidia,function = "uartd";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_ENABLE>;
288 nvidia,function = "irda";
289 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
293 /* Colibri USB_CDET */
295 nvidia,pins = "spdo";
296 nvidia,function = "rsvd2";
297 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
298 nvidia,tristate = <TEGRA_PIN_ENABLE>;
301 /* Colibri USBH_OC */
303 nvidia,pins = "spih";
304 nvidia,function = "spi2_alt";
305 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
306 nvidia,tristate = <TEGRA_PIN_ENABLE>;
309 /* Colibri USBH_PEN */
311 nvidia,pins = "spig";
312 nvidia,function = "spi2_alt";
313 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
317 /* Colibri VGA not supported */
319 nvidia,pins = "crtp";
320 nvidia,function = "crt";
321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322 nvidia,tristate = <TEGRA_PIN_ENABLE>;
325 /* I2C3 (Optional) */
328 nvidia,function = "i2c3";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_ENABLE>;
335 nvidia,pins = "gpu7";
336 nvidia,function = "rtck";
337 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
338 nvidia,tristate = <TEGRA_PIN_ENABLE>;
342 * LAN_RESET, LAN_EXT_WAKEUP and LAN_PME
347 nvidia,function = "rsvd2";
348 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
349 nvidia,tristate = <TEGRA_PIN_DISABLE>;
353 * LAN_V_BUS, VDD_FAULT, BATT_FAULT, WM9712 PENDOWN
354 * (All On-module); Colibri CAN_INT
358 nvidia,function = "rsvd1";
359 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
360 nvidia,tristate = <TEGRA_PIN_DISABLE>;
363 /* NAND (On-module) */
365 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
367 nvidia,function = "nand";
368 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
369 nvidia,tristate = <TEGRA_PIN_DISABLE>;
372 /* Onewire (Optional) */
375 nvidia,function = "owr";
376 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
380 /* Power I2C (On-module) */
382 nvidia,pins = "i2cp";
383 nvidia,function = "i2cp";
384 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
385 nvidia,tristate = <TEGRA_PIN_DISABLE>;
391 nvidia,function = "gmi";
392 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
398 * Note: spid and spie used for Colibri Address/Data
402 nvidia,pins = "spid", "spie", "spif";
403 nvidia,function = "spi1";
404 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
409 * THERMD_ALERT# (On-module), unlatched I2C address pin
410 * of LM95245 temperature sensor therefore requires
414 nvidia,pins = "lvp0";
415 nvidia,function = "rsvd3";
416 nvidia,tristate = <TEGRA_PIN_ENABLE>;
421 ac97: ac97@70002000 {
423 nvidia,codec-reset-gpio =
424 <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_HIGH>;
425 nvidia,codec-sync-gpio =
426 <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
430 compatible = "nvidia,tegra20-hsuart";
434 compatible = "nvidia,tegra20-hsuart";
437 nand-controller@70008000 {
442 #address-cells = <1>;
444 nand-bus-width = <8>;
446 nand-ecc-algo = "bch";
449 wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
454 * GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier
458 clock-frequency = <400000>;
461 /* DDC_SCL/SDA on X3 pin 15/16 (e.g. display EDID) */
462 hdmi_ddc: i2c@7000c400 {
463 clock-frequency = <10000>;
466 /* GEN2_I2C: unused */
468 /* CAM/GEN3_I2C: used as EXT_IO1/2 GPIOs on SODIMM pin 133/127 */
470 /* PWR_I2C: power I2C to PMIC and temperature sensor (On-module) */
473 clock-frequency = <100000>;
476 compatible = "ti,tps6586x";
478 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
479 ti,system-power-controller;
482 sys-supply = <®_module_3v3>;
483 vin-sm0-supply = <®_3v3_vsys>;
484 vin-sm1-supply = <®_3v3_vsys>;
485 vin-sm2-supply = <®_3v3_vsys>;
486 vinldo01-supply = <®_1v8_vdd_ddr2>;
487 vinldo23-supply = <®_module_3v3>;
488 vinldo4-supply = <®_module_3v3>;
489 vinldo678-supply = <®_module_3v3>;
490 vinldo9-supply = <®_module_3v3>;
494 regulator-name = "VSYS_3.3V";
499 regulator-name = "VDD_CORE_1.2V";
500 regulator-min-microvolt = <1200000>;
501 regulator-max-microvolt = <1200000>;
506 regulator-name = "VDD_CPU_1.0V";
507 regulator-min-microvolt = <1000000>;
508 regulator-max-microvolt = <1000000>;
512 reg_1v8_vdd_ddr2: sm2 {
513 regulator-name = "VDD_DDR2_1.8V";
514 regulator-min-microvolt = <1800000>;
515 regulator-max-microvolt = <1800000>;
519 /* LDO0 is not connected to anything */
522 * +3.3V_ENABLE_N switching via FET:
523 * AVDD_AUDIO_S and +3.3V
524 * see also +3.3V fixed supply
527 regulator-name = "AVDD_PLL_1.1V";
528 regulator-min-microvolt = <1100000>;
529 regulator-max-microvolt = <1100000>;
534 regulator-name = "VDD_RTC_1.2V";
535 regulator-min-microvolt = <1200000>;
536 regulator-max-microvolt = <1200000>;
539 /* LDO3 is not connected to anything */
542 regulator-name = "VDDIO_SYS_1.8V";
543 regulator-min-microvolt = <1800000>;
544 regulator-max-microvolt = <1800000>;
548 /* Switched via FET from regular +3.3V */
550 regulator-name = "+3.3V_USB";
551 regulator-min-microvolt = <3300000>;
552 regulator-max-microvolt = <3300000>;
557 regulator-name = "AVDD_VDAC_2.85V";
558 regulator-min-microvolt = <2850000>;
559 regulator-max-microvolt = <2850000>;
562 reg_3v3_avdd_hdmi: ldo7 {
563 regulator-name = "AVDD_HDMI_3.3V";
564 regulator-min-microvolt = <3300000>;
565 regulator-max-microvolt = <3300000>;
568 reg_1v8_avdd_hdmi_pll: ldo8 {
569 regulator-name = "AVDD_HDMI_PLL_1.8V";
570 regulator-min-microvolt = <1800000>;
571 regulator-max-microvolt = <1800000>;
575 regulator-name = "VDDIO_RX_DDR_2.85V";
576 regulator-min-microvolt = <2850000>;
577 regulator-max-microvolt = <2850000>;
582 regulator-name = "VCC_BATT";
583 regulator-min-microvolt = <3300000>;
584 regulator-max-microvolt = <3300000>;
590 /* LM95245 temperature sensor */
592 compatible = "national,lm95245";
598 nvidia,suspend-mode = <1>;
599 nvidia,cpu-pwr-good-time = <5000>;
600 nvidia,cpu-pwr-off-time = <5000>;
601 nvidia,core-pwr-good-time = <3845 3845>;
602 nvidia,core-pwr-off-time = <3875>;
603 nvidia,sys-clock-req-active-high;
605 /* Set SLEEP MODE bit in SUPPLYENE register of TPS658643 PMIC */
607 nvidia,i2c-controller-id = <3>;
608 nvidia,bus-addr = <0x34>;
609 nvidia,reg-addr = <0x14>;
610 nvidia,reg-data = <0x8>;
614 memory-controller@7000f400 {
617 compatible = "nvidia,tegra20-emc-table";
618 clock-frequency = <83250>;
619 nvidia,emc-registers = <0x00000005 0x00000011
620 0x00000004 0x00000002 0x00000004 0x00000004
621 0x00000001 0x0000000a 0x00000002 0x00000002
622 0x00000001 0x00000001 0x00000003 0x00000004
623 0x00000003 0x00000009 0x0000000c 0x0000025f
624 0x00000000 0x00000003 0x00000003 0x00000002
625 0x00000002 0x00000001 0x00000008 0x000000c8
626 0x00000003 0x00000005 0x00000003 0x0000000c
627 0x00000002 0x00000000 0x00000000 0x00000002
628 0x00000000 0x00000000 0x00000083 0x00520006
629 0x00000010 0x00000008 0x00000000 0x00000000
630 0x00000000 0x00000000 0x00000000 0x00000000>;
634 compatible = "nvidia,tegra20-emc-table";
635 clock-frequency = <133200>;
636 nvidia,emc-registers = <0x00000008 0x00000019
637 0x00000006 0x00000002 0x00000004 0x00000004
638 0x00000001 0x0000000a 0x00000002 0x00000002
639 0x00000002 0x00000001 0x00000003 0x00000004
640 0x00000003 0x00000009 0x0000000c 0x0000039f
641 0x00000000 0x00000003 0x00000003 0x00000002
642 0x00000002 0x00000001 0x00000008 0x000000c8
643 0x00000003 0x00000007 0x00000003 0x0000000c
644 0x00000002 0x00000000 0x00000000 0x00000002
645 0x00000000 0x00000000 0x00000083 0x00510006
646 0x00000010 0x00000008 0x00000000 0x00000000
647 0x00000000 0x00000000 0x00000000 0x00000000>;
651 compatible = "nvidia,tegra20-emc-table";
652 clock-frequency = <166500>;
653 nvidia,emc-registers = <0x0000000a 0x00000021
654 0x00000008 0x00000003 0x00000004 0x00000004
655 0x00000002 0x0000000a 0x00000003 0x00000003
656 0x00000002 0x00000001 0x00000003 0x00000004
657 0x00000003 0x00000009 0x0000000c 0x000004df
658 0x00000000 0x00000003 0x00000003 0x00000003
659 0x00000003 0x00000001 0x00000009 0x000000c8
660 0x00000003 0x00000009 0x00000004 0x0000000c
661 0x00000002 0x00000000 0x00000000 0x00000002
662 0x00000000 0x00000000 0x00000083 0x004f0006
663 0x00000010 0x00000008 0x00000000 0x00000000
664 0x00000000 0x00000000 0x00000000 0x00000000>;
668 compatible = "nvidia,tegra20-emc-table";
669 clock-frequency = <333000>;
670 nvidia,emc-registers = <0x00000014 0x00000041
671 0x0000000f 0x00000005 0x00000004 0x00000005
672 0x00000003 0x0000000a 0x00000005 0x00000005
673 0x00000004 0x00000001 0x00000003 0x00000004
674 0x00000003 0x00000009 0x0000000c 0x000009ff
675 0x00000000 0x00000003 0x00000003 0x00000005
676 0x00000005 0x00000001 0x0000000e 0x000000c8
677 0x00000003 0x00000011 0x00000006 0x0000000c
678 0x00000002 0x00000000 0x00000000 0x00000002
679 0x00000000 0x00000000 0x00000083 0x00380006
680 0x00000010 0x00000008 0x00000000 0x00000000
681 0x00000000 0x00000000 0x00000000 0x00000000>;
685 /* EHCI instance 1: ULPI PHY -> AX88772B (On-module) */
688 #address-cells = <1>;
693 local-mac-address = [00 00 00 00 00 00];
699 nvidia,phy-reset-gpio =
700 <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_LOW>;
701 vbus-supply = <®_lan_v_bus>;
705 compatible = "fixed-clock";
707 clock-frequency = <32768>;
710 reg_lan_v_bus: regulator-lan-v-bus {
711 compatible = "regulator-fixed";
712 regulator-name = "LAN_V_BUS";
713 regulator-min-microvolt = <5000000>;
714 regulator-max-microvolt = <5000000>;
716 gpio = <&gpio TEGRA_GPIO(BB, 1) GPIO_ACTIVE_HIGH>;
719 reg_module_3v3: regulator-module-3v3 {
720 compatible = "regulator-fixed";
721 regulator-name = "+V3.3";
722 regulator-min-microvolt = <3300000>;
723 regulator-max-microvolt = <3300000>;
728 compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
729 "nvidia,tegra-audio-wm9712";
730 nvidia,model = "Toradex Colibri T20";
731 nvidia,audio-routing =
732 "Headphone", "HPOUTL",
733 "Headphone", "HPOUTR",
737 nvidia,ac97-controller = <&ac97>;
738 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
739 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
740 <&tegra_car TEGRA20_CLK_CDEV1>;
741 clock-names = "pll_a", "pll_a_out0", "mclk";
748 gpios = <TEGRA_GPIO(V, 4) GPIO_ACTIVE_HIGH>;
750 line-name = "LAN_RESET#";
753 /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */
756 gpios = <TEGRA_GPIO(T, 5) GPIO_ACTIVE_HIGH>;
758 line-name = "Tri-state nPWE";
761 /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */
764 gpios = <TEGRA_GPIO(T, 6) GPIO_ACTIVE_HIGH>;
766 line-name = "Not tri-state RDnWR";