arch/arm/boot/dts/uniphier-ph1-sld8.dtsi

   1 /*
   2  * Device Tree Source for UniPhier PH1-sLD8 SoC
   3  *
   4  * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 /include/ "skeleton.dtsi"
  46
  47 / {
  48         compatible = "socionext,ph1-sld8";
  49
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53
  54                 cpu@0 {
  55                         device_type = "cpu";
  56                         compatible = "arm,cortex-a9";
  57                         reg = <0>;
  58                 };
  59         };
  60
  61         clocks {
  62                 arm_timer_clk: arm_timer_clk {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <50000000>;
  66                 };
  67
  68                 uart_clk: uart_clk {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <80000000>;
  72                 };
  73         };
  74
  75         soc {
  76                 compatible = "simple-bus";
  77                 #address-cells = <1>;
  78                 #size-cells = <1>;
  79                 ranges;
  80                 interrupt-parent = <&intc>;
  81
  82                 extbus: extbus {
  83                         compatible = "simple-bus";
  84                         #address-cells = <2>;
  85                         #size-cells = <1>;
  86                 };
  87
  88                 serial0: serial@54006800 {
  89                         compatible = "socionext,uniphier-uart";
  90                         status = "disabled";
  91                         reg = <0x54006800 0x40>;
  92                         interrupts = <0 33 4>;
  93                         clocks = <&uart_clk>;
  94                         fifo-size = <64>;
  95                 };
  96
  97                 serial1: serial@54006900 {
  98                         compatible = "socionext,uniphier-uart";
  99                         status = "disabled";
 100                         reg = <0x54006900 0x40>;
 101                         interrupts = <0 35 4>;
 102                         clocks = <&uart_clk>;
 103                         fifo-size = <64>;
 104                 };
 105
 106                 serial2: serial@54006a00 {
 107                         compatible = "socionext,uniphier-uart";
 108                         status = "disabled";
 109                         reg = <0x54006a00 0x40>;
 110                         interrupts = <0 37 4>;
 111                         clocks = <&uart_clk>;
 112                         fifo-size = <64>;
 113                 };
 114
 115                 serial3: serial@54006b00 {
 116                         compatible = "socionext,uniphier-uart";
 117                         status = "disabled";
 118                         reg = <0x54006b00 0x40>;
 119                         interrupts = <0 29 4>;
 120                         clocks = <&uart_clk>;
 121                         fifo-size = <64>;
 122                 };
 123
 124                 system-bus-controller-misc@59800000 {
 125                         compatible = "socionext,uniphier-system-bus-controller-misc",
 126                                      "syscon";
 127                         reg = <0x59800000 0x2000>;
 128                 };
 129
 130                 timer@60000200 {
 131                         compatible = "arm,cortex-a9-global-timer";
 132                         reg = <0x60000200 0x20>;
 133                         interrupts = <1 11 0x104>;
 134                         clocks = <&arm_timer_clk>;
 135                 };
 136
 137                 timer@60000600 {
 138                         compatible = "arm,cortex-a9-twd-timer";
 139                         reg = <0x60000600 0x20>;
 140                         interrupts = <1 13 0x104>;
 141                         clocks = <&arm_timer_clk>;
 142                 };
 143
 144                 intc: interrupt-controller@60001000 {
 145                         compatible = "arm,cortex-a9-gic";
 146                         #interrupt-cells = <3>;
 147                         interrupt-controller;
 148                         reg = <0x60001000 0x1000>,
 149                               <0x60000100 0x100>;
 150                 };
 151         };
 152 };