2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/ptrace.h>
20 #include <asm/asm-offsets.h>
21 #include <asm/memory.h>
22 #include <asm/thread_info.h>
23 #include <asm/system.h>
25 #ifdef CONFIG_DEBUG_LL
26 #include <mach/debug-macro.S>
30 * swapper_pg_dir is the virtual address of the initial page table.
31 * We place the page tables 16K below KERNEL_RAM_VADDR. Therefore, we must
32 * make sure that KERNEL_RAM_VADDR is correctly set. Currently, we expect
33 * the least significant 16 bits to be 0x8000, but we could probably
34 * relax this restriction to KERNEL_RAM_VADDR >= PAGE_OFFSET + 0x4000.
36 #define KERNEL_RAM_VADDR (PAGE_OFFSET + TEXT_OFFSET)
37 #if (KERNEL_RAM_VADDR & 0xffff) != 0x8000
38 #error KERNEL_RAM_VADDR must start at 0xXXXX8000
42 .equ swapper_pg_dir, KERNEL_RAM_VADDR - 0x4000
44 .macro pgtbl, rd, phys
45 add \rd, \phys, #TEXT_OFFSET - 0x4000
48 #ifdef CONFIG_XIP_KERNEL
49 #define KERNEL_START XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
50 #define KERNEL_END _edata_loc
52 #define KERNEL_START KERNEL_RAM_VADDR
53 #define KERNEL_END _end
57 * Kernel startup entry point.
58 * ---------------------------
60 * This is normally called from the decompressor code. The requirements
61 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
62 * r1 = machine nr, r2 = atags pointer.
64 * This code is mostly position independent, so if you link the kernel at
65 * 0xc0008000, you call this at __pa(0xc0008000).
67 * See linux/arch/arm/tools/mach-types for the complete list of machine
70 * We're trying to keep crap to a minimum; DO NOT add any machine specific
71 * crap here - that's what the boot loader (or in extreme, well justified
72 * circumstances, zImage) is for.
76 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
78 mrc p15, 0, r9, c0, c0 @ get processor id
79 bl __lookup_processor_type @ r5=procinfo r9=cpuid
80 movs r10, r5 @ invalid processor (r5=0)?
81 THUMB( it eq ) @ force fixup-able long branch encoding
82 beq __error_p @ yes, error 'p'
84 #ifndef CONFIG_XIP_KERNEL
87 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
88 add r8, r8, r4 @ PHYS_OFFSET
90 ldr r8, =PLAT_PHYS_OFFSET
94 * r1 = machine no, r2 = atags,
95 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
98 #ifdef CONFIG_SMP_ON_UP
101 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
104 bl __create_page_tables
107 * The following calls CPU specific code in a position independent
108 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
109 * xxx_proc_info structure selected by __lookup_processor_type
110 * above. On return, the CPU will be ready for the MMU to be
111 * turned on, and r0 will hold the CPU control register value.
113 ldr r13, =__mmap_switched @ address to jump to after
114 @ mmu has been enabled
115 adr lr, BSYM(1f) @ return (PIC) address
116 ARM( add pc, r10, #PROCINFO_INITFUNC )
117 THUMB( add r12, r10, #PROCINFO_INITFUNC )
122 #ifndef CONFIG_XIP_KERNEL
128 * Setup the initial page tables. We only setup the barest
129 * amount which are required to get the kernel running, which
130 * generally means mapping in the kernel code.
132 * r8 = phys_offset, r9 = cpuid, r10 = procinfo
135 * r0, r3, r5-r7 corrupted
136 * r4 = physical page table address
138 __create_page_tables:
139 pgtbl r4, r8 @ page table address
142 * Clear the 16K level 1 swapper page table
154 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
157 * Create identity mapping to cater for __enable_mmu.
158 * This identity mapping will be removed by paging_init().
160 adr r0, __enable_mmu_loc
161 ldmia r0, {r3, r5, r6}
162 sub r0, r0, r3 @ virt->phys offset
163 add r5, r5, r0 @ phys __enable_mmu
164 add r6, r6, r0 @ phys __enable_mmu_end
168 1: orr r3, r7, r5, lsl #20 @ flags + kernel base
169 str r3, [r4, r5, lsl #2] @ identity mapping
171 addne r5, r5, #1 @ next section
175 * Now setup the pagetables for our kernel direct
180 orr r3, r7, r3, lsl #20
181 add r0, r4, #(KERNEL_START & 0xff000000) >> 18
182 str r3, [r0, #(KERNEL_START & 0x00f00000) >> 18]!
183 ldr r6, =(KERNEL_END - 1)
185 add r6, r4, r6, lsr #18
191 #ifdef CONFIG_XIP_KERNEL
193 * Map some ram to cover our .data and .bss areas.
195 add r3, r8, #TEXT_OFFSET
197 add r0, r4, #(KERNEL_RAM_VADDR & 0xff000000) >> 18
198 str r3, [r0, #(KERNEL_RAM_VADDR & 0x00f00000) >> 18]!
201 add r6, r4, r6, lsr #18
209 * Then map boot params address in r2 or
210 * the first 1MB of ram if boot params address is not specified.
216 add r3, r3, #PAGE_OFFSET
217 add r3, r4, r3, lsr #18
221 #ifdef CONFIG_DEBUG_LL
222 #ifndef CONFIG_DEBUG_ICEDCC
224 * Map in IO space for serial debugging.
225 * This allows debug messages to be output
226 * via a serial console before paging_init.
234 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
235 cmp r3, #0x0800 @ limit to 512MB
239 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
240 orr r3, r7, r3, lsl #20
246 #else /* CONFIG_DEBUG_ICEDCC */
247 /* we don't need any serial debugging mappings for ICEDCC */
248 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
249 #endif /* !CONFIG_DEBUG_ICEDCC */
251 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
253 * If we're using the NetWinder or CATS, we also need to map
254 * in the 16550-type serial port for the debug messages
256 add r0, r4, #0xff000000 >> 18
257 orr r3, r7, #0x7c000000
260 #ifdef CONFIG_ARCH_RPC
262 * Map in screen at 0x02000000 & SCREEN2_BASE
263 * Similar reasons here - for debug. This is
264 * only for Acorn RiscPC architectures.
266 add r0, r4, #0x02000000 >> 18
267 orr r3, r7, #0x02000000
269 add r0, r4, #0xd8000000 >> 18
274 ENDPROC(__create_page_tables)
280 .long __enable_mmu_end
282 #if defined(CONFIG_SMP)
284 ENTRY(secondary_startup)
286 * Common entry point for secondary CPUs.
288 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
289 * the processor type - there is no need to check the machine type
290 * as it has already been validated by the primary processor.
292 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9
293 mrc p15, 0, r9, c0, c0 @ get processor id
294 bl __lookup_processor_type
295 movs r10, r5 @ invalid processor?
296 moveq r0, #'p' @ yes, error 'p'
297 THUMB( it eq ) @ force fixup-able long branch encoding
301 * Use the page tables supplied from __cpu_up.
303 adr r4, __secondary_data
304 ldmia r4, {r5, r7, r12} @ address to jump to after
305 sub r4, r4, r5 @ mmu has been enabled
306 ldr r4, [r7, r4] @ get secondary_data.pgdir
307 adr lr, BSYM(__enable_mmu) @ return address
308 mov r13, r12 @ __secondary_switched address
309 ARM( add pc, r10, #PROCINFO_INITFUNC ) @ initialise processor
310 @ (return control reg)
311 THUMB( add r12, r10, #PROCINFO_INITFUNC )
313 ENDPROC(secondary_startup)
316 * r6 = &secondary_data
318 ENTRY(__secondary_switched)
319 ldr sp, [r7, #4] @ get secondary_data.stack
321 b secondary_start_kernel
322 ENDPROC(__secondary_switched)
326 .type __secondary_data, %object
330 .long __secondary_switched
331 #endif /* defined(CONFIG_SMP) */
336 * Setup common bits before finally enabling the MMU. Essentially
337 * this is just loading the page table pointer and domain access
340 * r0 = cp#15 control register
343 * r4 = page table pointer
345 * r13 = *virtual* address to jump to upon completion
348 #ifdef CONFIG_ALIGNMENT_TRAP
353 #ifdef CONFIG_CPU_DCACHE_DISABLE
356 #ifdef CONFIG_CPU_BPREDICT_DISABLE
359 #ifdef CONFIG_CPU_ICACHE_DISABLE
362 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
363 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
364 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
365 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
366 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
367 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
369 ENDPROC(__enable_mmu)
372 * Enable the MMU. This completely changes the structure of the visible
373 * memory space. You will not be able to trace execution through this.
374 * If you have an enquiry about this, *please* check the linux-arm-kernel
375 * mailing list archives BEFORE sending another post to the list.
377 * r0 = cp#15 control register
381 * r13 = *virtual* address to jump to upon completion
383 * other registers depend on the function called upon completion
388 mcr p15, 0, r0, c1, c0, 0 @ write control reg
389 mrc p15, 0, r3, c0, c0, 0 @ read id reg
394 ENDPROC(__turn_mmu_on)
397 #ifdef CONFIG_SMP_ON_UP
399 and r3, r9, #0x000f0000 @ architecture version
400 teq r3, #0x000f0000 @ CPU ID supported?
401 bne __fixup_smp_on_up @ no, assume UP
403 bic r3, r9, #0x00ff0000
404 bic r3, r3, #0x0000000f @ mask 0xff00fff0
406 orr r4, r4, #0x0000b000
407 orr r4, r4, #0x00000020 @ val 0x4100b020
408 teq r3, r4 @ ARM 11MPCore?
409 moveq pc, lr @ yes, assume SMP
411 mrc p15, 0, r0, c0, c0, 5 @ read MPIDR
412 and r0, r0, #0xc0000000 @ multiprocessing extensions and
413 teq r0, #0x80000000 @ not part of a uniprocessor system?
414 moveq pc, lr @ yes, assume SMP
425 ARM( str r6, [r0, r3] )
426 THUMB( add r0, r0, r3 )
428 THUMB( mov r6, r6, ror #16 ) @ Convert word order for big-endian.
430 THUMB( strh r6, [r0], #2 ) @ For Thumb-2, store as two halfwords
431 THUMB( mov r6, r6, lsr #16 ) @ to be robust against misaligned r3.
432 THUMB( strh r6, [r0] )
450 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT
452 /* __fixup_pv_table - patch the stub instructions with the delta between
453 * PHYS_OFFSET and PAGE_OFFSET, which is assumed to be 16MiB aligned and
454 * can be expressed by an immediate shifter operand. The stub instruction
455 * has a form of '(add|sub) rd, rn, #imm'.
460 ldmia r0, {r3-r5, r7}
461 sub r3, r0, r3 @ PHYS_OFFSET - PAGE_OFFSET
462 add r4, r4, r3 @ adjust table start address
463 add r5, r5, r3 @ adjust table end address
464 add r7, r7, r3 @ adjust __pv_phys_offset address
465 str r8, [r7] @ save computed PHYS_OFFSET to __pv_phys_offset
466 #ifndef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
467 mov r6, r3, lsr #24 @ constant for add/sub instructions
468 teq r3, r6, lsl #24 @ must be 16MiB aligned
470 mov r6, r3, lsr #16 @ constant for add/sub instructions
471 teq r3, r6, lsl #16 @ must be 64kiB aligned
473 THUMB( it ne @ cross section branch )
475 str r6, [r7, #4] @ save to __pv_offset
477 ENDPROC(__fixup_pv_table)
481 .long __pv_table_begin
483 2: .long __pv_phys_offset
487 #ifdef CONFIG_THUMB2_KERNEL
488 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
498 orr r0, r0, r7, lsl #12
508 orr r6, r6, r7, lsl #12
511 2: @ at this point the C flag is always clear
513 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
515 tst ip, 0x0400 @ the i bit tells us LS or MS byte
517 cmp r0, #0 @ set C flag, and ...
518 biceq ip, 0x0400 @ immediate zero value has a special encoding
519 streqh ip, [r7] @ that requires the i bit cleared
523 orrcc ip, r6 @ mask in offset bits 31-24
524 orrcs ip, r0 @ mask in offset bits 23-16
527 ldrcc r7, [r4], #4 @ use branch for delay slot
531 #ifdef CONFIG_ARM_PATCH_PHYS_VIRT_16BIT
532 and r0, r6, #255 @ offset bits 23-16
533 mov r6, r6, lsr #8 @ offset bits 31-24
535 mov r0, #0 @ just in case...
539 bic ip, ip, #0x000000ff
540 tst ip, #0x400 @ rotate shift tells us LS or MS byte
541 orrne ip, ip, r6 @ mask in offset bits 31-24
542 orreq ip, ip, r0 @ mask in offset bits 23-16
545 ldrcc r7, [r4], #4 @ use branch for delay slot
549 ENDPROC(__fixup_a_pv_table)
551 ENTRY(fixup_pv_table)
552 stmfd sp!, {r4 - r7, lr}
553 ldr r2, 2f @ get address of __pv_phys_offset
554 mov r3, #0 @ no offset
555 mov r4, r0 @ r0 = table start
556 add r5, r0, r1 @ r1 = table size
557 ldr r6, [r2, #4] @ get __pv_offset
558 bl __fixup_a_pv_table
559 ldmfd sp!, {r4 - r7, pc}
560 ENDPROC(fixup_pv_table)
563 2: .long __pv_phys_offset
566 .globl __pv_phys_offset
567 .type __pv_phys_offset, %object
570 .size __pv_phys_offset, . - __pv_phys_offset
575 #include "head-common.S"