2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
15 * Copyright (C) 2012 ARM Limited
17 * Author: Will Deacon <will.deacon@arm.com>
19 #define pr_fmt(fmt) "CPU PMU: " fmt
21 #include <linux/bitmap.h>
22 #include <linux/export.h>
23 #include <linux/kernel.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
28 #include <asm/cputype.h>
29 #include <asm/irq_regs.h>
32 /* Set at runtime when we know what CPU type we are. */
33 static struct arm_pmu *cpu_pmu;
35 static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
36 static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
37 static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
40 * Despite the names, these two functions are CPU-specific and are used
41 * by the OProfile/perf code.
43 const char *perf_pmu_name(void)
48 return cpu_pmu->pmu.name;
50 EXPORT_SYMBOL_GPL(perf_pmu_name);
52 int perf_num_counters(void)
57 max_events = cpu_pmu->num_events;
61 EXPORT_SYMBOL_GPL(perf_num_counters);
63 /* Include the PMU-specific implementations. */
64 #include "perf_event_xscale.c"
65 #include "perf_event_v6.c"
66 #include "perf_event_v7.c"
68 static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
70 return &__get_cpu_var(cpu_hw_events);
73 static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
76 for_each_possible_cpu(cpu) {
77 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
78 events->events = per_cpu(hw_events, cpu);
79 events->used_mask = per_cpu(used_mask, cpu);
80 raw_spin_lock_init(&events->pmu_lock);
82 cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
84 /* Ensure the PMU has sane values out of reset. */
85 if (cpu_pmu && cpu_pmu->reset)
86 on_each_cpu(cpu_pmu->reset, NULL, 1);
90 * PMU hardware loses all context when a CPU goes offline.
91 * When a CPU is hotplugged back in, since some hardware registers are
92 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
93 * junk values out of them.
95 static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
96 unsigned long action, void *hcpu)
98 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
101 if (cpu_pmu && cpu_pmu->reset)
102 cpu_pmu->reset(NULL);
107 static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
108 .notifier_call = cpu_pmu_notify,
112 * PMU platform driver and devicetree bindings.
114 static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
115 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
116 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
117 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
118 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
119 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
120 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
121 {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
122 {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
126 static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
132 * CPU PMU identification and probing.
134 static struct arm_pmu *__devinit probe_current_pmu(void)
136 struct arm_pmu *pmu = NULL;
138 unsigned long cpuid = read_cpuid_id();
139 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
140 unsigned long part_number = (cpuid & 0xFFF0);
142 pr_info("probing PMU on CPU %d\n", cpu);
145 if (0x41 == implementor) {
146 switch (part_number) {
147 case 0xB360: /* ARM1136 */
148 case 0xB560: /* ARM1156 */
149 case 0xB760: /* ARM1176 */
150 pmu = armv6pmu_init();
152 case 0xB020: /* ARM11mpcore */
153 pmu = armv6mpcore_pmu_init();
155 case 0xC080: /* Cortex-A8 */
156 pmu = armv7_a8_pmu_init();
158 case 0xC090: /* Cortex-A9 */
159 pmu = armv7_a9_pmu_init();
161 case 0xC050: /* Cortex-A5 */
162 pmu = armv7_a5_pmu_init();
164 case 0xC0F0: /* Cortex-A15 */
165 pmu = armv7_a15_pmu_init();
167 case 0xC070: /* Cortex-A7 */
168 pmu = armv7_a7_pmu_init();
171 /* Intel CPUs [xscale]. */
172 } else if (0x69 == implementor) {
173 part_number = (cpuid >> 13) & 0x7;
174 switch (part_number) {
176 pmu = xscale1pmu_init();
179 pmu = xscale2pmu_init();
188 static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
190 const struct of_device_id *of_id;
191 struct arm_pmu *(*init_fn)(void);
192 struct device_node *node = pdev->dev.of_node;
195 pr_info("attempt to register multiple PMU devices!");
199 if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
200 init_fn = of_id->data;
203 cpu_pmu = probe_current_pmu();
209 cpu_pmu->plat_device = pdev;
210 cpu_pmu_init(cpu_pmu);
211 register_cpu_notifier(&cpu_pmu_hotplug_notifier);
212 armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
217 static struct platform_driver cpu_pmu_driver = {
220 .pm = &armpmu_dev_pm_ops,
221 .of_match_table = cpu_pmu_of_device_ids,
223 .probe = cpu_pmu_device_probe,
224 .id_table = cpu_pmu_plat_device_ids,
227 static int __init register_pmu_driver(void)
229 return platform_driver_register(&cpu_pmu_driver);
231 device_initcall(register_pmu_driver);