arch/arm/mach-davinci/cpuidle.c

   1 /*
   2  * CPU idle for DaVinci SoCs
   3  *
   4  * Copyright (C) 2009 Texas Instruments Incorporated. http://www.ti.com/
   5  *
   6  * Derived from Marvell Kirkwood CPU idle code
   7  * (arch/arm/mach-kirkwood/cpuidle.c)
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/cpuidle.h>
  18 #include <linux/io.h>
  19 #include <asm/proc-fns.h>
  20
  21 #include <mach/cpuidle.h>
  22 #include <mach/memory.h>
  23
  24 #define DAVINCI_CPUIDLE_MAX_STATES      2
  25
  26 struct davinci_ops {
  27         void (*enter) (u32 flags);
  28         void (*exit) (u32 flags);
  29         u32 flags;
  30 };
  31
  32 /* fields in davinci_ops.flags */
  33 #define DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN BIT(0)
  34
  35 static struct cpuidle_driver davinci_idle_driver = {
  36         .name   = "cpuidle-davinci",
  37         .owner  = THIS_MODULE,
  38 };
  39
  40 static DEFINE_PER_CPU(struct cpuidle_device, davinci_cpuidle_device);
  41 static void __iomem *ddr2_reg_base;
  42
  43 static void davinci_save_ddr_power(int enter, bool pdown)
  44 {
  45         u32 val;
  46
  47         val = __raw_readl(ddr2_reg_base + DDR2_SDRCR_OFFSET);
  48
  49         if (enter) {
  50                 if (pdown)
  51                         val |= DDR2_SRPD_BIT;
  52                 else
  53                         val &= ~DDR2_SRPD_BIT;
  54                 val |= DDR2_LPMODEN_BIT;
  55         } else {
  56                 val &= ~(DDR2_SRPD_BIT | DDR2_LPMODEN_BIT);
  57         }
  58
  59         __raw_writel(val, ddr2_reg_base + DDR2_SDRCR_OFFSET);
  60 }
  61
  62 static void davinci_c2state_enter(u32 flags)
  63 {
  64         davinci_save_ddr_power(1, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  65 }
  66
  67 static void davinci_c2state_exit(u32 flags)
  68 {
  69         davinci_save_ddr_power(0, !!(flags & DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN));
  70 }
  71
  72 static struct davinci_ops davinci_states[DAVINCI_CPUIDLE_MAX_STATES] = {
  73         [1] = {
  74                 .enter  = davinci_c2state_enter,
  75                 .exit   = davinci_c2state_exit,
  76         },
  77 };
  78
  79 /* Actual code that puts the SoC in different idle states */
  80 static int davinci_enter_idle(struct cpuidle_device *dev,
  81                                                 int index)
  82 {
  83         struct davinci_ops *ops = cpuidle_get_statedata(&dev->states[index]);
  84         struct timeval before, after;
  85         int idle_time;
  86
  87         local_irq_disable();
  88         do_gettimeofday(&before);
  89
  90         if (ops && ops->enter)
  91                 ops->enter(ops->flags);
  92         /* Wait for interrupt state */
  93         cpu_do_idle();
  94         if (ops && ops->exit)
  95                 ops->exit(ops->flags);
  96
  97         do_gettimeofday(&after);
  98         local_irq_enable();
  99         idle_time = (after.tv_sec - before.tv_sec) * USEC_PER_SEC +
 100                         (after.tv_usec - before.tv_usec);
 101
 102         dev->last_residency = idle_time;
 103
 104         return index;
 105 }
 106
 107 static int __init davinci_cpuidle_probe(struct platform_device *pdev)
 108 {
 109         int ret;
 110         struct cpuidle_device *device;
 111         struct davinci_cpuidle_config *pdata = pdev->dev.platform_data;
 112
 113         device = &per_cpu(davinci_cpuidle_device, smp_processor_id());
 114
 115         if (!pdata) {
 116                 dev_err(&pdev->dev, "cannot get platform data\n");
 117                 return -ENOENT;
 118         }
 119
 120         ddr2_reg_base = pdata->ddr2_ctlr_base;
 121
 122         ret = cpuidle_register_driver(&davinci_idle_driver);
 123         if (ret) {
 124                 dev_err(&pdev->dev, "failed to register driver\n");
 125                 return ret;
 126         }
 127
 128         /* Wait for interrupt state */
 129         device->states[0].enter = davinci_enter_idle;
 130         device->states[0].exit_latency = 1;
 131         device->states[0].target_residency = 10000;
 132         device->states[0].flags = CPUIDLE_FLAG_TIME_VALID;
 133         strcpy(device->states[0].name, "WFI");
 134         strcpy(device->states[0].desc, "Wait for interrupt");
 135
 136         /* Wait for interrupt and DDR self refresh state */
 137         device->states[1].enter = davinci_enter_idle;
 138         device->states[1].exit_latency = 10;
 139         device->states[1].target_residency = 10000;
 140         device->states[1].flags = CPUIDLE_FLAG_TIME_VALID;
 141         strcpy(device->states[1].name, "DDR SR");
 142         strcpy(device->states[1].desc, "WFI and DDR Self Refresh");
 143         if (pdata->ddr2_pdown)
 144                 davinci_states[1].flags |= DAVINCI_CPUIDLE_FLAGS_DDR2_PWDN;
 145         cpuidle_set_statedata(&device->states[1], &davinci_states[1]);
 146
 147         device->state_count = DAVINCI_CPUIDLE_MAX_STATES;
 148
 149         ret = cpuidle_register_device(device);
 150         if (ret) {
 151                 dev_err(&pdev->dev, "failed to register device\n");
 152                 cpuidle_unregister_driver(&davinci_idle_driver);
 153                 return ret;
 154         }
 155
 156         return 0;
 157 }
 158
 159 static struct platform_driver davinci_cpuidle_driver = {
 160         .driver = {
 161                 .name   = "cpuidle-davinci",
 162                 .owner  = THIS_MODULE,
 163         },
 164 };
 165
 166 static int __init davinci_cpuidle_init(void)
 167 {
 168         return platform_driver_probe(&davinci_cpuidle_driver,
 169                                                 davinci_cpuidle_probe);
 170 }
 171 device_initcall(davinci_cpuidle_init);
 172