2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
7 * Copyright (C) 2002 ARM Ltd.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
22 #include <linux/of_address.h>
24 #include <asm/cacheflush.h>
26 #include <asm/smp_plat.h>
27 #include <asm/smp_scu.h>
28 #include <asm/firmware.h>
35 extern void exynos4_secondary_startup(void);
38 * Set or clear the USE_DELAYED_RESET_ASSERTION option, set on Exynos4 SoCs
39 * during hot-(un)plugging CPUx.
41 * The feature can be cleared safely during first boot of secondary CPU.
43 * Exynos4 SoCs require setting USE_DELAYED_RESET_ASSERTION during powering
44 * down a CPU so the CPU idle clock down feature could properly detect global
45 * idle state when CPUx is off.
47 static void exynos_set_delayed_reset_assertion(u32 core_id, bool enable)
49 if (soc_is_exynos4()) {
52 tmp = pmu_raw_readl(EXYNOS_ARM_CORE_OPTION(core_id));
54 tmp |= S5P_USE_DELAYED_RESET_ASSERTION;
56 tmp &= ~(S5P_USE_DELAYED_RESET_ASSERTION);
57 pmu_raw_writel(tmp, EXYNOS_ARM_CORE_OPTION(core_id));
61 #ifdef CONFIG_HOTPLUG_CPU
62 static inline void cpu_leave_lowpower(u32 core_id)
67 "mrc p15, 0, %0, c1, c0, 0\n"
69 " mcr p15, 0, %0, c1, c0, 0\n"
70 " mrc p15, 0, %0, c1, c0, 1\n"
72 " mcr p15, 0, %0, c1, c0, 1\n"
74 : "Ir" (CR_C), "Ir" (0x40)
77 exynos_set_delayed_reset_assertion(core_id, false);
80 static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
82 u32 mpidr = cpu_logical_map(cpu);
83 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
87 /* Turn the CPU off on next WFI instruction. */
88 exynos_cpu_power_down(core_id);
91 * Exynos4 SoCs require setting
92 * USE_DELAYED_RESET_ASSERTION so the CPU idle
93 * clock down feature could properly detect
94 * global idle state when CPUx is off.
96 exynos_set_delayed_reset_assertion(core_id, true);
100 if (pen_release == core_id) {
102 * OK, proper wakeup, we're done
108 * Getting here, means that we have come out of WFI without
109 * having been woken up - this shouldn't happen
111 * Just note it happening - when we're woken, we can report
117 #endif /* CONFIG_HOTPLUG_CPU */
120 * exynos_core_power_down : power down the specified cpu
121 * @cpu : the cpu to power down
123 * Power down the specified cpu. The sequence must be finished by a
124 * call to cpu_do_idle()
127 void exynos_cpu_power_down(int cpu)
131 if (cpu == 0 && (of_machine_is_compatible("samsung,exynos5420") ||
132 of_machine_is_compatible("samsung,exynos5800"))) {
134 * Bypass power down for CPU0 during suspend. Check for
135 * the SYS_PWR_REG value to decide if we are suspending
138 int val = pmu_raw_readl(EXYNOS5_ARM_CORE0_SYS_PWR_REG);
140 if (!(val & S5P_CORE_LOCAL_PWR_EN))
144 core_conf = pmu_raw_readl(EXYNOS_ARM_CORE_CONFIGURATION(cpu));
145 core_conf &= ~S5P_CORE_LOCAL_PWR_EN;
146 pmu_raw_writel(core_conf, EXYNOS_ARM_CORE_CONFIGURATION(cpu));
150 * exynos_cpu_power_up : power up the specified cpu
151 * @cpu : the cpu to power up
153 * Power up the specified cpu
155 void exynos_cpu_power_up(int cpu)
157 u32 core_conf = S5P_CORE_LOCAL_PWR_EN;
159 if (soc_is_exynos3250())
160 core_conf |= S5P_CORE_AUTOWAKEUP_EN;
162 pmu_raw_writel(core_conf,
163 EXYNOS_ARM_CORE_CONFIGURATION(cpu));
167 * exynos_cpu_power_state : returns the power state of the cpu
168 * @cpu : the cpu to retrieve the power state from
171 int exynos_cpu_power_state(int cpu)
173 return (pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) &
174 S5P_CORE_LOCAL_PWR_EN);
178 * exynos_cluster_power_down : power down the specified cluster
179 * @cluster : the cluster to power down
181 void exynos_cluster_power_down(int cluster)
183 pmu_raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster));
187 * exynos_cluster_power_up : power up the specified cluster
188 * @cluster : the cluster to power up
190 void exynos_cluster_power_up(int cluster)
192 pmu_raw_writel(S5P_CORE_LOCAL_PWR_EN,
193 EXYNOS_COMMON_CONFIGURATION(cluster));
197 * exynos_cluster_power_state : returns the power state of the cluster
198 * @cluster : the cluster to retrieve the power state from
201 int exynos_cluster_power_state(int cluster)
203 return (pmu_raw_readl(EXYNOS_COMMON_STATUS(cluster)) &
204 S5P_CORE_LOCAL_PWR_EN);
207 void __iomem *cpu_boot_reg_base(void)
209 if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1)
210 return pmu_base_addr + S5P_INFORM5;
211 return sysram_base_addr;
214 static inline void __iomem *cpu_boot_reg(int cpu)
216 void __iomem *boot_reg;
218 boot_reg = cpu_boot_reg_base();
220 return ERR_PTR(-ENODEV);
221 if (soc_is_exynos4412())
223 else if (soc_is_exynos5420() || soc_is_exynos5800())
229 * Set wake up by local power mode and execute software reset for given core.
231 * Currently this is needed only when booting secondary CPU on Exynos3250.
233 static void exynos_core_restart(u32 core_id)
237 if (!of_machine_is_compatible("samsung,exynos3250"))
240 while (!pmu_raw_readl(S5P_PMU_SPARE2))
244 val = pmu_raw_readl(EXYNOS_ARM_CORE_STATUS(core_id));
245 val |= S5P_CORE_WAKEUP_FROM_LOCAL_CFG;
246 pmu_raw_writel(val, EXYNOS_ARM_CORE_STATUS(core_id));
248 pr_info("CPU%u: Software reset\n", core_id);
249 pmu_raw_writel(EXYNOS_CORE_PO_RESET(core_id), EXYNOS_SWRESET);
253 * Write pen_release in a way that is guaranteed to be visible to all
254 * observers, irrespective of whether they're taking part in coherency
255 * or not. This is necessary for the hotplug code to work reliably.
257 static void write_pen_release(int val)
261 sync_cache_w(&pen_release);
264 static void __iomem *scu_base_addr(void)
266 return (void __iomem *)(S5P_VA_SCU);
269 static DEFINE_SPINLOCK(boot_lock);
271 static void exynos_secondary_init(unsigned int cpu)
274 * let the primary processor know we're out of the
275 * pen, then head off into the C entry point
277 write_pen_release(-1);
280 * Synchronise with the boot thread.
282 spin_lock(&boot_lock);
283 spin_unlock(&boot_lock);
286 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle)
288 unsigned long timeout;
289 u32 mpidr = cpu_logical_map(cpu);
290 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
294 * Set synchronisation state between this boot processor
295 * and the secondary one
297 spin_lock(&boot_lock);
300 * The secondary processor is waiting to be released from
301 * the holding pen - release it, then wait for it to flag
302 * that it has been released by resetting pen_release.
304 * Note that "pen_release" is the hardware CPU core ID, whereas
305 * "cpu" is Linux's internal ID.
307 write_pen_release(core_id);
309 if (!exynos_cpu_power_state(core_id)) {
310 exynos_cpu_power_up(core_id);
313 /* wait max 10 ms until cpu1 is on */
314 while (exynos_cpu_power_state(core_id)
315 != S5P_CORE_LOCAL_PWR_EN) {
323 printk(KERN_ERR "cpu1 power enable failed");
324 spin_unlock(&boot_lock);
329 exynos_core_restart(core_id);
332 * Send the secondary CPU a soft interrupt, thereby causing
333 * the boot monitor to read the system wide flags register,
334 * and branch to the address found there.
337 timeout = jiffies + (1 * HZ);
338 while (time_before(jiffies, timeout)) {
339 unsigned long boot_addr;
343 boot_addr = virt_to_phys(exynos4_secondary_startup);
346 * Try to set boot address using firmware first
347 * and fall back to boot register if it fails.
349 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
350 if (ret && ret != -ENOSYS)
352 if (ret == -ENOSYS) {
353 void __iomem *boot_reg = cpu_boot_reg(core_id);
355 if (IS_ERR(boot_reg)) {
356 ret = PTR_ERR(boot_reg);
359 __raw_writel(boot_addr, boot_reg);
362 call_firmware_op(cpu_boot, core_id);
364 if (soc_is_exynos3250())
367 arch_send_wakeup_ipi_mask(cpumask_of(cpu));
369 if (pen_release == -1)
375 /* No harm if this is called during first boot of secondary CPU */
376 exynos_set_delayed_reset_assertion(core_id, false);
379 * now the secondary core is starting up let it run its
380 * calibrations, then wait for it to finish
383 spin_unlock(&boot_lock);
385 return pen_release != -1 ? ret : 0;
389 * Initialise the CPU possible map early - this describes the CPUs
390 * which may be present or become present in the system.
393 static void __init exynos_smp_init_cpus(void)
395 void __iomem *scu_base = scu_base_addr();
396 unsigned int i, ncores;
398 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
399 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
402 * CPU Nodes are passed thru DT and set_cpu_possible
403 * is set by "arm_dt_init_cpu_maps".
408 if (ncores > nr_cpu_ids) {
409 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
414 for (i = 0; i < ncores; i++)
415 set_cpu_possible(i, true);
418 static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
422 exynos_sysram_init();
424 if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
425 scu_enable(scu_base_addr());
428 * Write the address of secondary startup into the
429 * system-wide flags register. The boot monitor waits
430 * until it receives a soft interrupt, and then the
431 * secondary CPU branches to this address.
433 * Try using firmware operation first and fall back to
434 * boot register if it fails.
436 for (i = 1; i < max_cpus; ++i) {
437 unsigned long boot_addr;
442 mpidr = cpu_logical_map(i);
443 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
444 boot_addr = virt_to_phys(exynos4_secondary_startup);
446 ret = call_firmware_op(set_cpu_boot_addr, core_id, boot_addr);
447 if (ret && ret != -ENOSYS)
449 if (ret == -ENOSYS) {
450 void __iomem *boot_reg = cpu_boot_reg(core_id);
452 if (IS_ERR(boot_reg))
454 __raw_writel(boot_addr, boot_reg);
459 #ifdef CONFIG_HOTPLUG_CPU
461 * platform-specific code to shutdown a CPU
463 * Called with IRQs disabled
465 static void exynos_cpu_die(unsigned int cpu)
468 u32 mpidr = cpu_logical_map(cpu);
469 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
471 v7_exit_coherency_flush(louis);
473 platform_do_lowpower(cpu, &spurious);
476 * bring this CPU back into the world of cache
477 * coherency, and then restore interrupts
479 cpu_leave_lowpower(core_id);
482 pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
484 #endif /* CONFIG_HOTPLUG_CPU */
486 struct smp_operations exynos_smp_ops __initdata = {
487 .smp_init_cpus = exynos_smp_init_cpus,
488 .smp_prepare_cpus = exynos_smp_prepare_cpus,
489 .smp_secondary_init = exynos_secondary_init,
490 .smp_boot_secondary = exynos_boot_secondary,
491 #ifdef CONFIG_HOTPLUG_CPU
492 .cpu_die = exynos_cpu_die,