arch/arm/mach-kirkwood/common.c

   1 /*
   2  * arch/arm/mach-kirkwood/common.c
   3  *
   4  * Core functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/spinlock.h>
  20 #include <net/dsa.h>
  21 #include <asm/page.h>
  22 #include <asm/timex.h>
  23 #include <asm/kexec.h>
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/time.h>
  26 #include <mach/kirkwood.h>
  27 #include <mach/bridge-regs.h>
  28 #include <plat/audio.h>
  29 #include <plat/cache-feroceon-l2.h>
  30 #include <plat/mvsdio.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/ehci-orion.h>
  33 #include <plat/common.h>
  34 #include <plat/time.h>
  35 #include <plat/addr-map.h>
  36 #include <plat/mv_xor.h>
  37 #include "common.h"
  38
  39 /*****************************************************************************
  40  * I/O Address Mapping
  41  ****************************************************************************/
  42 static struct map_desc kirkwood_io_desc[] __initdata = {
  43         {
  44                 .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
  45                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
  46                 .length         = KIRKWOOD_PCIE_IO_SIZE,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
  50                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
  51                 .length         = KIRKWOOD_PCIE1_IO_SIZE,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
  55                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
  56                 .length         = KIRKWOOD_REGS_SIZE,
  57                 .type           = MT_DEVICE,
  58         },
  59 };
  60
  61 void __init kirkwood_map_io(void)
  62 {
  63         iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
  64 }
  65
  66 /*
  67  * Default clock control bits.  Any bit _not_ set in this variable
  68  * will be cleared from the hardware after platform devices have been
  69  * registered.  Some reserved bits must be set to 1.
  70  */
  71 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
  72
  73
  74 /*****************************************************************************
  75  * CLK tree
  76  ****************************************************************************/
  77 static DEFINE_SPINLOCK(gating_lock);
  78 static struct clk *tclk;
  79
  80 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
  81 {
  82         return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
  83                                  (void __iomem *)CLOCK_GATING_CTRL,
  84                                  bit_idx, 0, &gating_lock);
  85 }
  86
  87 void __init kirkwood_clk_init(void)
  88 {
  89         struct clk *runit, *ge0, *ge1;
  90
  91         tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
  92                                        CLK_IS_ROOT, kirkwood_tclk);
  93
  94         runit = kirkwood_register_gate("runit",  CGC_BIT_RUNIT);
  95         ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
  96         ge1 = kirkwood_register_gate("ge1",    CGC_BIT_GE1);
  97         kirkwood_register_gate("sata0",  CGC_BIT_SATA0);
  98         kirkwood_register_gate("sata1",  CGC_BIT_SATA1);
  99         kirkwood_register_gate("usb0",   CGC_BIT_USB0);
 100         kirkwood_register_gate("sdio",   CGC_BIT_SDIO);
 101         kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
 102         kirkwood_register_gate("xor0",   CGC_BIT_XOR0);
 103         kirkwood_register_gate("xor1",   CGC_BIT_XOR1);
 104         kirkwood_register_gate("pex0",   CGC_BIT_PEX0);
 105         kirkwood_register_gate("pex1",   CGC_BIT_PEX1);
 106         kirkwood_register_gate("audio",  CGC_BIT_AUDIO);
 107         kirkwood_register_gate("tdm",    CGC_BIT_TDM);
 108         kirkwood_register_gate("tsu",    CGC_BIT_TSU);
 109
 110         /* clkdev entries, mapping clks to devices */
 111         orion_clkdev_add(NULL, "orion_spi.0", runit);
 112         orion_clkdev_add(NULL, "orion_spi.1", runit);
 113         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
 114         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
 115 }
 116
 117 /*****************************************************************************
 118  * EHCI0
 119  ****************************************************************************/
 120 void __init kirkwood_ehci_init(void)
 121 {
 122         kirkwood_clk_ctrl |= CGC_USB0;
 123         orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
 124 }
 125
 126
 127 /*****************************************************************************
 128  * GE00
 129  ****************************************************************************/
 130 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 131 {
 132         kirkwood_clk_ctrl |= CGC_GE0;
 133
 134         orion_ge00_init(eth_data,
 135                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
 136                         IRQ_KIRKWOOD_GE00_ERR);
 137 }
 138
 139
 140 /*****************************************************************************
 141  * GE01
 142  ****************************************************************************/
 143 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 144 {
 145
 146         kirkwood_clk_ctrl |= CGC_GE1;
 147
 148         orion_ge01_init(eth_data,
 149                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
 150                         IRQ_KIRKWOOD_GE01_ERR);
 151 }
 152
 153
 154 /*****************************************************************************
 155  * Ethernet switch
 156  ****************************************************************************/
 157 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 158 {
 159         orion_ge00_switch_init(d, irq);
 160 }
 161
 162
 163 /*****************************************************************************
 164  * NAND flash
 165  ****************************************************************************/
 166 static struct resource kirkwood_nand_resource = {
 167         .flags          = IORESOURCE_MEM,
 168         .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
 169         .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
 170                                 KIRKWOOD_NAND_MEM_SIZE - 1,
 171 };
 172
 173 static struct orion_nand_data kirkwood_nand_data = {
 174         .cle            = 0,
 175         .ale            = 1,
 176         .width          = 8,
 177 };
 178
 179 static struct platform_device kirkwood_nand_flash = {
 180         .name           = "orion_nand",
 181         .id             = -1,
 182         .dev            = {
 183                 .platform_data  = &kirkwood_nand_data,
 184         },
 185         .resource       = &kirkwood_nand_resource,
 186         .num_resources  = 1,
 187 };
 188
 189 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
 190                                int chip_delay)
 191 {
 192         kirkwood_clk_ctrl |= CGC_RUNIT;
 193         kirkwood_nand_data.parts = parts;
 194         kirkwood_nand_data.nr_parts = nr_parts;
 195         kirkwood_nand_data.chip_delay = chip_delay;
 196         platform_device_register(&kirkwood_nand_flash);
 197 }
 198
 199 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 200                                    int (*dev_ready)(struct mtd_info *))
 201 {
 202         kirkwood_clk_ctrl |= CGC_RUNIT;
 203         kirkwood_nand_data.parts = parts;
 204         kirkwood_nand_data.nr_parts = nr_parts;
 205         kirkwood_nand_data.dev_ready = dev_ready;
 206         platform_device_register(&kirkwood_nand_flash);
 207 }
 208
 209 /*****************************************************************************
 210  * SoC RTC
 211  ****************************************************************************/
 212 static void __init kirkwood_rtc_init(void)
 213 {
 214         orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 215 }
 216
 217
 218 /*****************************************************************************
 219  * SATA
 220  ****************************************************************************/
 221 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 222 {
 223         kirkwood_clk_ctrl |= CGC_SATA0;
 224         if (sata_data->n_ports > 1)
 225                 kirkwood_clk_ctrl |= CGC_SATA1;
 226
 227         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 228 }
 229
 230
 231 /*****************************************************************************
 232  * SD/SDIO/MMC
 233  ****************************************************************************/
 234 static struct resource mvsdio_resources[] = {
 235         [0] = {
 236                 .start  = SDIO_PHYS_BASE,
 237                 .end    = SDIO_PHYS_BASE + SZ_1K - 1,
 238                 .flags  = IORESOURCE_MEM,
 239         },
 240         [1] = {
 241                 .start  = IRQ_KIRKWOOD_SDIO,
 242                 .end    = IRQ_KIRKWOOD_SDIO,
 243                 .flags  = IORESOURCE_IRQ,
 244         },
 245 };
 246
 247 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 248
 249 static struct platform_device kirkwood_sdio = {
 250         .name           = "mvsdio",
 251         .id             = -1,
 252         .dev            = {
 253                 .dma_mask = &mvsdio_dmamask,
 254                 .coherent_dma_mask = DMA_BIT_MASK(32),
 255         },
 256         .num_resources  = ARRAY_SIZE(mvsdio_resources),
 257         .resource       = mvsdio_resources,
 258 };
 259
 260 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 261 {
 262         u32 dev, rev;
 263
 264         kirkwood_pcie_id(&dev, &rev);
 265         if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
 266                 mvsdio_data->clock = 100000000;
 267         else
 268                 mvsdio_data->clock = 200000000;
 269         kirkwood_clk_ctrl |= CGC_SDIO;
 270         kirkwood_sdio.dev.platform_data = mvsdio_data;
 271         platform_device_register(&kirkwood_sdio);
 272 }
 273
 274
 275 /*****************************************************************************
 276  * SPI
 277  ****************************************************************************/
 278 void __init kirkwood_spi_init()
 279 {
 280         kirkwood_clk_ctrl |= CGC_RUNIT;
 281         orion_spi_init(SPI_PHYS_BASE);
 282 }
 283
 284
 285 /*****************************************************************************
 286  * I2C
 287  ****************************************************************************/
 288 void __init kirkwood_i2c_init(void)
 289 {
 290         orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 291 }
 292
 293
 294 /*****************************************************************************
 295  * UART0
 296  ****************************************************************************/
 297
 298 void __init kirkwood_uart0_init(void)
 299 {
 300         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 301                          IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 302 }
 303
 304
 305 /*****************************************************************************
 306  * UART1
 307  ****************************************************************************/
 308 void __init kirkwood_uart1_init(void)
 309 {
 310         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 311                          IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 312 }
 313
 314 /*****************************************************************************
 315  * Cryptographic Engines and Security Accelerator (CESA)
 316  ****************************************************************************/
 317 void __init kirkwood_crypto_init(void)
 318 {
 319         kirkwood_clk_ctrl |= CGC_CRYPTO;
 320         orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
 321                           KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
 322 }
 323
 324
 325 /*****************************************************************************
 326  * XOR0
 327  ****************************************************************************/
 328 void __init kirkwood_xor0_init(void)
 329 {
 330         kirkwood_clk_ctrl |= CGC_XOR0;
 331
 332         orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
 333                         IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 334 }
 335
 336
 337 /*****************************************************************************
 338  * XOR1
 339  ****************************************************************************/
 340 void __init kirkwood_xor1_init(void)
 341 {
 342         kirkwood_clk_ctrl |= CGC_XOR1;
 343
 344         orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
 345                         IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
 346 }
 347
 348
 349 /*****************************************************************************
 350  * Watchdog
 351  ****************************************************************************/
 352 void __init kirkwood_wdt_init(void)
 353 {
 354         orion_wdt_init(kirkwood_tclk);
 355 }
 356
 357
 358 /*****************************************************************************
 359  * Time handling
 360  ****************************************************************************/
 361 void __init kirkwood_init_early(void)
 362 {
 363         orion_time_set_base(TIMER_VIRT_BASE);
 364 }
 365
 366 int kirkwood_tclk;
 367
 368 static int __init kirkwood_find_tclk(void)
 369 {
 370         u32 dev, rev;
 371
 372         kirkwood_pcie_id(&dev, &rev);
 373
 374         if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
 375                 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
 376                         return 200000000;
 377
 378         return 166666667;
 379 }
 380
 381 static void __init kirkwood_timer_init(void)
 382 {
 383         kirkwood_tclk = kirkwood_find_tclk();
 384
 385         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 386                         IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 387 }
 388
 389 struct sys_timer kirkwood_timer = {
 390         .init = kirkwood_timer_init,
 391 };
 392
 393 /*****************************************************************************
 394  * Audio
 395  ****************************************************************************/
 396 static struct resource kirkwood_i2s_resources[] = {
 397         [0] = {
 398                 .start  = AUDIO_PHYS_BASE,
 399                 .end    = AUDIO_PHYS_BASE + SZ_16K - 1,
 400                 .flags  = IORESOURCE_MEM,
 401         },
 402         [1] = {
 403                 .start  = IRQ_KIRKWOOD_I2S,
 404                 .end    = IRQ_KIRKWOOD_I2S,
 405                 .flags  = IORESOURCE_IRQ,
 406         },
 407 };
 408
 409 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
 410         .burst       = 128,
 411 };
 412
 413 static struct platform_device kirkwood_i2s_device = {
 414         .name           = "kirkwood-i2s",
 415         .id             = -1,
 416         .num_resources  = ARRAY_SIZE(kirkwood_i2s_resources),
 417         .resource       = kirkwood_i2s_resources,
 418         .dev            = {
 419                 .platform_data  = &kirkwood_i2s_data,
 420         },
 421 };
 422
 423 static struct platform_device kirkwood_pcm_device = {
 424         .name           = "kirkwood-pcm-audio",
 425         .id             = -1,
 426 };
 427
 428 void __init kirkwood_audio_init(void)
 429 {
 430         kirkwood_clk_ctrl |= CGC_AUDIO;
 431         platform_device_register(&kirkwood_i2s_device);
 432         platform_device_register(&kirkwood_pcm_device);
 433 }
 434
 435 /*****************************************************************************
 436  * General
 437  ****************************************************************************/
 438 /*
 439  * Identify device ID and revision.
 440  */
 441 char * __init kirkwood_id(void)
 442 {
 443         u32 dev, rev;
 444
 445         kirkwood_pcie_id(&dev, &rev);
 446
 447         if (dev == MV88F6281_DEV_ID) {
 448                 if (rev == MV88F6281_REV_Z0)
 449                         return "MV88F6281-Z0";
 450                 else if (rev == MV88F6281_REV_A0)
 451                         return "MV88F6281-A0";
 452                 else if (rev == MV88F6281_REV_A1)
 453                         return "MV88F6281-A1";
 454                 else
 455                         return "MV88F6281-Rev-Unsupported";
 456         } else if (dev == MV88F6192_DEV_ID) {
 457                 if (rev == MV88F6192_REV_Z0)
 458                         return "MV88F6192-Z0";
 459                 else if (rev == MV88F6192_REV_A0)
 460                         return "MV88F6192-A0";
 461                 else if (rev == MV88F6192_REV_A1)
 462                         return "MV88F6192-A1";
 463                 else
 464                         return "MV88F6192-Rev-Unsupported";
 465         } else if (dev == MV88F6180_DEV_ID) {
 466                 if (rev == MV88F6180_REV_A0)
 467                         return "MV88F6180-Rev-A0";
 468                 else if (rev == MV88F6180_REV_A1)
 469                         return "MV88F6180-Rev-A1";
 470                 else
 471                         return "MV88F6180-Rev-Unsupported";
 472         } else if (dev == MV88F6282_DEV_ID) {
 473                 if (rev == MV88F6282_REV_A0)
 474                         return "MV88F6282-Rev-A0";
 475                 else if (rev == MV88F6282_REV_A1)
 476                         return "MV88F6282-Rev-A1";
 477                 else
 478                         return "MV88F6282-Rev-Unsupported";
 479         } else {
 480                 return "Device-Unknown";
 481         }
 482 }
 483
 484 void __init kirkwood_l2_init(void)
 485 {
 486 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 487         writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
 488         feroceon_l2_init(1);
 489 #else
 490         writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
 491         feroceon_l2_init(0);
 492 #endif
 493 }
 494
 495 void __init kirkwood_init(void)
 496 {
 497         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 498                 kirkwood_id(), kirkwood_tclk);
 499
 500         /*
 501          * Disable propagation of mbus errors to the CPU local bus,
 502          * as this causes mbus errors (which can occur for example
 503          * for PCI aborts) to throw CPU aborts, which we're not set
 504          * up to deal with.
 505          */
 506         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 507
 508         kirkwood_setup_cpu_mbus();
 509
 510 #ifdef CONFIG_CACHE_FEROCEON_L2
 511         kirkwood_l2_init();
 512 #endif
 513
 514         /* Setup root of clk tree */
 515         kirkwood_clk_init();
 516
 517         /* internal devices that every board has */
 518         kirkwood_rtc_init();
 519         kirkwood_wdt_init();
 520         kirkwood_xor0_init();
 521         kirkwood_xor1_init();
 522         kirkwood_crypto_init();
 523
 524 #ifdef CONFIG_KEXEC
 525         kexec_reinit = kirkwood_enable_pcie;
 526 #endif
 527 }
 528
 529 static int __init kirkwood_clock_gate(void)
 530 {
 531         unsigned int curr = readl(CLOCK_GATING_CTRL);
 532         u32 dev, rev;
 533
 534         kirkwood_pcie_id(&dev, &rev);
 535         printk(KERN_DEBUG "Gating clock of unused units\n");
 536         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 537
 538         /* Make sure those units are accessible */
 539         writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 540
 541         /* For SATA: first shutdown the phy */
 542         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 543                 /* Disable PLL and IVREF */
 544                 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
 545                 /* Disable PHY */
 546                 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
 547         }
 548         if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
 549                 /* Disable PLL and IVREF */
 550                 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
 551                 /* Disable PHY */
 552                 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 553         }
 554
 555         /* For PCIe: first shutdown the phy */
 556         if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 557                 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 558                 while (1)
 559                         if (readl(PCIE_STATUS) & 0x1)
 560                                 break;
 561                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 562         }
 563
 564         /* For PCIe 1: first shutdown the phy */
 565         if (dev == MV88F6282_DEV_ID) {
 566                 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
 567                         writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
 568                         while (1)
 569                                 if (readl(PCIE1_STATUS) & 0x1)
 570                                         break;
 571                         writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
 572                 }
 573         } else  /* keep this bit set for devices that don't have PCIe1 */
 574                 kirkwood_clk_ctrl |= CGC_PEX1;
 575
 576         /* Now gate clock the required units */
 577         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 578         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
 579
 580         return 0;
 581 }
 582 late_initcall(kirkwood_clock_gate);
 583
 584 void kirkwood_restart(char mode, const char *cmd)
 585 {
 586         /*
 587          * Enable soft reset to assert RSTOUTn.
 588          */
 589         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 590
 591         /*
 592          * Assert soft reset.
 593          */
 594         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 595
 596         while (1)
 597                 ;
 598 }