arch/arm/mach-kirkwood/common.c

   1 /*
   2  * arch/arm/mach-kirkwood/common.c
   3  *
   4  * Core functions for Marvell Kirkwood SoCs
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/ata_platform.h>
  16 #include <linux/mtd/nand.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/spinlock.h>
  20 #include <net/dsa.h>
  21 #include <asm/page.h>
  22 #include <asm/timex.h>
  23 #include <asm/kexec.h>
  24 #include <asm/mach/map.h>
  25 #include <asm/mach/time.h>
  26 #include <mach/kirkwood.h>
  27 #include <mach/bridge-regs.h>
  28 #include <plat/audio.h>
  29 #include <plat/cache-feroceon-l2.h>
  30 #include <plat/mvsdio.h>
  31 #include <plat/orion_nand.h>
  32 #include <plat/ehci-orion.h>
  33 #include <plat/common.h>
  34 #include <plat/time.h>
  35 #include <plat/addr-map.h>
  36 #include <plat/mv_xor.h>
  37 #include "common.h"
  38
  39 /*****************************************************************************
  40  * I/O Address Mapping
  41  ****************************************************************************/
  42 static struct map_desc kirkwood_io_desc[] __initdata = {
  43         {
  44                 .virtual        = KIRKWOOD_PCIE_IO_VIRT_BASE,
  45                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
  46                 .length         = KIRKWOOD_PCIE_IO_SIZE,
  47                 .type           = MT_DEVICE,
  48         }, {
  49                 .virtual        = KIRKWOOD_PCIE1_IO_VIRT_BASE,
  50                 .pfn            = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
  51                 .length         = KIRKWOOD_PCIE1_IO_SIZE,
  52                 .type           = MT_DEVICE,
  53         }, {
  54                 .virtual        = KIRKWOOD_REGS_VIRT_BASE,
  55                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
  56                 .length         = KIRKWOOD_REGS_SIZE,
  57                 .type           = MT_DEVICE,
  58         },
  59 };
  60
  61 void __init kirkwood_map_io(void)
  62 {
  63         iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
  64 }
  65
  66 /*
  67  * Default clock control bits.  Any bit _not_ set in this variable
  68  * will be cleared from the hardware after platform devices have been
  69  * registered.  Some reserved bits must be set to 1.
  70  */
  71 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
  72
  73
  74 /*****************************************************************************
  75  * CLK tree
  76  ****************************************************************************/
  77 static DEFINE_SPINLOCK(gating_lock);
  78 static struct clk *tclk;
  79
  80 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
  81 {
  82         return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
  83                                  (void __iomem *)CLOCK_GATING_CTRL,
  84                                  bit_idx, 0, &gating_lock);
  85 }
  86
  87 void __init kirkwood_clk_init(void)
  88 {
  89         struct clk *runit, *ge0, *ge1;
  90
  91         tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
  92                                        CLK_IS_ROOT, kirkwood_tclk);
  93
  94         runit = kirkwood_register_gate("runit",  CGC_BIT_RUNIT);
  95         ge0 = kirkwood_register_gate("ge0",    CGC_BIT_GE0);
  96         ge1 = kirkwood_register_gate("ge1",    CGC_BIT_GE1);
  97         kirkwood_register_gate("sata0",  CGC_BIT_SATA0);
  98         kirkwood_register_gate("sata1",  CGC_BIT_SATA1);
  99         kirkwood_register_gate("usb0",   CGC_BIT_USB0);
 100         kirkwood_register_gate("sdio",   CGC_BIT_SDIO);
 101         kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
 102         kirkwood_register_gate("xor0",   CGC_BIT_XOR0);
 103         kirkwood_register_gate("xor1",   CGC_BIT_XOR1);
 104         kirkwood_register_gate("pex0",   CGC_BIT_PEX0);
 105         kirkwood_register_gate("pex1",   CGC_BIT_PEX1);
 106         kirkwood_register_gate("audio",  CGC_BIT_AUDIO);
 107         kirkwood_register_gate("tdm",    CGC_BIT_TDM);
 108         kirkwood_register_gate("tsu",    CGC_BIT_TSU);
 109
 110         /* clkdev entries, mapping clks to devices */
 111         orion_clkdev_add(NULL, "orion_spi.0", runit);
 112         orion_clkdev_add(NULL, "orion_spi.1", runit);
 113         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
 114         orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
 115         orion_clkdev_add(NULL, "orion_wdt", tclk);
 116 }
 117
 118 /*****************************************************************************
 119  * EHCI0
 120  ****************************************************************************/
 121 void __init kirkwood_ehci_init(void)
 122 {
 123         kirkwood_clk_ctrl |= CGC_USB0;
 124         orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
 125 }
 126
 127
 128 /*****************************************************************************
 129  * GE00
 130  ****************************************************************************/
 131 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
 132 {
 133         kirkwood_clk_ctrl |= CGC_GE0;
 134
 135         orion_ge00_init(eth_data,
 136                         GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
 137                         IRQ_KIRKWOOD_GE00_ERR);
 138 }
 139
 140
 141 /*****************************************************************************
 142  * GE01
 143  ****************************************************************************/
 144 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
 145 {
 146
 147         kirkwood_clk_ctrl |= CGC_GE1;
 148
 149         orion_ge01_init(eth_data,
 150                         GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
 151                         IRQ_KIRKWOOD_GE01_ERR);
 152 }
 153
 154
 155 /*****************************************************************************
 156  * Ethernet switch
 157  ****************************************************************************/
 158 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
 159 {
 160         orion_ge00_switch_init(d, irq);
 161 }
 162
 163
 164 /*****************************************************************************
 165  * NAND flash
 166  ****************************************************************************/
 167 static struct resource kirkwood_nand_resource = {
 168         .flags          = IORESOURCE_MEM,
 169         .start          = KIRKWOOD_NAND_MEM_PHYS_BASE,
 170         .end            = KIRKWOOD_NAND_MEM_PHYS_BASE +
 171                                 KIRKWOOD_NAND_MEM_SIZE - 1,
 172 };
 173
 174 static struct orion_nand_data kirkwood_nand_data = {
 175         .cle            = 0,
 176         .ale            = 1,
 177         .width          = 8,
 178 };
 179
 180 static struct platform_device kirkwood_nand_flash = {
 181         .name           = "orion_nand",
 182         .id             = -1,
 183         .dev            = {
 184                 .platform_data  = &kirkwood_nand_data,
 185         },
 186         .resource       = &kirkwood_nand_resource,
 187         .num_resources  = 1,
 188 };
 189
 190 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
 191                                int chip_delay)
 192 {
 193         kirkwood_clk_ctrl |= CGC_RUNIT;
 194         kirkwood_nand_data.parts = parts;
 195         kirkwood_nand_data.nr_parts = nr_parts;
 196         kirkwood_nand_data.chip_delay = chip_delay;
 197         platform_device_register(&kirkwood_nand_flash);
 198 }
 199
 200 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
 201                                    int (*dev_ready)(struct mtd_info *))
 202 {
 203         kirkwood_clk_ctrl |= CGC_RUNIT;
 204         kirkwood_nand_data.parts = parts;
 205         kirkwood_nand_data.nr_parts = nr_parts;
 206         kirkwood_nand_data.dev_ready = dev_ready;
 207         platform_device_register(&kirkwood_nand_flash);
 208 }
 209
 210 /*****************************************************************************
 211  * SoC RTC
 212  ****************************************************************************/
 213 static void __init kirkwood_rtc_init(void)
 214 {
 215         orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
 216 }
 217
 218
 219 /*****************************************************************************
 220  * SATA
 221  ****************************************************************************/
 222 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
 223 {
 224         kirkwood_clk_ctrl |= CGC_SATA0;
 225         if (sata_data->n_ports > 1)
 226                 kirkwood_clk_ctrl |= CGC_SATA1;
 227
 228         orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
 229 }
 230
 231
 232 /*****************************************************************************
 233  * SD/SDIO/MMC
 234  ****************************************************************************/
 235 static struct resource mvsdio_resources[] = {
 236         [0] = {
 237                 .start  = SDIO_PHYS_BASE,
 238                 .end    = SDIO_PHYS_BASE + SZ_1K - 1,
 239                 .flags  = IORESOURCE_MEM,
 240         },
 241         [1] = {
 242                 .start  = IRQ_KIRKWOOD_SDIO,
 243                 .end    = IRQ_KIRKWOOD_SDIO,
 244                 .flags  = IORESOURCE_IRQ,
 245         },
 246 };
 247
 248 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
 249
 250 static struct platform_device kirkwood_sdio = {
 251         .name           = "mvsdio",
 252         .id             = -1,
 253         .dev            = {
 254                 .dma_mask = &mvsdio_dmamask,
 255                 .coherent_dma_mask = DMA_BIT_MASK(32),
 256         },
 257         .num_resources  = ARRAY_SIZE(mvsdio_resources),
 258         .resource       = mvsdio_resources,
 259 };
 260
 261 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
 262 {
 263         u32 dev, rev;
 264
 265         kirkwood_pcie_id(&dev, &rev);
 266         if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
 267                 mvsdio_data->clock = 100000000;
 268         else
 269                 mvsdio_data->clock = 200000000;
 270         kirkwood_clk_ctrl |= CGC_SDIO;
 271         kirkwood_sdio.dev.platform_data = mvsdio_data;
 272         platform_device_register(&kirkwood_sdio);
 273 }
 274
 275
 276 /*****************************************************************************
 277  * SPI
 278  ****************************************************************************/
 279 void __init kirkwood_spi_init()
 280 {
 281         kirkwood_clk_ctrl |= CGC_RUNIT;
 282         orion_spi_init(SPI_PHYS_BASE);
 283 }
 284
 285
 286 /*****************************************************************************
 287  * I2C
 288  ****************************************************************************/
 289 void __init kirkwood_i2c_init(void)
 290 {
 291         orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
 292 }
 293
 294
 295 /*****************************************************************************
 296  * UART0
 297  ****************************************************************************/
 298
 299 void __init kirkwood_uart0_init(void)
 300 {
 301         orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
 302                          IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
 303 }
 304
 305
 306 /*****************************************************************************
 307  * UART1
 308  ****************************************************************************/
 309 void __init kirkwood_uart1_init(void)
 310 {
 311         orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
 312                          IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
 313 }
 314
 315 /*****************************************************************************
 316  * Cryptographic Engines and Security Accelerator (CESA)
 317  ****************************************************************************/
 318 void __init kirkwood_crypto_init(void)
 319 {
 320         kirkwood_clk_ctrl |= CGC_CRYPTO;
 321         orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
 322                           KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
 323 }
 324
 325
 326 /*****************************************************************************
 327  * XOR0
 328  ****************************************************************************/
 329 void __init kirkwood_xor0_init(void)
 330 {
 331         kirkwood_clk_ctrl |= CGC_XOR0;
 332
 333         orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
 334                         IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
 335 }
 336
 337
 338 /*****************************************************************************
 339  * XOR1
 340  ****************************************************************************/
 341 void __init kirkwood_xor1_init(void)
 342 {
 343         kirkwood_clk_ctrl |= CGC_XOR1;
 344
 345         orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
 346                         IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
 347 }
 348
 349
 350 /*****************************************************************************
 351  * Watchdog
 352  ****************************************************************************/
 353 void __init kirkwood_wdt_init(void)
 354 {
 355         orion_wdt_init();
 356 }
 357
 358
 359 /*****************************************************************************
 360  * Time handling
 361  ****************************************************************************/
 362 void __init kirkwood_init_early(void)
 363 {
 364         orion_time_set_base(TIMER_VIRT_BASE);
 365 }
 366
 367 int kirkwood_tclk;
 368
 369 static int __init kirkwood_find_tclk(void)
 370 {
 371         u32 dev, rev;
 372
 373         kirkwood_pcie_id(&dev, &rev);
 374
 375         if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
 376                 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
 377                         return 200000000;
 378
 379         return 166666667;
 380 }
 381
 382 static void __init kirkwood_timer_init(void)
 383 {
 384         kirkwood_tclk = kirkwood_find_tclk();
 385
 386         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
 387                         IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 388 }
 389
 390 struct sys_timer kirkwood_timer = {
 391         .init = kirkwood_timer_init,
 392 };
 393
 394 /*****************************************************************************
 395  * Audio
 396  ****************************************************************************/
 397 static struct resource kirkwood_i2s_resources[] = {
 398         [0] = {
 399                 .start  = AUDIO_PHYS_BASE,
 400                 .end    = AUDIO_PHYS_BASE + SZ_16K - 1,
 401                 .flags  = IORESOURCE_MEM,
 402         },
 403         [1] = {
 404                 .start  = IRQ_KIRKWOOD_I2S,
 405                 .end    = IRQ_KIRKWOOD_I2S,
 406                 .flags  = IORESOURCE_IRQ,
 407         },
 408 };
 409
 410 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
 411         .burst       = 128,
 412 };
 413
 414 static struct platform_device kirkwood_i2s_device = {
 415         .name           = "kirkwood-i2s",
 416         .id             = -1,
 417         .num_resources  = ARRAY_SIZE(kirkwood_i2s_resources),
 418         .resource       = kirkwood_i2s_resources,
 419         .dev            = {
 420                 .platform_data  = &kirkwood_i2s_data,
 421         },
 422 };
 423
 424 static struct platform_device kirkwood_pcm_device = {
 425         .name           = "kirkwood-pcm-audio",
 426         .id             = -1,
 427 };
 428
 429 void __init kirkwood_audio_init(void)
 430 {
 431         kirkwood_clk_ctrl |= CGC_AUDIO;
 432         platform_device_register(&kirkwood_i2s_device);
 433         platform_device_register(&kirkwood_pcm_device);
 434 }
 435
 436 /*****************************************************************************
 437  * General
 438  ****************************************************************************/
 439 /*
 440  * Identify device ID and revision.
 441  */
 442 char * __init kirkwood_id(void)
 443 {
 444         u32 dev, rev;
 445
 446         kirkwood_pcie_id(&dev, &rev);
 447
 448         if (dev == MV88F6281_DEV_ID) {
 449                 if (rev == MV88F6281_REV_Z0)
 450                         return "MV88F6281-Z0";
 451                 else if (rev == MV88F6281_REV_A0)
 452                         return "MV88F6281-A0";
 453                 else if (rev == MV88F6281_REV_A1)
 454                         return "MV88F6281-A1";
 455                 else
 456                         return "MV88F6281-Rev-Unsupported";
 457         } else if (dev == MV88F6192_DEV_ID) {
 458                 if (rev == MV88F6192_REV_Z0)
 459                         return "MV88F6192-Z0";
 460                 else if (rev == MV88F6192_REV_A0)
 461                         return "MV88F6192-A0";
 462                 else if (rev == MV88F6192_REV_A1)
 463                         return "MV88F6192-A1";
 464                 else
 465                         return "MV88F6192-Rev-Unsupported";
 466         } else if (dev == MV88F6180_DEV_ID) {
 467                 if (rev == MV88F6180_REV_A0)
 468                         return "MV88F6180-Rev-A0";
 469                 else if (rev == MV88F6180_REV_A1)
 470                         return "MV88F6180-Rev-A1";
 471                 else
 472                         return "MV88F6180-Rev-Unsupported";
 473         } else if (dev == MV88F6282_DEV_ID) {
 474                 if (rev == MV88F6282_REV_A0)
 475                         return "MV88F6282-Rev-A0";
 476                 else if (rev == MV88F6282_REV_A1)
 477                         return "MV88F6282-Rev-A1";
 478                 else
 479                         return "MV88F6282-Rev-Unsupported";
 480         } else {
 481                 return "Device-Unknown";
 482         }
 483 }
 484
 485 void __init kirkwood_l2_init(void)
 486 {
 487 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
 488         writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
 489         feroceon_l2_init(1);
 490 #else
 491         writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
 492         feroceon_l2_init(0);
 493 #endif
 494 }
 495
 496 void __init kirkwood_init(void)
 497 {
 498         printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
 499                 kirkwood_id(), kirkwood_tclk);
 500
 501         /*
 502          * Disable propagation of mbus errors to the CPU local bus,
 503          * as this causes mbus errors (which can occur for example
 504          * for PCI aborts) to throw CPU aborts, which we're not set
 505          * up to deal with.
 506          */
 507         writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
 508
 509         kirkwood_setup_cpu_mbus();
 510
 511 #ifdef CONFIG_CACHE_FEROCEON_L2
 512         kirkwood_l2_init();
 513 #endif
 514
 515         /* Setup root of clk tree */
 516         kirkwood_clk_init();
 517
 518         /* internal devices that every board has */
 519         kirkwood_rtc_init();
 520         kirkwood_wdt_init();
 521         kirkwood_xor0_init();
 522         kirkwood_xor1_init();
 523         kirkwood_crypto_init();
 524
 525 #ifdef CONFIG_KEXEC
 526         kexec_reinit = kirkwood_enable_pcie;
 527 #endif
 528 }
 529
 530 static int __init kirkwood_clock_gate(void)
 531 {
 532         unsigned int curr = readl(CLOCK_GATING_CTRL);
 533         u32 dev, rev;
 534
 535         kirkwood_pcie_id(&dev, &rev);
 536         printk(KERN_DEBUG "Gating clock of unused units\n");
 537         printk(KERN_DEBUG "before: 0x%08x\n", curr);
 538
 539         /* Make sure those units are accessible */
 540         writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
 541
 542         /* For SATA: first shutdown the phy */
 543         if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
 544                 /* Disable PLL and IVREF */
 545                 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
 546                 /* Disable PHY */
 547                 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
 548         }
 549         if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
 550                 /* Disable PLL and IVREF */
 551                 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
 552                 /* Disable PHY */
 553                 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
 554         }
 555
 556         /* For PCIe: first shutdown the phy */
 557         if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
 558                 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
 559                 while (1)
 560                         if (readl(PCIE_STATUS) & 0x1)
 561                                 break;
 562                 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
 563         }
 564
 565         /* For PCIe 1: first shutdown the phy */
 566         if (dev == MV88F6282_DEV_ID) {
 567                 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
 568                         writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
 569                         while (1)
 570                                 if (readl(PCIE1_STATUS) & 0x1)
 571                                         break;
 572                         writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
 573                 }
 574         } else  /* keep this bit set for devices that don't have PCIe1 */
 575                 kirkwood_clk_ctrl |= CGC_PEX1;
 576
 577         /* Now gate clock the required units */
 578         writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
 579         printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
 580
 581         return 0;
 582 }
 583 late_initcall(kirkwood_clock_gate);
 584
 585 void kirkwood_restart(char mode, const char *cmd)
 586 {
 587         /*
 588          * Enable soft reset to assert RSTOUTn.
 589          */
 590         writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
 591
 592         /*
 593          * Assert soft reset.
 594          */
 595         writel(SOFT_RESET, SYSTEM_SOFT_RESET);
 596
 597         while (1)
 598                 ;
 599 }