2 * arch/arm/mach-kirkwood/common.c
4 * Core functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/ata_platform.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/clk-provider.h>
19 #include <linux/spinlock.h>
22 #include <asm/timex.h>
23 #include <asm/kexec.h>
24 #include <asm/mach/map.h>
25 #include <asm/mach/time.h>
26 #include <mach/kirkwood.h>
27 #include <mach/bridge-regs.h>
28 #include <plat/audio.h>
29 #include <plat/cache-feroceon-l2.h>
30 #include <plat/mvsdio.h>
31 #include <plat/orion_nand.h>
32 #include <plat/ehci-orion.h>
33 #include <plat/common.h>
34 #include <plat/time.h>
35 #include <plat/addr-map.h>
36 #include <plat/mv_xor.h>
39 /*****************************************************************************
41 ****************************************************************************/
42 static struct map_desc kirkwood_io_desc[] __initdata = {
44 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
45 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
46 .length = KIRKWOOD_PCIE_IO_SIZE,
49 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
50 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
51 .length = KIRKWOOD_PCIE1_IO_SIZE,
54 .virtual = KIRKWOOD_REGS_VIRT_BASE,
55 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
56 .length = KIRKWOOD_REGS_SIZE,
61 void __init kirkwood_map_io(void)
63 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
67 * Default clock control bits. Any bit _not_ set in this variable
68 * will be cleared from the hardware after platform devices have been
69 * registered. Some reserved bits must be set to 1.
71 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
74 /*****************************************************************************
76 ****************************************************************************/
77 static DEFINE_SPINLOCK(gating_lock);
78 static struct clk *tclk;
80 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
82 return clk_register_gate(NULL, name, "tclk", CLK_IGNORE_UNUSED,
83 (void __iomem *)CLOCK_GATING_CTRL,
84 bit_idx, 0, &gating_lock);
87 void __init kirkwood_clk_init(void)
89 struct clk *runit, *ge0, *ge1;
91 tclk = clk_register_fixed_rate(NULL, "tclk", NULL,
92 CLK_IS_ROOT, kirkwood_tclk);
94 runit = kirkwood_register_gate("runit", CGC_BIT_RUNIT);
95 ge0 = kirkwood_register_gate("ge0", CGC_BIT_GE0);
96 ge1 = kirkwood_register_gate("ge1", CGC_BIT_GE1);
97 kirkwood_register_gate("sata0", CGC_BIT_SATA0);
98 kirkwood_register_gate("sata1", CGC_BIT_SATA1);
99 kirkwood_register_gate("usb0", CGC_BIT_USB0);
100 kirkwood_register_gate("sdio", CGC_BIT_SDIO);
101 kirkwood_register_gate("crypto", CGC_BIT_CRYPTO);
102 kirkwood_register_gate("xor0", CGC_BIT_XOR0);
103 kirkwood_register_gate("xor1", CGC_BIT_XOR1);
104 kirkwood_register_gate("pex0", CGC_BIT_PEX0);
105 kirkwood_register_gate("pex1", CGC_BIT_PEX1);
106 kirkwood_register_gate("audio", CGC_BIT_AUDIO);
107 kirkwood_register_gate("tdm", CGC_BIT_TDM);
108 kirkwood_register_gate("tsu", CGC_BIT_TSU);
110 /* clkdev entries, mapping clks to devices */
111 orion_clkdev_add(NULL, "orion_spi.0", runit);
112 orion_clkdev_add(NULL, "orion_spi.1", runit);
113 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".0", ge0);
114 orion_clkdev_add(NULL, MV643XX_ETH_NAME ".1", ge1);
115 orion_clkdev_add(NULL, "orion_wdt", tclk);
118 /*****************************************************************************
120 ****************************************************************************/
121 void __init kirkwood_ehci_init(void)
123 kirkwood_clk_ctrl |= CGC_USB0;
124 orion_ehci_init(USB_PHYS_BASE, IRQ_KIRKWOOD_USB, EHCI_PHY_NA);
128 /*****************************************************************************
130 ****************************************************************************/
131 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
133 kirkwood_clk_ctrl |= CGC_GE0;
135 orion_ge00_init(eth_data,
136 GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
137 IRQ_KIRKWOOD_GE00_ERR);
141 /*****************************************************************************
143 ****************************************************************************/
144 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
147 kirkwood_clk_ctrl |= CGC_GE1;
149 orion_ge01_init(eth_data,
150 GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
151 IRQ_KIRKWOOD_GE01_ERR);
155 /*****************************************************************************
157 ****************************************************************************/
158 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
160 orion_ge00_switch_init(d, irq);
164 /*****************************************************************************
166 ****************************************************************************/
167 static struct resource kirkwood_nand_resource = {
168 .flags = IORESOURCE_MEM,
169 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
170 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
171 KIRKWOOD_NAND_MEM_SIZE - 1,
174 static struct orion_nand_data kirkwood_nand_data = {
180 static struct platform_device kirkwood_nand_flash = {
181 .name = "orion_nand",
184 .platform_data = &kirkwood_nand_data,
186 .resource = &kirkwood_nand_resource,
190 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
193 kirkwood_clk_ctrl |= CGC_RUNIT;
194 kirkwood_nand_data.parts = parts;
195 kirkwood_nand_data.nr_parts = nr_parts;
196 kirkwood_nand_data.chip_delay = chip_delay;
197 platform_device_register(&kirkwood_nand_flash);
200 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
201 int (*dev_ready)(struct mtd_info *))
203 kirkwood_clk_ctrl |= CGC_RUNIT;
204 kirkwood_nand_data.parts = parts;
205 kirkwood_nand_data.nr_parts = nr_parts;
206 kirkwood_nand_data.dev_ready = dev_ready;
207 platform_device_register(&kirkwood_nand_flash);
210 /*****************************************************************************
212 ****************************************************************************/
213 static void __init kirkwood_rtc_init(void)
215 orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
219 /*****************************************************************************
221 ****************************************************************************/
222 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
224 kirkwood_clk_ctrl |= CGC_SATA0;
225 if (sata_data->n_ports > 1)
226 kirkwood_clk_ctrl |= CGC_SATA1;
228 orion_sata_init(sata_data, SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
232 /*****************************************************************************
234 ****************************************************************************/
235 static struct resource mvsdio_resources[] = {
237 .start = SDIO_PHYS_BASE,
238 .end = SDIO_PHYS_BASE + SZ_1K - 1,
239 .flags = IORESOURCE_MEM,
242 .start = IRQ_KIRKWOOD_SDIO,
243 .end = IRQ_KIRKWOOD_SDIO,
244 .flags = IORESOURCE_IRQ,
248 static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
250 static struct platform_device kirkwood_sdio = {
254 .dma_mask = &mvsdio_dmamask,
255 .coherent_dma_mask = DMA_BIT_MASK(32),
257 .num_resources = ARRAY_SIZE(mvsdio_resources),
258 .resource = mvsdio_resources,
261 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
265 kirkwood_pcie_id(&dev, &rev);
266 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
267 mvsdio_data->clock = 100000000;
269 mvsdio_data->clock = 200000000;
270 kirkwood_clk_ctrl |= CGC_SDIO;
271 kirkwood_sdio.dev.platform_data = mvsdio_data;
272 platform_device_register(&kirkwood_sdio);
276 /*****************************************************************************
278 ****************************************************************************/
279 void __init kirkwood_spi_init()
281 kirkwood_clk_ctrl |= CGC_RUNIT;
282 orion_spi_init(SPI_PHYS_BASE);
286 /*****************************************************************************
288 ****************************************************************************/
289 void __init kirkwood_i2c_init(void)
291 orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
295 /*****************************************************************************
297 ****************************************************************************/
299 void __init kirkwood_uart0_init(void)
301 orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
302 IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
306 /*****************************************************************************
308 ****************************************************************************/
309 void __init kirkwood_uart1_init(void)
311 orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
312 IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
315 /*****************************************************************************
316 * Cryptographic Engines and Security Accelerator (CESA)
317 ****************************************************************************/
318 void __init kirkwood_crypto_init(void)
320 kirkwood_clk_ctrl |= CGC_CRYPTO;
321 orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
322 KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
326 /*****************************************************************************
328 ****************************************************************************/
329 void __init kirkwood_xor0_init(void)
331 kirkwood_clk_ctrl |= CGC_XOR0;
333 orion_xor0_init(XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
334 IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
338 /*****************************************************************************
340 ****************************************************************************/
341 void __init kirkwood_xor1_init(void)
343 kirkwood_clk_ctrl |= CGC_XOR1;
345 orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
346 IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
350 /*****************************************************************************
352 ****************************************************************************/
353 void __init kirkwood_wdt_init(void)
359 /*****************************************************************************
361 ****************************************************************************/
362 void __init kirkwood_init_early(void)
364 orion_time_set_base(TIMER_VIRT_BASE);
369 static int __init kirkwood_find_tclk(void)
373 kirkwood_pcie_id(&dev, &rev);
375 if (dev == MV88F6281_DEV_ID || dev == MV88F6282_DEV_ID)
376 if (((readl(SAMPLE_AT_RESET) >> 21) & 1) == 0)
382 static void __init kirkwood_timer_init(void)
384 kirkwood_tclk = kirkwood_find_tclk();
386 orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
387 IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
390 struct sys_timer kirkwood_timer = {
391 .init = kirkwood_timer_init,
394 /*****************************************************************************
396 ****************************************************************************/
397 static struct resource kirkwood_i2s_resources[] = {
399 .start = AUDIO_PHYS_BASE,
400 .end = AUDIO_PHYS_BASE + SZ_16K - 1,
401 .flags = IORESOURCE_MEM,
404 .start = IRQ_KIRKWOOD_I2S,
405 .end = IRQ_KIRKWOOD_I2S,
406 .flags = IORESOURCE_IRQ,
410 static struct kirkwood_asoc_platform_data kirkwood_i2s_data = {
414 static struct platform_device kirkwood_i2s_device = {
415 .name = "kirkwood-i2s",
417 .num_resources = ARRAY_SIZE(kirkwood_i2s_resources),
418 .resource = kirkwood_i2s_resources,
420 .platform_data = &kirkwood_i2s_data,
424 static struct platform_device kirkwood_pcm_device = {
425 .name = "kirkwood-pcm-audio",
429 void __init kirkwood_audio_init(void)
431 kirkwood_clk_ctrl |= CGC_AUDIO;
432 platform_device_register(&kirkwood_i2s_device);
433 platform_device_register(&kirkwood_pcm_device);
436 /*****************************************************************************
438 ****************************************************************************/
440 * Identify device ID and revision.
442 char * __init kirkwood_id(void)
446 kirkwood_pcie_id(&dev, &rev);
448 if (dev == MV88F6281_DEV_ID) {
449 if (rev == MV88F6281_REV_Z0)
450 return "MV88F6281-Z0";
451 else if (rev == MV88F6281_REV_A0)
452 return "MV88F6281-A0";
453 else if (rev == MV88F6281_REV_A1)
454 return "MV88F6281-A1";
456 return "MV88F6281-Rev-Unsupported";
457 } else if (dev == MV88F6192_DEV_ID) {
458 if (rev == MV88F6192_REV_Z0)
459 return "MV88F6192-Z0";
460 else if (rev == MV88F6192_REV_A0)
461 return "MV88F6192-A0";
462 else if (rev == MV88F6192_REV_A1)
463 return "MV88F6192-A1";
465 return "MV88F6192-Rev-Unsupported";
466 } else if (dev == MV88F6180_DEV_ID) {
467 if (rev == MV88F6180_REV_A0)
468 return "MV88F6180-Rev-A0";
469 else if (rev == MV88F6180_REV_A1)
470 return "MV88F6180-Rev-A1";
472 return "MV88F6180-Rev-Unsupported";
473 } else if (dev == MV88F6282_DEV_ID) {
474 if (rev == MV88F6282_REV_A0)
475 return "MV88F6282-Rev-A0";
476 else if (rev == MV88F6282_REV_A1)
477 return "MV88F6282-Rev-A1";
479 return "MV88F6282-Rev-Unsupported";
481 return "Device-Unknown";
485 void __init kirkwood_l2_init(void)
487 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
488 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
491 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
496 void __init kirkwood_init(void)
498 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
499 kirkwood_id(), kirkwood_tclk);
502 * Disable propagation of mbus errors to the CPU local bus,
503 * as this causes mbus errors (which can occur for example
504 * for PCI aborts) to throw CPU aborts, which we're not set
507 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
509 kirkwood_setup_cpu_mbus();
511 #ifdef CONFIG_CACHE_FEROCEON_L2
515 /* Setup root of clk tree */
518 /* internal devices that every board has */
521 kirkwood_xor0_init();
522 kirkwood_xor1_init();
523 kirkwood_crypto_init();
526 kexec_reinit = kirkwood_enable_pcie;
530 static int __init kirkwood_clock_gate(void)
532 unsigned int curr = readl(CLOCK_GATING_CTRL);
535 kirkwood_pcie_id(&dev, &rev);
536 printk(KERN_DEBUG "Gating clock of unused units\n");
537 printk(KERN_DEBUG "before: 0x%08x\n", curr);
539 /* Make sure those units are accessible */
540 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
542 /* For SATA: first shutdown the phy */
543 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
544 /* Disable PLL and IVREF */
545 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
547 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
549 if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
550 /* Disable PLL and IVREF */
551 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
553 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
556 /* For PCIe: first shutdown the phy */
557 if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
558 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
560 if (readl(PCIE_STATUS) & 0x1)
562 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
565 /* For PCIe 1: first shutdown the phy */
566 if (dev == MV88F6282_DEV_ID) {
567 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
568 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
570 if (readl(PCIE1_STATUS) & 0x1)
572 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
574 } else /* keep this bit set for devices that don't have PCIe1 */
575 kirkwood_clk_ctrl |= CGC_PEX1;
577 /* Now gate clock the required units */
578 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
579 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
583 late_initcall(kirkwood_clock_gate);
585 void kirkwood_restart(char mode, const char *cmd)
588 * Enable soft reset to assert RSTOUTn.
590 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
595 writel(SOFT_RESET, SYSTEM_SOFT_RESET);